[gem5-dev] Removing CSR Instruction Fixes in gem5

Hello, We are pushing a change to remove patches 67717 (arch-riscv: Fix the CSR instruction behavior.) and 67897 (arch-riscv: Fix the behavior of write to status CSR), as they

[gem5-dev] Changes to stats output within gem5

Hello, I am currently working on introducing a change to the way stats output within gem5. Currently, certain stats output under different names depending on the CPU, such as insts in the O3 CPU versus numInsts in the Simple CPU. Additionally, other stats only output in certain CPUs when they may

[gem5-dev] Changes to stats output

Hello, I have submitted a changeset to gem5 that will alter the way stats output at the end of the simulation. These changes unify stats with similar names from different CPUs, such as insts in the O3 CPU versus numInsts in the Simple CPU. It also moves some stats that are only located in specifi

[gem5-dev] [Important Announcement] gem5 Migration from Gerrit to GitHub

Dear gem5-dev community, We are writing to you to inform you that the migration of gem5 from Gerrit to GitHub will be taking place on Monday, July 10. At this point in time, Gerrit will become read-only, and the repository will be hosted at https://github.com/gem5/gem5. Any changes made to Gerri