Hello All,
I'm trying to compile and install PCB (version 20091103) and I have an
question.
I have created two (/home/me/tools/bin, /home/me/tools/share) directories.
Then I use:
./configure --prefix=/home/me/tools/ --with-exporters="ps gerber nelma bom
png"
make
make install
So far so good.
PCB
Hello All,
I have re-compiled pcb using the same commands and for some reason all
is OK now. I have the standard footprint libraries available.
I have no idea what when wrong, but sorry to waste your time with this.
Regards, Robert
-Original Message-
From: my...@iae.nl
Reply-to: gEDA u
:
make install
from the top level directory.
^^
Forgot to cd .. back to the top level dir. for the make install.
Again sorry to waste your time.
Regards, Robert
-Original Message-
From: myken
Reply-to: gEDA user mailing list
To: gEDA user mailing list
Subject: Re: gEDA-user
Thanks Dan,
I have found my mistake, see previous posting.
Robert.
-Original Message-
From: Dan McMahill
Reply-to: gEDA user mailing list
To: gEDA user mailing list
Subject: Re: gEDA-user: Compiling PCB 20001103 -> missing libraries
Date: Thu, 25 Mar 2010 23:16:30 -0400
Mailer: Thunde
Hello All,
Sorry to bother you again with a novice question. I'm in the proces of
understanding PCB so please be gentle.
I have a component (DPAK) on the top (component) side of my pcb,
surrounded by a polygon. I have connected one pad to the polygon by
using copper trackes. I also have a polygon
> I think your question concerns solder mask, not copper clearance. So you
> can use the "Solder Mask" button on the left (GTK) to make solder mask
> relief visible.
>
> If you need this via as thermal via for parts with thermal center pad,
> and you want a rectangular shape: You may use a footpri
Sorry I was to quick with my comment.
> The relevant code is in src/strflags.c, although I'll warn you.. I felt
> compelled to gouge out my eyes after trying to read it.
>
Mmm, yes this will keep me quiet for some time. Nevertheless, thanks.
___
geda
I don't fully understand the source code and I don't know if anyone is
interested but this is what I found.
Apparently there are 5 types of thermals:
1. a X shape with straight spokes
2. a X shape with round spokes
3. a + shape with straight spokes
4. a + shape with round spokes
5. a solid shape
Hello all,
I want to use a component with the attached footprint.
Is it possible to make a footprint with an arc inside?
Any help appreciated.
Regards, Robert
<>
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8:04 +, Kai-Martin Knaak wrote:
> On Mon, 29 Mar 2010 11:29:34 +0200, myken-kVLBEChPVFc wrote:
>
> > Is it possible to make a footprint with an arc inside?
>
> Not with "real" arcs, but arbitrarily close. The pads of footprints can
> be composed of multiple straigh
If you hover above a pad and hit the "F" key (Find Connections) all
connections that are attached to that pad will be marked.
It helps me to find out which pad is connected to what without the use of
the schematic.
I hope I understand your problem correctly.
Robert.
Yes, but when there are multip
> This wiki page might be useful:
> http://geda.seul.org/wiki/geda:pcb-quick_reference
> It is more complete than the online help in the menu.
I have looked at the wiki page above and found difference with my
(standard) configuration.
\ thin-draw toggles thin draw mode
for me it only works with
sh
Please take a look here: http://geda.seul.org/wiki/geda:csygas
I had trouble in the past with gEDA <-> SPICE because of the rule:
Note that if the file holds a .MODEL, the refdes should start with U; if
the file holds a .SUBCKT, the refdes should start with X.
If the refdes starts with D SPICE w
in gschem add the following items to your symbol:
* devive: 1N750
* model-name: 1n750
(or whatever the name of the model is called inside your spice model)
Look at your spice file for something like
.MODEL 1n750 d
^-> this is the model-name attribute (upper and lower case do
matter)
an
Hello all,
I was playing around with a suggestion Kai-Martin has made in a previous
post "Re: gEDA-user: gsch2pcb to pcb error".
Being: "You can assemble frequently needed subcircuits in a special
symbol and add them with one click to your sheet."
So I took a fresh sheet, removed the titleblock,
rnaud wrote:
> Hello Robert,
>
> myken writes:
> > [...]
> > So I took a fresh sheet, removed the titleblock, added sum components
> > ("include_component_as_individual_objects"), added sum nets, then I did
> > a symbol translate (=0) and
Hello Nikos,
The net attribute inside a symbol has the form
net=signalname:pinname,pinname,pinname
Please also see: http://www.geda.seul.org/wiki/geda:na_howto
In your case pin 1 and pin 3V are both connected to VCC.
So probably you want something like net=3V:1 or net=3V:pwr
If you instantiate a
Ladies and Gentlemen,
I need some assistance with a DRC error.
The file attached produces a DRC error (Copper areas too close). However
if I disconnect the large polygon from D203 (hover over the polygon and
press "s") the DRC error disappears.
But the weird thing is that if I do not disconnect th
Hello DJ,
Sorry, almost but not quite. If I apply the patch the DRC error in the
original file disappears, but if I move the small polygon to the larger
one keeping 6 mill distance no DRC error reappears. (DRC distance is set
to 10 mill). If I make the distance between the two 5 mill then I get a
Hello all,
On Thu, 2010-12-09 at 21:55 +1100, Stephen Ecob wrote:
> > I'm aiming to finish University in a few months.. if people would
> > like to fund work on the toporouter, then I would be pretty keen to
> > work on it full time.
> >
> > Regards,
> > Anthony
>
> Good, we've established that
Hello all,
I was wondering if it is possible to add more information to the
fabrication layer output of the gerber export (*.fab).
I like to add the copper thickness for that specific pcb (preferably for
ever layer individually (inner/outer layer)).
Thanks,
Robert.
_
I'm using Time Tracker (Project Hamster)
http://projecthamster.wordpress.com/
It's a gnome applet. Very easy to use.
Billing I do through the TSV file save output.
Just my $0.02
Robert.
On 02/02/11 14:43, Bob Paddock wrote:
On Sun, Jan 30, 2011 at 7:26 PM, Darryl Gibson wrote:
I'm curious w
Hello all,
I didn't see any reply on my question so I guess the very busy and
overloaded knowledge base of this list didn't find the time to look at
it, so please consider this a friendly reminder ;-)
Or am I asking a very silly question? (didn't find a answer by google)
The question was:
I
On 25/03/11 07:36, yamazakir2 wrote:
Anybody know of a source, other than digikey, that sells prefabbed
prewound SMPS transformers? Digikey has a few, but their selection
pretty limited.
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http://www.s
Great!
Well done!
And pictures would be nice.
Robert.
On 23/05/11 03:57, John Doty wrote:
Well, here I am in Osaka. It's Monday morning, and I just saw the prototype
Soft X-ray Imager (SXI) for the ASTRO-H space mission under test. Much of the
electronics, a large, complex circuit board and s
How we organize the data, and how the user interacts with it, need not
be the same :-)
I didn't read the complete threat so if I miss the point or if I repeat
anyone I'm sorry.
Is it not possible to make a top level program that launches the
different programs (gschem, pcb, simtools, .)?
What I think users want is to have the underlying tools be more aware
of the other sources of data in the design, and each other, so that
the GUIs appear to be more integrated despite being individual tools
and datasets underneath. This may require some high-level "these are
the files in your d
Thanks DJ,
I had the same thought that Vx was floating somewhere unwanted, that's
why I added the resistor (which didn't work).
Gazing at this problem for a couple of days make me miss the obvious,
just split the filter. Brilliant.
I'll give it a try.
Robert.
On 16/06/11 20:48, DJ Delorie wr
.
I will try the options suggested in this list today.
Robert.
On 17/06/11 04:13, gene glick wrote:
On 06/16/2011 02:30 PM, myken wrote:
Hello all,
I would appreciate some expert advice.
Are you trying to make a low current power supply?
I agree with DJ - the unequal loading on + and - cycle
Hello all,
As a remark on your observation Andy I would like to say in my defence
that I simplified and reduced the problem/information simply to avoid
wasting anyones time with details and (in my opinion) irrelevant side
effects. That the two load resistors are in fact a representation of two
co
Vcc and Vss are still sensitive to load. So if the design requires
both Vss and Vee be equal and opposite, then it needs regulation -
zener, for example.
Your absolutely right, but that's what comes next. It is the regulators
how create the difference in load balance.
___
Hallo all,
I'm new to this mailinglist so please be gentle.
My question:
Is it possible to make a net thicker in gschem (not a line but a net).
I want to indicate in my schematic than the net is a high current power
net.
Thanks for your answers.
Best regards, Robert.
who can tell you about
some of the other ways that you can customise gEDA but I hope this
gets you off in the right direction.
Cheers,
Andy.
http://signality.co.uk
2009/9/3 myken :
> Hallo all,
>
> I'm new to this mailinglist so please be gentle.
>
> My question:
&
Hello All,
I was just wondering, is there any documentation on how the autorouter
of PCB is implemented? Restrictions, strategy, information used, hooks,
alternatives, etc.
Is there an active development in that area?
Just to explain: I am using gEDA/PCB professionally but I do the routing
by ha
Hello all,
I did an oval shape hole once by using three overlapping round drill
holes, worked fine. maybe you can do the same with 6 small round holes:
ooo
ooo
ooo
Cheers, Robert
-Original Message-
From: Dave N6NZ
Reply-to: gEDA user mailing list
To: gEDA user mailing list
Subject: Re
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