On Tue, Mar 9, 2010 at 8:44 PM, DJ Delorie wrote:
[...]
> Committed, thanks!
Thank you :)
Steve
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On Tue, Mar 16, 2010 at 6:34 AM, gene glick wrote:
>> So now the question is "Who else will pledge money?".
Sure, happy to contribute.
Stephen
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On Sat, Jun 26, 2010 at 10:33 PM, gene glick wrote:
> can anyone recommend a viewer for these drawings?
I like QCad community edition. DXF is its native format, and it can
edit as well as view.
Stephen
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I've hit a strange bug in PCB20100929. I've logged it on sourceforge
as ID: 3103250:
The attached element (250mOhm 4 terminal resistor) became corrupted
following autorouting and trace optimisation with PCB20100929.
Loading the .pcb file in a text editor shows that the element
ResCu250mOhm is pre
On Fri, Nov 5, 2010 at 10:40 AM, DJ Delorie wrote:
>
> I've seen something similar with an SMT inductor footprint made of 5
> pcb pads per inductor pad.
OK, it's not just me :)
I'll investigate further, perhaps I'll be able narrow it down to the
autorouter or one of the trace optimisers.
__
On Fri, Nov 5, 2010 at 10:50 AM, Stephen Ecob
wrote:
> On Fri, Nov 5, 2010 at 10:40 AM, DJ Delorie wrote:
>>
>> I've seen something similar with an SMT inductor footprint made of 5
>> pcb pads per inductor pad.
>
> OK, it's not just me :)
> I'll inv
On Mon, Nov 8, 2010 at 3:47 AM, DJ Delorie wrote:
>
> Just FYI I'm working on PCB all day today. Join me in IRC if you want
> to help.
Hi DJ, am I too late to catch your PCB day ? Time zone difference can
be a killer!
I'm working on fixing bug tracker bug #3103250. I've tracked it down
to djop
Problem fixed with the following patch, now listed on the sourceforge
tracker as #3105670
diff --git a/src/djopt.c b/src/djopt.c
index 240b86b..7a1a315 100644
--- a/src/djopt.c
+++ b/src/djopt.c
@@ -2851,6 +2851,9 @@ padcleaner ()
if (layer_type[l->layer] != layerflag)
On Wed, Nov 10, 2010 at 8:36 AM, Kai-Martin Knaak
wrote:
> Colin D Bennett wrote:
>
>> The startup messages are a little annoying,
>> but when I hit 'o' and get a barrage of dozens of "shorted net"
>> warnings, etc., it's basically unusable.
>
> I have installed many versions of pcb but have never
On Fri, Nov 12, 2010 at 9:31 AM, wrote:
> I think the 2000 dpi output is great!
>
> You coding wizards can do in a minute what would take me a month, but I
> would like to try writing a g-code to dxf conversion program in C. Thanks,
> Stephen Ecob for the jump start!
>
> S
aces" has the PCBs
with existing traces and planes removed to allow autorouter trials.
Notes
* autorouting now breaks undo -> please save your PCB somewhere safe
before experimenting with this branch
* A menu checkbox "Settings->Disable 2008 autoroute
On Mon, Nov 15, 2010 at 1:37 PM, Peter Clifton wrote:
> An actual rendering from PCB+GL with some code I've been playing with...
>
> http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d_packages_mockup.png
>
>
> Not currently pushed to any repository, this hard-codes a search for
> ACY400 foo
On Tue, Nov 16, 2010 at 12:47 AM, Kai-Martin Knaak
wrote:
> Stephen Ecob wrote:
>
>> Motivation
>> Having laid out a couple of boards with PCB 20091103 I became aware of
>> some bugs in the autorouter that made the job difficult:
>
> Are you talking about the default
On Tue, Nov 16, 2010 at 9:52 PM, Jan Martinek wrote:
> On 11/15/2010 09:24 PM, Stephen Ecob wrote:
>>
>> On Tue, Nov 16, 2010 at 12:47 AM, Kai-Martin Knaak
>> wrote:
>>>
>>> Stephen Ecob wrote:
>>>
>>>> Motivation
>>>>
On Tue, Nov 16, 2010 at 10:09 PM, timecop wrote:
> With TopoR having a freeware version for 2 layers and up to 256 nets
> (or some other fairly high for 'hobby' use limitation), there's not
> really any point on bothering improving built in autorouter...
> Does PCB have Specctra DSN/SES export/imp
2009. This made it work
better in many cases, but in some cases the older version works
better. My branch of PCB includes both versions. I often try both
autorouters and keep the best results.
How to get it?
git clone git://repo.or.cz/geda-pcb/see.git
cd see
./autogen.sh
./configure
make
src/pcb
Enjoy!
Stephen Ecob
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On Thu, Nov 25, 2010 at 2:59 AM, DJ Delorie wrote:
>
> The menus are defined by a resource file, you might have one in ~/.pcb
> that overrides the freshly-installed version.
Oh, my mistake: I forgot to commit my changes to the resource file
src/gpcb-menu.res
I've now done a git push that adds thi
You can tell which resource file PCB is using for its menus by opening
the "Window -> Message Log" window after start up. You'll see
something like this:
Loading menus from /usr/local/share/pcb/gpcb-menu.res
or
Using default menus (if it can't find a menu resource file)
My updated gpcb-menu.
On Thu, Nov 25, 2010 at 9:38 AM, Jan Martinek wrote:
> Yes, now it works :-) I tried to run the autorouter, but it ate all my
> memory after several minutes.
Yes, for the PCB I'm currently working on I lose around 1MB per run of
the autorouter.
I set up the dmalloc library to investigate, but un
>> Moreover, it uses layers which are disabled.
>> And one thing - even if I select thicker traces (for example Power), it
>> still uses default thickness (Signal).
>
> Yes, I'm working on a fix for these problems.
These problems are now solved with my most recent git push.
It also now updates the
On Fri, Nov 26, 2010 at 1:50 AM, Hannu Vuolasaho wrote:
> I'm waiting to see some screencasts (resistor pr0n again) how this is
> working but I was wondering is it possible to run HE autorouter to
> optimize vias?
Since you ask!
http://commons.wikimedia.org/wiki/File:HighEffortDemo1.ogv
h
On Fri, Nov 26, 2010 at 6:10 PM, Hannu Vuolasaho wrote:
> > And yes, I'll make a change before my next commit so that
> optimisation
> > for minimum vias is also possible.
> Beatiful. I so see how one takes all the PCB files, exports jpg and
> makes them video. Very hot stuff in product
On Fri, Nov 26, 2010 at 11:30 PM, Peter Clifton wrote:
> How to you get it to draw updates as the auto-router progresses?
Actually, I disable draw updates during each individual run of the
autorouter using the usual LIVEROUTEFLAG + HID_LIVE_DRAWING mechanism.
I only update the display when a sup
Oh, BTW, what are your thoughts for processes & threads with PCB+GL ?
For my HE autorouter hack I have in mind to fork() off extra processes
so that all of my CPU cores can run separate autorouter instances. As
HE has an unbounded run time I'm thinking that the main PCB process
should simply hang
On Fri, Dec 3, 2010 at 10:30 AM, Peter Clifton wrote:
> As I see it, PCB priorities (for me at least) are approximately:
>
> Release?
> Merge 2D parts of PCB+GL drawing
> Release?
> Merge 3D parts of PCB+GL drawing
> GUI to control PCB+GL rendering styles
> Release?
Before that first release on
I don't think chamfering is available. Other related features are
available though:
Mitering is available from Connects->Optimize routed tracks->Miter.
Only works for intersections with one vertical trace meeting one
horizontal trace.
A "puller" is available from Connects->Optimize routed tracks->
On Sun, Dec 5, 2010 at 2:20 AM, Peter Clifton wrote:
> On Sat, 2010-12-04 at 11:15 +1100, Stephen Ecob wrote:
branch.. sorry).
[...]
> So, a mix of NOT LEAKS, and "might be leaks". We need back-traces of the
> cases where callers are allocating things repeatedly and not free
On Mon, Dec 6, 2010 at 9:28 AM, George M. Gallant, Jr.
wrote:
> Well that was interesting. The tracks->Miter made it look very sloppy
> and the completely hung PCB. Using version 20100929.
"look very sloppy" - could you be more specific ?
A couple of notes on using the Miter function:
* autoroute
If you use (or intend to use) lib dmalloc with PCB you will find the
following useful.
I've uploaded a patch against current heaad to sourceforge, ID
#3129279, described as follows:
PCB supports the use of the dmalloc library as a configuration option.
This patch makes the PCB source code more "f
On Tue, Dec 7, 2010 at 12:31 AM, Peter Clifton wrote:
> On Mon, 2010-12-06 at 16:58 +1100, Stephen Ecob wrote:
>> If you use (or intend to use) lib dmalloc with PCB you will find the
>> following useful.
>>
>> I've uploaded a patch against current heaad to source
On Tue, Dec 7, 2010 at 11:48 AM, Peter Clifton wrote:
> On Tue, 2010-12-07 at 10:04 +1100, Stephen Ecob wrote:
>
>> Dropping the (a) ? (a) : 1 foolishness would be cleaner, but could
>> expose latent bugs in the 71 callers of the mymem allocators.
>> I'm happy to proc
I count 54 locations in head that call MyStrdup()
A run time check of calls to MyStrdup() shows:
create.c:197 made 0 NULL calls, 48 good calls
create.c:219 made 0 NULL calls, 32 good calls
create.c:238 made 0 NULL calls, 1 good calls
create.c:240 made 0 NULL calls, 1 good calls
create.c:286 made 1
I propose the following solution:
1. replace all calls to MyCalloc() with calls to calloc()
2. replace all calls to MyMalloc() with calls to malloc()
3. replace all calls to MyRealloc() with calls to realloc()
4. replace all calls to SaveFree() with calls to free()
5. retain the MYFREE() macro as
On Tue, Dec 7, 2010 at 3:06 PM, timecop wrote:
>> 5. retain the MYFREE() macro as its pointer clearing side effect is required
>> 8. Instead of simply retaining MYFREE(p) (point 5), we could replace
>> each use of it with an explicit:
>> free(p);
>> p = NULL;
>
> Is this "MY" prefix actually in
I just submitted a patch for some memory leaks that have been annoying
me. The soureforge id is #3131063:
https://sourceforge.net/tracker/?func=detail&aid=3131063&group_id=73743&atid=538813
Most users won't have noticed these leaks as only around 1MB is leaked
each time a new PCB is loaded. The
> Agreed, and I had a similar experience. I was hoping to get a review or just
> some comments on a couple of patches I submitted (3114991, 3117075). Now I
> can understand that it was probably in an off beat area and not the topic du
> jour, so I went ahead and posted it to the patches tracker. No
On Wed, Dec 8, 2010 at 12:52 AM, Peter Clifton wrote:
> Note that the second patch gets my test PCB loading again, but does not
> consider every possible case.
>
> Before committing, these MUST be squashed, but it is convenient to keep
> them separate for now.
>
> Thinking about it, a pre-patch co
On Wed, Dec 8, 2010 at 4:51 AM, Peter Clifton wrote:
> Stephen, I'd appreciate your Acked-by: or Reviewed-by: on the attached
> patches:
Patch 0001 is good, but I can suggest some additional MyStrdup() calls
that can safely be directly replaced with strdup():
create.c
196: safe because DefaultLa
Regarding 0002-Not-so-sure-about-these-MyStrdup-calls.patch:
buffer.c:984: I can't tell, and suggest playing it safe with STRDUP()
create.c:593: My $0.02: CreateNewText() called with a NULL pointer
should be stopped in its tracks with a segfault rather than
propagating the error. If you're unsure
Patch0002: we're getting close. I see only one remaining issue:
create.c:900: you address this both in patch 0001 and patch 0002
In patch 0001 you preserve the behaviour of the existing code
In patch 0002 you unconditionally call strdup()
I've looked at the code further, and I think that the appro
On Thu, Dec 9, 2010 at 12:10 AM, Peter Clifton wrote:
> On Wed, 2010-12-08 at 13:40 +1100, Stephen Ecob wrote:
>> Regarding 0002-Not-so-sure-about-these-MyStrdup-calls.patch:
>>
>> buffer.c:984: I can't tell, and suggest playing it safe with STRDUP()
>
> if (li
On Thu, Dec 9, 2010 at 12:24 AM, Peter Clifton wrote:
> On Wed, 2010-12-08 at 14:26 +1100, Stephen Ecob wrote:
>> Patch0002: we're getting close. I see only one remaining issue:
>>
>> create.c:900: you address this both in patch 0001 and patch 0002
>> In patch 00
On Thu, Dec 9, 2010 at 4:22 AM, Kai-Martin Knaak
wrote:
> Hi.
> Thanks to the little scheme script print.scm distributed with geda,
> I finally managed to do non-interactive print of more complex projects.
> Attached to this mail you can find a little script that descends recursively
> down a hier
On Thu, Dec 9, 2010 at 5:52 AM, DJ Delorie wrote:
>
>> Yes, it will be fine. A pad must always have a valid number.
>
> Um, no?
>
>> Oh yes, my mistake - I forgot that there are two calls on adjacent
>> lines. strdup (Number) should be fine as a pin must always have a
>> number.
>
> Again... Um,
On Thu, Dec 9, 2010 at 5:58 AM, DJ Delorie wrote:
>
>> quick read about gschem's approach to multiple page schematics quickly
>> convinced me that I'd rather shrink my symbols and keep to one page
>
> You don't need to shrink your symbols. Symbols don't have an absolute
> size like footprints - t
On Thu, Dec 9, 2010 at 6:56 AM, DJ Delorie wrote:
>
> Anything that's STRING in parse_y.y starts off as NULL if it's the ""
> string. This is done in parse_l.l.
My assumption was wrong, thanks for spotting that DJ.
Peter, as a consequence:
create.c:789 should use STRDUP() to support NULL pin Num
Sorry about that :-(
I've created a patch which fixes it, sourceforge patch ID 3132699:
https://sourceforge.net/tracker/?func=detail&aid=3132699&group_id=73743&atid=538813
FixSmash.patch
Description: Binary data
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Boiling it down greatly, Clif and Kaimartin are both asking for more
attention from the maintainers. Has the gEDA community given thought
to the possibility of paid maintainers ? I'm a relative newbie,
please let me know if this has already been thrashed through. If it
is worth discussing, I gue
On Thu, Dec 9, 2010 at 2:59 PM, DJ Delorie wrote:
>
> If you want to hire a maintainer, consider that the average senior
> engineer costs about $200k per year, if you include benefits - and if
> you want a full time engineer, you'd have to provide them because
> you'd be replacing their regular jo
On Thu, Dec 9, 2010 at 3:11 PM, DJ Delorie wrote:
>
>> * You wrote the very useful visual DRC system with some financial help
>> from Linux Fund.
>
> No, I did the schematic importer.
Sorry, I must have misunderstood - that was the impression I got from
reading this page:
http://www.linuxfund.or
On Thu, Dec 9, 2010 at 3:16 PM, DJ Delorie wrote:
>
> There were a bunch of projects scheduled, but even LF couldn't
> generate enough funding for more than one of them.
I'm sorry to hear that :(
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htt
On Thu, Dec 9, 2010 at 7:06 PM, Peter Brett wrote:
>> 1. Would any of the existing maintainers be able to devote more time
>> to gEDA if they had financial support to do so ?
>
> In my case: yes. :-/
>
> Peter
OK, so that's a 'yes' for question 1!
Now for question 2 - money.
A few weeks
On Thu, Dec 9, 2010 at 7:46 PM, uv wrote:
> Dears,
>
> Is there any simple way to hide all component numbers on the board?
>
> Thank you
>
> Péter Papp
Yes:
1. Select all (Alt+A or use the menu Edit -> Select all visible)
2. Enter command mode by typing :
3. Type the command ToggleHideName(Selec
> I'm aiming to finish University in a few months.. if people would
> like to fund work on the toporouter, then I would be pretty keen to
> work on it full time.
>
> Regards,
> Anthony
Good, we've established that money could help to improve gEDA :) What
I'm *very* unsure of is whether we could
> I'd welcome feedback from people who actively encounter and report bugs
> (especially in favour of the move ;)).
>
> I'd also welcome feedback from anyone who works with bug reports, test
> patches, merge code etc... (Doesn't have to be with gEDA / PCB, anything
> regarding Launchpad / SourceForg
On Fri, Dec 10, 2010 at 9:45 AM, myken wrote:
>> fund a full time developer. But it's nothing more than a pipe dream
>> unless there are others out there who think the same.
>> Does anyone else think the same ?
>
> I think the same, but I am also in the same position (start-up, tight
> cashflow)
On Fri, Dec 10, 2010 at 10:27 AM, wrote:
> How about a Kickstarter project for the toporouter? Let Anthony make
> a proposal and put it on www.kickstarter.com, and then gEDA users can
> pledge donations. If it raises enough money by graduation (or
> whatever other deadline), then we all fund An
On Fri, Dec 10, 2010 at 2:09 PM, Peter Clifton wrote:
> On Fri, 2010-12-10 at 11:26 +1100, Stephen Ecob wrote:
>> Hi Peter,
>> Here's my patch that should be equivalent to your patches 0001
>> followed by 0002.
>> My patch
On Fri, Jan 14, 2011 at 7:22 AM, Tamas Szabo wrote:
> I made a loop antenna (for ZigBee too), same problem. I ignore DRC.
>
> There was a thread about it, maybe a year ago or more, without any good
> solution.
I've had similar problems when making low value resistors out of
copper tracks and whe
> Perhaps I was going a bit far to suggest full DRC for the actual antenna
> design. What I really meant was not loosing information for net
> connectivity checking leading up the antenna.
Thinking longer term, why not support DRC checking of inductance and
resistance for specially tagged traces ?
> A similar "track is component" scenario:
>
> PCB fuse track - a dirty trick I've seen in some Honywell boiler
> controllers.. where a deliberately thin trace is used to act as a fuse.
That certainly is a dirty trick! (But on a very tight budget it could
make sense).
So there are several use cas
> Similar to the last is a jumper location that is connected by copper by
> default to be cut if an open is needed. Consider this to be a 1 bit PROM.
>
> Rick
Yes, they're useful. I use them a lot on early revision boards when
the design is still subject to change in some areas.
__
> Flux is the secret... Applying flux is the crucial step to success.
+1
Get yourself some good quality flux, it makes this sort of problem disappear.
I've used Electrolube SMFL (aerosol with dispenser tube) with good
results, but there are many good options. Look for something with
"surface moun
> The main problem I have is not code, but deciding what such geometry
> needs to look like it and how to specify it. Whatever we decide we have
> to live with, as we can't go changing geometry on users with existing
> boards.
I think it would be acceptable to change geometry on the community if
i
A quick solution is to just use large round holes - large enough to
accept the rectangular pins. A bit ugly, but I've successfully done
that in the past. If you're going to wave solder it would be wise to
talk with your assembler about whether their wave machine will handle
it well.
Another appr
On Tue, Feb 1, 2011 at 9:25 AM, Joshua wrote:
> Here is an update for refdes_renum_slot.
>
> New Feature:
> The tool now takes into consideration the components x position along with
> its y position when assigning a part number. Thus a screen full of
> components will be numbered from left to ri
On Mon, Feb 14, 2011 at 6:27 AM, Kai-Martin Knaak wrote:
> Hi.
> The solder paste pattern emitted by PCB seems to coincide exactly with
> the copper of the pads. This is a reasonable default. But there are use
> cases where a different solder paste size is better.
>
> 1) A pad completely covered w
>>> 2) Pads partly covered by solder mask should receive a solder mask
>>> pillow that corresponds to the hole in the mask, rather than to the
>>> pads copper dimensions. Such partly covered pads are useful as a heat
>>> sink.
>>
>> Yes, that works fine - see S005.fp. This is for a SMD bridge and
On Mon, Feb 14, 2011 at 8:08 AM, Kai-Martin Knaak wrote:
>>> 2) Pads partly covered by solder mask should receive a solder mask
>>> pillow that corresponds to the hole in the mask, rather than to the
>>> pads copper dimensions. Such partly covered pads are useful as a heat
>>> sink.
This patch a
> Right now I've got PhD work which I'm failing at (I'm on medical leave
> due to being depressed), and some part-time paid work trying to avoid
> going broke (which is otherwise imminent) so I can keep paying the rent.
Do take care - I've had depression and know how debilitating it is.
I really v
On Tue, Feb 15, 2011 at 10:14 AM, DJ Delorie wrote:
>
>> Limiting the paste size to min(Mask, Thickness) seems like a good
>> idea, but can anyone think of a case where you'd actually want the
>
> Can you add a check for a fully tented pad? I.e. if mask==0, don't
> draw anything?
Sure.
--- a/sr
I've added this patch to the corresponding LaunchPad bug, #718342
My opinion is that the patch improves PCB's generation of the solder
paste and has a very low risk of creating undesired side effects. I
recommend it for early incorporation into GIT head.
_
On Thu, Feb 17, 2011 at 7:32 AM, yamazakir2 wrote:
> Does anybody know where I can order 50 boards with the price per board
> at the most $5?
>
> The closest I could find was 150 boards with $4.47 per board cost at
> Advanced Circuits. Their 50 qty order is $9.94 :(
What board size ?
Try:
http:
On Thu, Feb 17, 2011 at 7:59 AM, yamazakir2 wrote:
> The board size is 6.275x1.705. Modest amount of holes/vias, nothing
> too crazy. Tolerances are standard, I think the default setup in pcb.
>
> Shipping to the US, specifically CA.
Then it's certainly do-able. The price from custompcb.com for t
On Thu, Feb 17, 2011 at 8:38 AM, Ben Jackson wrote:
> I would not recommend CustomPCB (aka Silver Circuits) for a 50 board
> run. I've used them before and the individual boards have required too
> much attention to imagine using them for 50+. I got one batch where
> most of the vias did not con
On Mon, Feb 21, 2011 at 1:51 PM, Kai-Martin Knaak wrote:
> Ineiev wrote:
>
>> Pushed to git-head.
>
> Great!
> Congrats to your new status!
> The geda project got a new dev!
> This is really good news :-)
+1 :-)
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It's crucial for parts to be quite dry *before* soldering - otherwise
the rapid boiling of trapped moisture can cause components to crack.
*After* soldering, it's much less of an issue. Many components can be
washed with water and detergent, no problem. Most resistors, ceramic
caps and tantalum c
> Thanks for the helpful information. Are ICs and LEDs generally fine to
> wash in water and/or detergent?
Yes, should be fine - but probably a good idea to post wash with
alcohol and certainly give them a good dry.
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On Thu, Feb 24, 2011 at 8:46 AM, yamazakir2 wrote:
> So am I getting this right?
>
> Step 1. Flux Remover
> Step 2. Wash with soap and water (dish soap)
> Step 3. Wash with Isopropyl Alcohol
> Step 4. Dry
Yes, if the water has low mineral content.
> That should leave me with a nice clean board c
On Thu, Feb 24, 2011 at 9:34 AM, yamazakir2 wrote:
> Can I use this instead of distilled water?
>
> http://www.mgchemicals.com/products/406b.html
Looks like you could use it after IPA for cleaning off rosin type
fluxes. Could be worth a try.
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So DJ's teardrop plugin and Ben Jackson's smartdisperse plugin are now
both broken because of changes made to PCB head in the last few
months.
This raises a question for me - should these plugins be incorporated
into PCB head ?
These plugins were written before I joined this list, has the
rationale
> The policy is that we allow anyone to write plugins for their own use,
> and if they want to share them, they may. I see no reason to require
> authors to contribute their plugins to the core pcb code if they do
> not wish to.
I don't want to /require/ anyone to do anything :) Both plugins are
I'm looking for PCIe x1 footprints, both card and motherboard sides.
Ethan Swint posted PCIe x4 footprints to this list in February 2009,
my current plan is to reduce these down to PCIe x1.
Has anyone used Ethan's footprints ? It'd be nice to know if they've
been fabbed and loaded successfully, or
My favorite tool for desoldering is a hot air blower. It may look
like a glorified hair dryer, but it works like a charm. No damaged
tips either :-)
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On Fri, Mar 25, 2011 at 5:36 PM, yamazakir2 wrote:
> Anybody know of a source, other than digikey, that sells prefabbed
> prewound SMPS transformers? Digikey has a few, but their selection
> pretty limited.
Shinhom have some:
http://www.shinhom.com/produc6-1.htm
Their prices are pretty good, bu
> What, if there was a way to flag a track as "don't look" for connectivity
> check? You'd attach the flag to the segment that bridges the domains.
> That way, the DRC check would still be sensitive to violations at other
> places. Such a DRCignore flag might have more legitimate uses. E.g, the
> o
On Mon, May 2, 2011 at 8:49 AM, Rob Butts wrote:
> I'm using out and in symbols in gschem to label nets in a schematic and
> tie nets together without traces running everywhere. I set the net
> attribute of the corresponding out and in symbols in the schematic to
> the same value (clk for
On Mon, May 2, 2011 at 9:16 AM, Rob Butts wrote:
> Really? So now instead of having a nice clean schematic with net names
> like clk, _clk, reset and _reset I have to have clk:1, _clk:1...
> Is the way around that making the net attribute not visible and making
> the value attribute visib
On Wed, May 4, 2011 at 7:37 AM, Peter Clifton wrote:
> On Tue, 2011-05-03 at 19:46 +0200, Kai-Martin Knaak wrote:
>> Peter Clifton wrote:
>>
>> > I'm very close to being able to push the basic 2D portions of PCB+GL
>> > into git HEAD.
>>
>> I feel like a supporter at the course of a marathon race:
On Thu, May 5, 2011 at 5:43 AM, Rob Butts wrote:
> I'm not clear on the groups in the PCB preferences. If I want to auto
> route a board in 4 layers how do I set up the groups?
> Thanks
>From PCB Preferences -> Layers -> Change group you can add or remove
layers, and change their order.
Gr
footprint converts fine for PCB fetched from GIT on 2011-03-29
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On Sat, May 21, 2011 at 1:26 AM, Kai-Martin Knaak
wrote:
> Colin D Bennett wrote:
>
>> Not to get into the whole light/heavy symbol debate
>
> Maybe, it is time to look at this issue again. When I first read geda
> documentation, there were already references that this had been discussed
> ad naus
> I would like to see some options added to the symbol library dialogue:
>
> 1. Create a new (e.g. local) library
> 2. Copy an existing symbol to another (e.g. local) library
> 3. Create a completely new symbol (perhaps using a wizard interface)
Incorporating DJboxsym (or similar) into the wizard
On Wed, May 25, 2011 at 5:25 PM, Tom Pope wrote:
> Just dwelling on the 'what' phase a little more, can we start a few
> pages on the wiki for people to list:
>
> a) all the workflows people would like supported (maybe break it down
> into newby GUI workflows, 'power user' GUI workflows and script
> Then two more usage questions:
> - Zero length lines in PCB: I found that when drawing lines in PCB,
> sometimes dots (zero length lines) get created inadvertently on corners
> and bends. This isn't much of a problem, until I start dragging lines
> and end points in rubber band mode: those dots t
>> > - Zero length lines in PCB: I found that when drawing lines in PCB,
>>
>> I think you're tripping over the metric-rouding bug, where what you're
>> seeing is lines that are 0.01 mil long. We're working on that with
>> the metrification of PCB.
>
> Is there already some sort of script to elimi
On Tue, May 31, 2011 at 7:21 AM, Richard Rasker wrote:
> Op donderdag 26-05-2011 om 22:56 uur [tijdzone +1000], schreef Stephen
> Ecob:
>> > Then two more usage questions:
>> > - Zero length lines in PCB: I found that when drawing lines in PCB,
>> > sometimes dot
>> The trace optimizer only touches autorouted tracks by default - if you
>> want it to work on manually routed traces you need to clear the
>> "Connects -> Optimize routed tracks -> [/] Only autorouted nets"
>> checkbox.
>
> Thanks for the suggestion, but it messed up the layout something
> wicke
On Wed, Jun 1, 2011 at 6:59 AM, Thomas Oldbury wrote:
> Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like
> each jumper to have a refdes and BOM entry if possible.)
The hack I use for solder jumpers is to make a footprint that is open
circuit, and bridge where needed with
On Wed, Jun 22, 2011 at 6:50 AM, Andrew Poelstra wrote:
> We are working on moving pcb toward metric base units -- then
> a mm would be 10^6 nm rather than "about 3937.00787 cmils"
> like we have now.
Thanks for your work on this Andrew, it is a much anticipated improvement :)
I see that you've
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