In gschem I have my default text size set as 8. If I add attributes
via gattrib then the text is added as size 10. Obviously these are two
separate programmes and gattrib is not dependant on the settings in my
gschemrc, so this behaviour is kind of expected. Is there any way to
set the default size
> In gschem I have my default text size set as 8. If I add attributes
> via gattrib then the text is added as size 10. Obviously these are two
> separate programmes and gattrib is not dependant on the settings in my
> gschemrc, so this behaviour is kind of expected. Is there any way to
> set the de
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The meeting will be an o
> I forget the exact behavior of gattrib, but I can say that gattrib
> *does* read the gafrc file. Therefore, try putting a text-size
> declaration in your gafrc file.
I tried putting (text-size 8) into the gafrc file and removed it from
the gschemrc file. Text added in gschem is then back to the
>> I forget the exact behavior of gattrib, but I can say that gattrib
>> *does* read the gafrc file. Therefore, try putting a text-size
>> declaration in your gafrc file.
>
> I tried putting (text-size 8) into the gafrc file and removed it from
> the gschemrc file. Text added in gschem is then bac
On Mon, 2008-10-27 at 07:35 -0400, Stuart Brorson wrote:
> >> I forget the exact behavior of gattrib, but I can say that gattrib
> >> *does* read the gafrc file. Therefore, try putting a text-size
> >> declaration in your gafrc file.
> >
> > I tried putting (text-size 8) into the gafrc file and re
Sometimes it is necessary/recommended to partition (separate) power or
ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in
http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf
We can do this in pcb program with (adjoining) polygons.
Disadvantage is, that if we change the size of on
I do not fully understand what is going on when a polygon is divided by
a trace (with clearance).
Is there somewhere an explanation how it (should) work?
Is there a way to deactivate the removal of copper?
It is my impression that always the smaller part of a rectangle/polygon
is removed, even w
I typically deal with this by separating the planes at the schematic
level using a bead-core inductor. The two planes are then on different
nets at the PCB level. This not only makes it easier to do the routing
but they also serve an electrical purpose of isolating the two planes
from a high freque
Am Montag, den 27.10.2008, 11:59 -0400 schrieb Neil Webster:
> I typically deal with this by separating the planes at the schematic
> level using a bead-core inductor. The two planes are then on different
> nets at the PCB level. This not only makes it easier to do the routing
> but they also serve
I do not want to start a flame war, since I am relatively new here but I
have to comment ...
On Sun, 2008-10-26 at 20:47 +0100, Stefan Salewski wrote:
> Am Sonntag, den 26.10.2008, 14:25 -0500 schrieb Kipton Moravec:
> >
> > There are huge differences in the size of these footprints!
>
> Please
> Why in gods name would some one call a footprint 0603 when it is
> really an 0201. Nobody uses a metric name for resistors or
> capacitors. You folks are asking for trouble.
It's not us, it's the international standards. We're microscopic fish
in a galaxy-sized pond.
On Oct 27, 2008, at 10:21 AM, Kipton Moravec wrote:
> Why in gods name would some one call a footprint 0603 when it is
> really
> an 0201.
Because that's what's on the datasheet.
> Nobody uses a metric name for resistors or capacitors.
I see it all the time. For example, here's a blurb that
Ahh, haha.
In the USA, electronic design engineers have been using inches (with
0603 meaning 0.06 by 0.03 inches) to describe surface mount resistors
and capacitors.
Folks in other countries have probably always been using metric.
But I've noticed that recently digikey.com (a pop
On Mon, Oct 27, 2008 at 11:21:50AM -0600, John Doty wrote:
> > Nobody uses a metric name for resistors or capacitors.
>
> I see it all the time. For example, here's a blurb that gives both
> with priority to metric:
>
> http://www.rohm.com/ad/mcr004/index.html
Another example is Altium, which
>> I typically deal with this by separating the planes at the schematic
>> level using a bead-core inductor.
> Yes, I also have GND and AGND in my schematics.
Don't put inductors between ground planes, connect them at a star
point. If you are going to use inductors then have them on the power
sid
Am Montag, den 27.10.2008, 19:47 +0200 schrieb Duncan Drennan:
>
> > Yes, I also have GND and AGND in my schematics.
>
> Don't put inductors between ground planes, connect them at a star
> point. If you are going to use inductors then have them on the power
> side, not between grounds.
>
I thin
On Mon, 27 Oct 2008 19:47:32 +0200, Duncan Drennan wrote:
>> How do I best divide a copper area (physically) into subsections with
>> complicated shape/outline.
>
> Is there a good way to do this with PCB?
If you want to partially divide a polygon:
* Draw lines on copper with zero thickness b
Am Montag, den 27.10.2008, 18:17 + schrieb Kai-Martin Knaak:
> On Mon, 27 Oct 2008 19:47:32 +0200, Duncan Drennan wrote:
>
> >> How do I best divide a copper area (physically) into subsections with
> >> complicated shape/outline.
> >
> > Is there a good way to do this with PCB?
>
> If you wa
On Mon, 2008-10-27 at 16:47 +0100, Stefan Salewski wrote:
> I do not fully understand what is going on when a polygon is divided by
> a trace (with clearance).
>
> Is there somewhere an explanation how it (should) work?
>
> Is there a way to deactivate the removal of copper?
> It is my impressio
Kipton Moravec wrote:
> I do not want to start a flame war,
.
.
.
Everyone
> should design for the machine.
You might get one. But probably not... gEDA users are about as individual as
they come,
and often do things "their way", so you won't be able to convince them to all
design any one way
I agree with Niel, I separate my ground planes with a symbol for a power
inductor. I do this at the schematic level and then I read the layout
suggestions typically provided by the A/D data sheet on where to connect
the planes. For the fab I put in the power inductor foot print. You can
then use th
On the issue of powering boards I have been playing with some really
neat programmable power supply controllers (surface mount chip) that
support power supply modules. Prices of the modules seem to be
comparable to the prices of the individual components one would need to
build various forms of swi
On Mon, 27 Oct 2008 19:47:52 +0100, Stefan Salewski wrote:
>> * Draw lines on copper with zero thickness but finite clearance.
>>
> Does this really result in legal Gerber files -- would be not so nice if
> a few manufacturers can not handle it.
I didn't check the Gerber specs. My favorite fab
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