People,
I need some help here. I'm trying to work with _LARGE_ symbols and
footprints. In the smaller case, over 1100 pins and in the larger case
over 1700 pins. In order to make the information more readable, I have
broken the symbols into slots, 4 in the smaller case and 6 in the larger
case.
On 2/23/07, Dan McMahill <[EMAIL PROTECTED]> wrote:
John Luciani wrote:
> On 2/23/07, Marc Moreau <[EMAIL PROTECTED]> wrote:
>
>> well Primarily: Ping Luciani.
>>
>> How did you make all the gifs of your footprints? Is it a script to
>> do it automagickly, or is it part of PCB?
>
>
> I have a sc
The installer worked fine on Fedora Core 5 x86_64.I don't install from a
CD but copy the contents to a directory on the hardrive and install from
there.
Ray Warren
Thank you!
I'll move the .iso over to seul.org shortly since most reports were
positive
_
Harold,
To run gsch2pcb I have created a project1 file in which I can tell the
system which schematic pages to process (1 symbol slot per page). If I
process only 1 or 2 pages, i.e. 1 or 2 slots, the system functions
correctly and I can enter PCB and pull up the footprint and view the
associate
Harold D. Skank wrote:
People,
I just created a 4-slot symbol and associated 1153 pin footprint for a
Xilinx element that I need to route. This morning I set out to test
these elements to see if they worked together OK. Well -
I created a dummy schematic composed of the 4 slot elements, and
c
Stuart Brorson wrote:
It's just a blind shot in the dark, but here's a possibility.
I took two minutes to look through the gsch2pcb.c code, which lives in
utils/src. There are a number of places where a 1024 byte character
buffer is created at the beginning of a function, like this:
add_elem
Ben,
Thanks for the feedback. I didn't know about that pinout - I didn't see
it in the first document you sent, but I saw it in the second. Anyway,
I 've been working on a tool for doing footprints more easily, and your
part looked different from the ones I've been doing, so I thought I'd
t
Harold,
>> People,
>>
>> I need some help here. I'm trying to work with _LARGE_ symbols and
>> footprints. In the smaller case, over 1100 pins and in the larger case
[snip]
>
>Can you send me a test case that I can run? It is quite possible that
As I responded yesterday:
http://archives.seu
Harold D. Skank wrote:
People,
I need some help here. I'm trying to work with _LARGE_ symbols and
footprints. In the smaller case, over 1100 pins and in the larger case
over 1700 pins. In order to make the information more readable, I have
broken the symbols into slots, 4 in the smaller case
On Sat, 24 Feb 2007 08:26:19 -0500
"John Luciani" <[EMAIL PROTECTED]> wrote:
> On 2/23/07, Dan McMahill <[EMAIL PROTECTED]> wrote:
> > John Luciani wrote:
> > > On 2/23/07, Marc Moreau <[EMAIL PROTECTED]> wrote:
> > >
> > >> well Primarily: Ping Luciani.
> > >>
> > >> How did you make all the gifs
no, I'm pretty certain (95%) that it is not gsch2pcb causing the
problem. It
is almost certainly gnetlist.
gnetlist -g PCB -o myfile.net mysch1.sch mysch2.sch ...
Fair enough. In the backend gnet-PCB.scm, this fcn:
(define (PCB:display-connections nets)
(apply format #f "~:@{~A-~A ~
Dan McMahill wrote:
DJ Delorie wrote:
I was just thinking "teach pcb to load elements directly". Then you
can export them wit the EPS hid.
that would be convenient.
A path to do that could be load element to the buffer...the reverse of what we
already have...
I like all the talk lately
DJ Delorie wrote:
Ok, done.
$ pcb -x eps --eps-scale 8 --eps-file r8c-ssop20.eps r8c-ssop20.fp
Nice. much more utile than "load to buffer"!
Thanks DJ,
John Griessen
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bi
Harold D. Skank wrote:
People,
I need some help here. I'm trying to work with _LARGE_ symbols and
footprints..
.
.
.
Help would be greatly appreciated. This is an important project and
further delays would cause serious problems.
Steve Meier works with large FPGA symbols and probably has a
On Sat, 24 Feb 2007, Harold D. Skank wrote:
In order to make the information more readable, I have
broken the symbols into slots, 4 in the smaller case and 6 in the larger
case. Since none of the slots within a symbol share any common pins, I
have deleted the slotdef attribute from the symbols.
Dobry den,
tento mail vam poslal pocitac, pretoze ste sa pokusili poslat
mi prilis velku prilohu. Zial, take velke prilohy sa do mojej
schranky nezmestia. Poslite, prosim, mail znova bez prilohy a
prilohu ulozte na verejnom ulozisku, napriklad
http://www.yousendit.com/
alebo http://www.uschovna.
Stuart,
That was pretty much my starting point, with the same results. Thanks
for the information though, as in thinking about the problem, I wasn't
certain just what the various slot attributes were contributing, given
that there were no common pins among the *.sym elements.
Harold Skank
O
Harold D. Skank wrote:
Dan & Co.
I have attached all the files revelant to this problem below, i.e. the
pcb footprint, the *.sym files from gEDA, the schematic and project
files and a copy of the error output from the gsch2pcb command.
I VERY much appreciate any assistance on this problem. Whi
Dan,
Sorry, I inadvertently sent you a copy of project1 using only 2 of the
symbol slots, Test_2.sch and Test_3.sch. I can run that version
correctly as well.
I expect you will see a failure if you add Test_1.sch to the project1
file.
I'm attaching an altered copy of project1 below.
Harold
Harold D. Skank wrote:
Dan,
Sorry, I inadvertently sent you a copy of project1 using only 2 of the
symbol slots, Test_2.sch and Test_3.sch. I can run that version
correctly as well.
I expect you will see a failure if you add Test_1.sch to the project1
file.
I'm attaching an altered copy of pr
Dan,
Comments inserted below.
Harold Skank
On Sat, 2007-02-24 at 15:04 -0500, Dan McMahill wrote:
> Harold D. Skank wrote:
> > Dan,
> >
> > Sorry, I inadvertently sent you a copy of project1 using only 2 of the
> > symbol slots, Test_2.sch and Test_3.sch. I can run that version
> > correct
I have jcl's library installed. If I specify a package name that appears
many places, like 0805, I get the m4 one from gsch2pcb. Similarly for
SO16W. If I specify a name that's unique, like DIP-18-300, then it will
find the file and use it.
How can I set the search order to prefer a particular
Harold,
The bad news for you is that I was able to successfully run gsch2pcb
on your file. So both Dan and I had no problem with your design
files.
Here's another thought. Your error is:
FORMAT: error with call: (format #f "~:@{~A-~A ~}
<===" ("U1" "G29") ("U1" "G34") ("U1" "G9") ("U1" "H1")
On Fri, Feb 23, 2007 at 06:38:03AM -0500, Stuart Brorson wrote:
> gEDA users --
>
> Following the releases of PCB and gEDA/gaf, I have created a new
> version of the gEDA Suite install CD. For now, it lives on my
> website:
>
> http://www.brorson.com/gEDA/
>
> Later, after some testing, I will
Ben Jackson wrote:
I have jcl's library installed.
You can also install jcl's sch2pcb, specifying the directory and _file_
footprints.
Save a text file as sch2pcb in your project directory and just
./sch2pcb project
to get it to run. It should be something like what's below, changing
fo
[EMAIL PROTECTED] wrote:
Ben Jackson wrote:
I have jcl's library installed.
You can also install jcl's sch2pcb, specifying the directory and _file_
footprints.
Save a text file as sch2pcb in your project directory and just
./sch2pcb project
to get it to run. It should be something lik
Stuart Brorson wrote:
Harold,
The bad news for you is that I was able to successfully run gsch2pcb
on your file. So both Dan and I had no problem with your design
files.
Here's another thought. Your error is:
FORMAT: error with call: (format #f "~:@{~A-~A ~}
<===" ("U1" "G29") ("U1" "G34") (
I just pulled up Darrel Harmon's single board computer to test a plugin
I'm working on. I'm on the latest PCB CVS, minus a day or so. It takes
my computer about 4 seconds to redraw if you can see the whole thing.
I went back to 20060822 and it's much faster, essentially no lag for
drawing the sam
On Sat, Feb 24, 2007 at 05:11:36PM -0800, Ben Jackson wrote:
> I just pulled up Darrel Harmon's single board computer to test a plugin
Sorry, forgot the link:
http://dlharmon.com/sbc.html
--
Ben Jackson AD7GD
<[EMAIL PROTECTED]>
http://www.ben.com/
On 2/23/07, Ben Jackson <[EMAIL PROTECTED]> wrote:
I need a PCB element for a Molex 71661-2068:
http://www.molex.com/product/micro/71661r.html
I've placed the Molex 71661 series connectors on my website at
http://www.luciani.org/geda/pcb/pcb-footprint-list.html#Connector
The silkscreen shou
* Added CTS resistor networks series 740, 741, 742, 743, 744, 745,
746,
* Added Molex EBBI connectors 71661 Series (Option B). See Molex
drawing SDA-71661-2*** Rev. M for mounting information.
* Fixed the silkscreen on the Molex 68301 header footprints. For the
headers with an odd number of p
Ben Jackson wrote:
I just pulled up Darrel Harmon's single board computer to test a plugin
I'm working on. I'm on the latest PCB CVS, minus a day or so. It takes
my computer about 4 seconds to redraw if you can see the whole thing.
I went back to 20060822 and it's much faster, essentially no la
On Sat, Feb 24, 2007 at 08:27:24PM -0500, Dan McMahill wrote:
>
> Probably the polygon clipper code. After the initial loading is it
> faster to zoom and pan?
I thought that might be it, but my recent hacking on autocrop led me
to believe that polygons would only be "plowed" when necessary, and
> Probably the polygon clipper code. After the initial loading is it
> faster to zoom and pan?
Probably is. If you disable the two inner layer, it's normal speed.
If you view just one inner layer, it's slow.
> Makes me wonder if polygons in pcb need to have a "poured/unpoured"
> state. In t
My first test board for PCB involved an array of LEDs, and even with just
a few components it got really annoying searching for the resistors that
went with each LED after the DisperseElements().
My head was filled with grandiose schemes for improving Disperse without
turning it into autoplace. I
> In the spirit of open source I cast this hack upon the waters for
> someone else to improve. Ultimately I think the PCB data structures
> are so bad, especially from the perspective of a plugin, that a
> really good plugin would have to construct a whole new
> element/netlist representation int
Dan McMahill wrote:
Stuart Brorson wrote:
Harold,
The bad news for you is that I was able to successfully run gsch2pcb
on your file. So both Dan and I had no problem with your design
files.
and I've now tried gnetlist from 20070216, 20061020, 20050820, and
20040111 with varying guile vers
--- DJ Delorie <[EMAIL PROTECTED]> wrote:
> Lesstif has a "thindraw polygons" option that does
> basically that.
> Unfortunately, the clipper makes it useless because
> it doesn't know
> about the flag, so you see hundreds of polygon slice
> outlines. I need
> to move all the thindraw stuff to o
> Line 2046 in draw.c attempts to check for the thindraw flag but it
> seems you've moved the thin drawing into the hid (but only for
> lesstif). The GTK gui correctly handles thin draw of the polygons,
> which make the panning and zooming much faster for the sbc board.
Yup, I saw that. That's w
Ok, having "finished" the smartdisperse plugin, I moved on to phase 2 of
my "I'm sick of moving LEDs by hand" master plan.
Introducing Align() and Distribute(), which work much like the similarly
named functions in Visio. Given that PCB does not have the concept of
"first selected object" to draw
How about a "move element by name to X,Y" action? Then you could
write a perl script to generate an action script, and run it to place
everything.
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-us
41 matches
Mail list logo
