> Original Message
> Subject: Re: gEDA-user: verilog -> gschem
> From: Steven Michalske
> Date: Fri, July 08, 2011 1:46 pm
> To: gEDA user mailing list
> Will the gentlest backend for verilog accept symbols with the source
> attribute set, like hierarchy symbols, but > making
> Original Message
> Subject: Re: gEDA-user: verilog -> gschem
> From: Ouabache Designworks
> Date: Fri, July 08, 2011 9:43 am
> To: geda-user@moria.seul.org
>
>
> The only difference between that and and PCB layout program is that you
> don't care about trace width and you can
> Original Message
> Subject: Re: gEDA-user: verilog -> gschem
> From: John Griessen
> Date: Fri, July 08, 2011 9:27 am
> To: gEDA user mailing list
>
> On 07/07/11 17:31, fr...@frankthomson.net wrote:
>> I just need to get it into gschem format to run through
>> gnetlist to a
p in the process requires running the design through
gnetlist but since gnetlist only reads gschem files as input I need to
get the verilog files to gschem to feed gnetlist.
-Frank
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n. I'll take a look at the spice-sdb backend and also at
your gEDA fork. Since you are also doing IC work, if you happen to know
of
an open source detail or maze router please let me know.
-Frank
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r as I
know they haven't made it to the >official documentation.
Yes, I found that a day ago and it was very helpful, appreciate you having
posted it.
-Frank
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I'm working on a backend for gnetlist and have a minor problem, the top
level schematic has IPAD/OPAD/IOPADs that i need to list in the netlist
but I can't find a way to directly address the top level schematic, it
doesn't seem to have a uref I can use to reference it. It does have a
I know you can select an element and hide it's refdes with 'h'. Is
there a way to hide all of the silk of an element?
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On Jan 5, 2011, at 5:51 PM, Kai-Martin Knaak wrote:
> Frank wrote:
>
>> I'm creating a footprint according to the datasheet, and it has 3
>> different prohibited areas on the footprint. I'm not sure of the
>> exact meaning of these areas. Can someone explai
I'm creating a footprint according to the datasheet, and it has 3
different prohibited areas on the footprint. I'm not sure of the exact
meaning of these areas. Can someone explain?
1) Prohibited Area
2) Pattern Prohibition Area
2) Solder Prohibition Area
. Moving it is not a problem. How can I rotate
it?
Thanks,
Frank
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can be compiled with mingw-cross
(http://mingw-cross-env.nongnu.org/). It's usable but lacks some
features you have to disable at compile time and run slow on win32.
Frank.
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Am 11.11.2010 00:13, schrieb Peter Clifton:
On Wed, 2010-11-10 at 21:34 +0100, Frank Bergmann wrote:
You find the backtrace at
http://www.frajasalo.de/frank/projekt/pcb/gdb-pcb.local_customisation_no_pours-backtrace-20101110-1.txt
I hope it will help, even without the debugging symbols in
://www.frajasalo.de/frank/projekt/pcb/pcb.local_customisation_no_pours-20101110_amd4core.png
The pixel shader which draws the rounded line ends (and vias / holes
etc..) isn't working. Your hardware might not support that GL extension,
I misread.. the card isn't that old.. but Debian stable i
On 11.11.2010 00:13, Peter Clifton wrote:
On Wed, 2010-11-10 at 21:34 +0100, Frank Bergmann wrote:
And on my Intel system I have disturbances comming like rays from the
middle of the viewport/drawing area, see:
http://www.frajasalo.de/frank/projekt/pcb/pcb.local_customisation_no_pours
On 10.11.2010 23:17, DJ Delorie wrote:
gdlib-config is part of the GD library available from www.boutell.com/gd.
or install the gd and gd-devel packages.
for ubuntu you find it in libgd2-(no)xpm-dev package
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On 10.11.2010 21:36, DJ Delorie wrote:
Try ./configure --disable-dbus
or try installing package libdbus-1-dev
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fer
mapped whilst I'm glClear'ing. (Although it should not care!).
You find the backtrace at
http://www.frajasalo.de/frank/projekt/pcb/gdb-pcb.local_customisation_no_pours-backtrace-20101110-1.txt
I hope it will help, even without the debugging symbols in the system
stuff. In my former te
false; will give you mapping with use_vbo, or arrays without.
Sorry, I can not find any appearance of "buffer->use_map" or even
"use_map" in your latest local_customisation_no_pours branch. Shall I
use an other branch? Or
ivers. The cards are not well supported
by proprietary drivers at installation time.
Segmentation fault happens in hidgl_clean_unassigned_stencil()
(hid/common/hidgl.c:1069) and backtrace goes into
/usr/lib/dri/r300_dri.so, so maybe its a problem in the drive
On 12.10.2010 22:37, Andrew Poelstra wrote:
What does "lefthanded coordinate system" mean?
http://en.wikipedia.org/wiki/Cartesian_coordinate_system#In_two_dimensions
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d the silk
and paste (for this board only smt parts had paste layer) layer to it.
Now I got errors if I placed parts in the soldering tracks. Copper are
allowed because it was covered by solder mask.)
Frank.
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aps a
step to far (or too early). There are probably other more useful
refactors, such as making a layer-selector widget, route-style selector
widget etc., and defining clean interfaces with those.
... command entry widget with history and auto completion ...
ata
(http://library.gnome.org/devel/gobject/stable/gobject-The-Base-Object-Type.html#g-object-get-data)?
Maybe this can help putting some of the global variables in the main window.
Frank.
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http://www.seul.o
.org/devel/gdl/stable/) for this feature. Maybe GDL
will be longer available :)
Frank.
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nd if necessary.
I guess the terms you want to understand are mostly relevant for writing
new/own widgets.
Frank.
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Am 08.09.2010 03:31, schrieb DJ Delorie:
Editing *anything* with two editors (any kind of editors) at the same
time IS BAD, unless both are explicitly designed to work together that
way.
Yes, multiple users/instances can work on the same layout simultaneous...
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he submitter to provide better patches next time.
BTW ineiev "guides" me across my patch on sf until his requirements are met.
Frank Bergmann.
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hey are good for, or does that just need some notes and
> documentation and phone calls?
For me, just copper, no solder mask but described in the bom and appeared
in the pick and place data. Communicaton starts typically when they are
missed ...
rework
my patch with libgdl. And the opportunity for different severities
(different colors or little icons, filters, ...) are also in my mind.
Frank Bergmann.
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On Mon, 01 Feb 2010 18:52:40 -0500, DJ Delorie wrote:
> Fixed. Amusingly enough, the lesstif hid had the same conflict, but
> avoided it as that file didn't pull in the header.
Now it builds, thanks!
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pcb/src/hid/gtk/gui-netlist-window.c:978: error: conflicting types for
‘NetlistChanged’
../../pcb/src/misc.h:124: note: previous declaration of ‘NetlistChanged’ was
here
make[4]: *** [hid/gtk/libgtk_a-gui-netlist-window.o] Error 1
Frank.
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On Tue, 17 Nov 2009 19:24:48 +, Peter Clifton wrote:
> On Tue, 2009-11-17 at 18:35 +, Ineiev wrote:
>> On 11/17/09, Peter Clifton
>> wrote:
>> > On Tue, 2009-11-17 at 14:11 +, Ineiev wrote:
>> >> I think you may want to use this Frank Bergm
On Fri, 30 Oct 2009 19:25:24 +0100, Bert Timmerman wrote:
> On Thu, 2009-10-29 at 20:31 +0000, Frank Bergmann wrote:
>> On Wed, 28 Oct 2009 21:47:21 -0400, DJ Delorie wrote:
>>
>> > Where do you keep "unplaced" parts in your scheme? Do they still
>>
On Thu, 29 Oct 2009 18:12:50 -0400, DJ Delorie wrote:
> Don't forget to handle the case where the board doesn't yet have an
> outline layer :-)
Mmmh ... ! I'll create one ;-)
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hange internal data structures.
Mmmh ... I think about it ... and maybe I found a solution for me and can
provide some patches.
Frank.
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On Thu, 29 Oct 2009 16:42:09 -0400, DJ Delorie wrote:
>> What are "unplaced parts"? - I know tools that define such parts as
>> "parts not within the (closed) board outline" and mark them by color or
>> symbol.
>
> Ah, "you don't" :-)
>
> The LinuxFund work includes an item for storing unplaced
On Wed, 28 Oct 2009 21:47:21 -0400, DJ Delorie wrote:
>> http://frajasalo.de/frank/projekt/pcb/pcb_part-view_20091028-2257.png
>
> That board looks familiar... ;-)
I would be suprised if not ... It is a good reference, throws some drc
errors, is not to big to delay pcb'
able to multi-select, and hit "auto-disperse
> selected" in the parts bin. Filter by name, by footprint (leave all
> those decoupling caps to last etc..)...
>
> Anyone want to code this??
Mmmh - digging in my local git repos give me this:
http://frajasalo.de/frank/p
g driver...so here is my...)
running your pcb-gl master-branch on FC11 with intel xorg driver
(2.7.0) crashes my xserver while showing drc window (library window
is ok). It seems to be a bug in the driver, because the same code
on a debian lenny system with radeonhd xorg driver r
(smt res and caps as plain boxes) to the coordinates from the xyfile should
give the first results.
Frank.
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On Fri, 02 Oct 2009 20:14:46 +0100, Peter Clifton wrote:
> On Fri, 2009-10-02 at 18:59 +0000, Frank Bergmann wrote:
>> Is the code you have trouble with already in your git repo?
>
> git clone git://repo.or.cz/geda-pcb/pcjc2.git cd pcjc2
> git checkout -b before_pours o
ioned before cairo claims hw acceleration.
Well, I am have no x/graphics/rendering experience ...
Is the code you have trouble with already in your git repo?
And is the step towards OpenGL the next big step in pcb (gtkhid) development?
Frank.
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On Thu, 01 Oct 2009 19:43:09 +, Frank Bergmann wrote:
> On Tue, 29 Sep 2009 18:22:04 +0100, Peter Clifton wrote:
>
>> Hi guys,
>>
>> This is a vague bug report at best - hence mentioned here in case it
>> means anything to anyone. I've not really got e
On Thu, 01 Oct 2009 23:22:14 +0200, Stefan Salewski wrote:
> Hope not annoying you, but if you followed this list very carefully the
> last years (I did not
Me too. I am pretty new to this project.
> ) you may know that Peter C. is a very smart
> software developer who has contributed much to gE
here on FC11. If you have code and
instructions how to reproduce the "bug" I can do some tests here.
Frank.
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Since DJ mentioned impedance level concerns associated with different kinds
of flux: please note that the flux pen shown in John Luciani's generally
excellent recommendations leads to seriously low electrical conductivity.
[At least for high-impedance analog circuits].
It's a pretty aggressive flu
t ought to be happening soon actually.
I am looking forward to the moment when the gl code hits the main line.
Because it seems to be much faster, at least on one of my systems. When
I load DJ's m32c sdram project the speed difference is dramatically! It
still have some "fl
On Tue, 02 Jun 2009 00:17:22 +0100, Peter Clifton wrote:
> On Mon, 2009-06-01 at 21:28 +0000, Frank Bergmann wrote:
>> Am Fri, 29 May 2009 07:25:27 -0400 schrieb Dan McMahill:
>>
>> > I just pushed some changes to part of how the PCB build system works.
>> >
it's a little bit of topic, but
there are any plans to integrate the OpenGL branch into the main git
repo? Even perhaps as another hid compile option or, still better, as
a runtime option?
Frank.
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on of a clean git repository, it could
be better to discuss patches before applying them to the repo.
git is designed to support this ...
I have not tested your changes yet, but I like the intention.
Frank.
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e/she is willing to provide a further patch.
Frank.
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one can see and
> discuss the patch, and if people like it a committer can apply it with
> almost zero effort.
Find http://www.kernel.org/pub/software/scm/git/docs/everyday.html
usefull learning git usage.
Frank.
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27;m
afraid the project needs a dicussion about the direction of such
improvements/modernizations.
> Cheers,
Frank.
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DJ Delorie wrote:
>> Is there some reason that "New Lines... clear polygons" is not on by
>> default?
>It *is* on by default. The problem is that gsch2pcb doesn't use pcb's
>defaults. That's why in my tutorials, I don't let gsch2pcb create the
>initial board.
I'm probably blind, but I've only
Thanks John and Kai-Martin, that should be an adequate if awkward work-around.
It must also be the approach to take when other "shape changes" are desirable
beyond the limits of rotation and mirroring.
-Frank
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Newbie questioner...
Is there a way to selectively hide the power pins of a multi-sectioned
component?
That is, without having to resort to the "hidden connection" (net attribute)
method?
A simple example: a 7400 package, with 4 2-in nand gates. With OrCAD, I was
able
to create a _5_ element
yone for their ideas.
Frank Miles
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provides
a nice mechanism for hand-entry, but doesn't (in my quick check) seem to
provide
any mechanism for program control.
If anyone can provide pointers to the documents that I have sloppily overlooked,
I'd appreciate it. Thanks!
Frank Miles
Gerbv (including 1.0.3) seems to have difficulty reading the format string.
I've been trying to get gerbv to handle the first example Gerber code from the
file:
http://gerbv.sourceforge.net/docs/rs274xrevd_e.pdf :
*G04 EXAMPLE 1: 2 BOXES
%FSLAX23Y23*%
%MOIN*%
I'm trying to understand symbol attributes. The most current version of the
"master
attribute document" that I've found (2004) seems to be missing some things -
such
definitions for "pins" (seems to be the pin count) and "class" (what are the
allowed
values?). Is a more up-to-date doc availab
I'm trying to understand symbol attributes. The most current version of the
"master
attribute document" (2004) seems to be missing some things - such definitions
for
"pins" (seems to be the pin count) and "class" (and the acceptable values, if
limited, for class).
I haven't found any docs whic
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