Re: gEDA-user: icarus, fork, and recursive tasks

DJ Delorie wrote: >> task automatic twait > > Tried that first. Icarus didn't support it. Actually, Icarus Verilog should support automatic tasks, even the 0.9 version that you say you're running. Maybe there is a bug that is tripped by a specific use? -- Steve Williams"The woo

Re: gEDA-user: Icarus Verilog 0.9.3 is Available

Hirokatsu SUNAKAWA wrote: > On Mon, 27 Sep 2010 17:05:06 -0700 > Stephen Williams wrote: > >> More details, including known limitations, deviations from IEEE Std >> 1364-2005, where to obtain the source code, and links to some of the >> precompiled packages can be

gEDA-user: Icarus Verilog 0.9.3 is Available

The developers are pleased to announce the next stable release in the 0.9 series, version 0.9.3. Icarus Verilog is a mostly complete implementation of the hardware description language Verilog, as described in IEEE Std 1364-2005. It also includes a number of user requested extensions. It is freely

Re: gEDA-user: Icarus verilog Synthesis

What are you trying to do? Are you really trying to "synthesize" your Verilog design, meaning you are trying to generate a bit stream to load into your FPGA? Or are you trying to compile and simulate your Verilog? Icarus Verilog is mostly a *simulator*, not a synthesizer. There were some synthesi

Re: gEDA-user: Yet another Icarus question

This looks like a bug in Icarus Verilog, I'm afraid. Since all the values in your expression have explicit sizes, the bit width need not have carry space tacked on and the width should be 26bits. In fact, in your example the bus is particularly nasty because it causes the enablemask bits to be shi

Re: gEDA-user: OT Verilog syntax question

I'm a little surprised that Icarus Verilog doesn't already pay attention to the "4" in your "%4b". In any case, this should do the trick for you: integer result; ... $display("%b", result[3:0]); ... or failing that, you can try: wire [3:0] tmp = result; ... $display("%b", tmp); Pa

Re: gEDA-user: What's the best way to run a test version of iverilog?

Patrick Doyle wrote: > On Fri, Jul 9, 2010 at 3:20 PM, Stephen Williams > wrote: >> Patrick Doyle wrote: >>> If I want to compile and test a particular version of Icarus Verilog >>> without messing my existing working installation, what's the best way >>

Re: gEDA-user: What's the best way to run a test version of iverilog?

Patrick Doyle wrote: > If I want to compile and test a particular version of Icarus Verilog > without messing my existing working installation, what's the best way > to do that? > > I could configure it with a prefix of some temp directory and add that > directory (/bin) to my path. > > Or I coul

Re: gEDA-user: Strange behavior from Icarus Verilog

Eric Brombaugh wrote: > I ran this through Modelsim LE and got the following result: > > # -7.093308,7.093308,7.093308,7 > > Running it through my copy of Icarus 0.9.2 gives the same answer you got > above, so I'm guessing that there's something odd going on with the way > Icarus is parsing compl

Re: gEDA-user: Structure of Iverilog Windows Version

Ronald Mathias wrote: >I have downloaded the windows version of icarus verilog version 0.8.1.7 >from [1]http://bleyer.org/icarus/. When I install the executable, I get >the executable vlpp.exe ivl.exe. in the lib\ivl directory. I know that >vlpp.exe is the preprocessor. But I do not

Re: gEDA-user: hydraulic symbols and schematics

Stuart Brorson wrote: >> Do you foresee any other difficulties? ... aside from simulating a >> hydraulic circuit with spice or generating a layout. > > Actually, my first thought was: What kinds of simulations (if any) > does one do in hydraulics? Are there any standard simulators? If so, > g

Re: gEDA-user: iVerilog/GTKWave - Viewing multi-dimensional arrays in GTKWave

Some things have indeed been done. At the very least, you can explicitly list in $dumpvars the array words that you want to dump. The list needs to be explicit to prevent the explosion of traces when you have large memories in your design. Denis Daly wrote: > Hi, > > I'm trying to simulate a Ver

Re: gEDA-user: net= attributes, symbols and schematics

serve relationships. Kai-Martin Knaak wrote: > On Wed, 14 Oct 2009 15:58:14 -0700, Stephen Williams wrote: > >> I'm planing a circuit where some chips have a wide variety of different >> power supply requirements. I'm debating with myself whether I should >> create symbol

gEDA-user: net= attributes, symbols and schematics

I'm planing a circuit where some chips have a wide variety of different power supply requirements. I'm debating with myself whether I should create symbols that have net= attributes for all the various power types, or if I should attach attributes from outside the symbol, or create pins for all th

Re: gEDA-user: Issue with Icarus for windows v0.9.1 & lxt file generation

Jackson Nichol wrote: > I am hoping that someone can help me with a problem that I am having. I have > upgraded to Icarus Verilog for windows v0.9.1 from the www.bleyer.org/icarus > site. > > Now when I run a simple test using the following two command line options > iverilog -o tb.vvp -s tb tb

Re: gEDA-user: Icarus: Synthesize Verilog to Verilog

The Verilog target for Icarus Verilog needs attention. If it were it a usable (even compilable) state, it would be of use to you. Is it sits, getting it it working order would be a great summer project for somebody. Philipp Klaus Krause wrote: > Is it possible to use Icarus to simplify Verilog co

Re: gEDA-user: Timing in Icarus Verilog not working

What verion of Icarus Verilog are you using? Icarus Verilog doesn't support specify blocks before the 0.9 release. I think with the 0.9 release, it is default turned off, you enable it with -gspecify. Philipp Klaus Krause wrote: > I want to model gate delays, but everything happens without delay.

Re: gEDA-user: mail to Stephen Williams

For the record, and this is the last I'll say about this, the access list that the icarus.com mail server uses is kept copied here: The policy is simple and somewhat automatic: If an IP source sends mail to icarus.com that is clearly spam, the assumption

gEDA-user: Icarus Verilog Release 0.9.1

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 It's been *years* since we've made a new stable release, but the time has finally come. Icarus Verilog 0.9.1 is the first release of the 0.9 series! Get the source here: Since this is

Re: gEDA-user: Icarus Verilog: How to exit simulator with non-zero status?

Larry Doolittle wrote: > Patrick - > > On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote: >> Should I have been able to find that somewhere else? (I am >>asking in a tone of voice of "I would like to know where to look for >>answers such as these so I don't have to pester the

Re: gEDA-user: Google SoC : Potential Candidate seeking Info

Aanjhan R wrote: >> On Wednesday 11 February 2009, Stephen Williams wrote: >>>> Given the apparent bent towards analog in your selection of >>>> candidate projects, might I suggest you take a look at the >>>> "gnucap Code Generator" on the Icaru

Re: gEDA-user: Google SoC : Potential Candidate seeking Info

Aanjhan R wrote: > The projects that am interested in are as follows (not in any specific order): > > 1. Usability improvements for ngspice/Gnucap - Under gaf > 2. More "interesting" integrations with other tools. The new Tcl > interface adds a bunch of possibilities. I know one guy is using it t

Re: gEDA-user: order of defparam vs. #(.) parameters in icarus

Matt Ettus wrote: > In some Xilinx models, they make instantiations like this: > > block instance(ports); > defparam instance.param=VALUE > > > This normally works ok. The problem is that inside the block, > generate statements are being used which are dependent on the value of > the parameter.

Re: gEDA-user: Any discussion about combining schematics and symbols into one file?

Yamazaki R2 wrote: >I think i might have brought this up before but I wanted to bring this >up again. I know this would be kind of a big change to the way gEDA >works, but it would be nice to combine component's schematic, symbol, >and maybe pcb view into one file. Or at least the o

Re: gEDA-user: OT: Recommendations for laptop?

Stuart Brorson wrote: > My old laptop has gotten old and is starting to act like it should be > retired. I use it for hacking (including working on gEDA stuff on > those now rare occasions when I get to it), writing, accessing the > net, and as the primary computer when I travel. Its replacement

Re: gEDA-user: Icarus, way to get module instance name?

Timothy Normand Miller wrote: > Does Icarus (or Verilog) have a way to find out the current module > instance name? I have some $display statements where I'd like to > distinguish between different instances of the same module. > It supports the %m format string, which is standard. It gives you

gEDA-user: First Snapshot of Simbus

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I've successfully simulated a non-trivial PCI device using my new simbus package, so I think it's time to make the first snapshot:

Re: gEDA-user: [iverilog] running the git source of Icarus Verilog

Günter Dannoritzer wrote: > Jared Casper wrote: >> On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer <[EMAIL PROTECTED]> >> wrote: >>> So with the latest development snapshot it gave me an assertion, but >>> with the git version a segmentation fault. >>> >> I saw this behavior as well, so I don

Re: gEDA-user: [iverilog] running the git source of Icarus Verilog

Günter Dannoritzer wrote: > Hi, > > I tried to install Icarus Verilog from git and wonder whether I did > something wrong, as when things go wrong it crashes with a segmentation > fault. > > I have to say that I have the latest development snapshot installed in > parallel in the standard path.

Re: gEDA-user: [icarus] task automatic causes assertion

I think there is a bug report related to this in the icarus verilog bugs tracker already. "automatic" tasks are not supported yes, and there is a patch that I recently applied that reports this as a proper error. Günter Dannoritzer wrote: > Hi, > > I tried compiling some Verilog code with a 'tas

Re: gEDA-user: poll: How do you geda?

Kai-Martin Knaak wrote: > I am curious, just how heterogeneous the group of geda users and > developers is. So I thought, I'd start this little non-random sample poll > in the mailing list: > > * What OS do you run geda applications on? Linux (openSUSE 10.x) Mac OS X (10.5 Intel) > * How did y

Re: gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process

[EMAIL PROTECTED] wrote: > Good day! > I'm just a NB in Verilog design, sorry if my question is too stupid :) > > I've started with free Xilinx ISE, but now i'm trying to do my best to > take part in icarus verilog community. > > I became familiar with IV modelling system, but synth restrain my a

Re: gEDA-user: Removing default title box

Stuart Brorson wrote: > You're a power user. Power users generally know about system-gschemrc, > right? Or is that an invalid assumption? That to me is an invalid and totally exasperating assumption, actually. My opinion (for what it's worth) is that even power users want things clear and conven

Re: gEDA-user: paging Steve Williams

When that happens, you can send to my gmail account at steveicarus at the usual gmail.com. In fact, at this instant that would be more convenient as I'm furiously hacking away on my mac, where I can read gmail. In the mean time, I'll look at the mail blocker. Spam musta come from comcast. Dan

Re: gEDA-user: A Verilog AMS program to try

Dan McMahill wrote: > Stephen Williams wrote: >> Does anybody have access to a Verilog-AMS tool and can said person >> attempt to run the attached sample program? It is a very simple >> program, but it is an attempt to test some of my understanding of >> very basi

gEDA-user: A Verilog AMS program to try

Does anybody have access to a Verilog-AMS tool and can said person attempt to run the attached sample program? It is a very simple program, but it is an attempt to test some of my understanding of very basic principles of Verilog-AMS. I understand that Verilog-AMS tools are very few and very far

Re: gEDA-user: Icarus build problem?

Evan Lavelle wrote: > I was on autoconf 2.59, which comes with Centos 4.4. I couldn't > immediately find a 2.61 rpm, so I did the AP_CHECK_FUNCS hack, which let > everything compile. Thanks. Maybe I'll just change it to AC_CHECK_FUNCS and leave it at that. The difference is subtle and not really

Re: gEDA-user: Icarus build problem?

Evan Lavelle wrote: > I can't run configure after downloading from git and sourcing > autoconf.sh. The output from configure ends with: > > checking for BZ2_bzdopen in -lbz2... yes > checking for BZ2_bzdopen in -lbz2... (cached) yes > ../../git2/verilog/vpi/configure: line 4002: syntax error near

Re: gEDA-user: PCB drill file question

More often then not, when I had problems like that with Icarus Verilog it turned out to be different handling (by the O/S) of dynamically allocated memory. One or the other (I forget which) will leave random data in malloc'ed memory. If malloc'ed data is not initialized, this can lead to code down

Re: gEDA-user: Open VHDL Simulators?

Attila Kinali wrote: > On Fri, 25 Apr 2008 14:04:38 -0700 > Stephen Williams <[EMAIL PROTECTED]> wrote: > >> As you know, this year's Icarus Verilog GSoC candidate is working >> on a VHDL code generator back-end for Icarus Verilog. Hooray! >> But suddenly t

Re: gEDA-user: Open VHDL Simulators?

Attila Kinali wrote: > On Sat, 26 Apr 2008 09:22:17 +0200 > Hagen SANKOWSKI <[EMAIL PROTECTED]> wrote: >> Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs. > > Uhm... I don't think i have to comment on something uneducated > like this, do i? Right, let's please not fall int

gEDA-user: Open VHDL Simulators?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, "How are we going to run these generated files?" I'm here looking for suggestio

Re: gEDA-user: Iverilog synthesis problems

Darren Stevens wrote: > Hello Stephen > There are however a very large number of logic gate entries, AND2, AND2B1, > AND2B2.. AND3 (up to 9 inputs IIRC) along with OR, NAND XOR etc.. > > So I editied the EDF file and changed the LUT2 entry to AND2 - ngdbuild was > quite happy with that. I even ma

Re: gEDA-user: Iverilog synthesis problems

Darren Stevens wrote: > Hello All, > > I've been trying to use a Digilent XLA development board fitted with a Xilinx > spartan XCS10 fitted. > > Since the Xilinx free tools for this chip don't include a synthesis tool I've > been trying to use Iverilog, with some success. I'm surprised by that.

Re: gEDA-user: Icarus Verilog: specify path for $readmemh?

Günter Dannoritzer wrote: > Hi, > > I am using the system task $readmemh to init some ROM. Now my question > is, can I specify for the simulation with Icarus somewhere the path to > the file I am using with $readmemh? I can think of 2 ways: You can use $value$plusargs at run time to get the path

Re: gEDA-user: PC emulator and HDL

Ahmad Sayed wrote: >>> John Griessen wrote: >>> Are you thinking of making your special parallel port driver >>> GPL and eventually part of linux? That would make a great tutorial > approach for iverilog... > > when i reach reasonable point, i'm going to do so, I just want with this > discussion

Re: gEDA-user: PC emulator and HDL

Ahmad Sayed wrote: > Dear all, > > I have an idea of a project, but actually i'm software developer rather than > hardware designer, so i need you to help me to figure out the usability of > it, my idea in short focus on the circuit designed to work wih computer e.g. > computer prephierals. > I ne

Re: gEDA-user: Icarus Verilog vvp32 on 64bit systems

Günter Dannoritzer wrote: > Stephen Williams wrote: >> Question: >> >> Does *anybody* use or even see value in the 32bit runtime support >> that Icarus Verilog includes in 64bit builds? In particular, there >> is support in the Icarus Verilog source for building si

gEDA-user: Icarus Verilog vvp32 on 64bit systems

Question: Does *anybody* use or even see value in the 32bit runtime support that Icarus Verilog includes in 64bit builds? In particular, there is support in the Icarus Verilog source for building simultaneously a vvp (64bit) and a vvp32 (32bit) to support 32bit VPI's transported from 32bit system

Re: gEDA-user: Icarus Verilog issues with Teal

Günter Dannoritzer wrote: > Hi, > > I am looking into using Icarus Verilog with Teal/Truss, a C++ based > verification framework. > With Icarus 0.8.6 all tests but the last, with release of a_wire, are > working. It's probably a matter of it not being implemented yet. Looks like a candidate for

Re: gEDA-user: Math functions and PLI

I believe the current Icarus Verilog vvp now has all the infrastructure needed to support real-valued system functions, and there are some PLI2 functions that return real values. So the PLI1 support is just a matter of providing the right translation layer code to make it work. Any volunteers? La

Re: gEDA-user: Icarus Verilog Release 0.8.6

Werner Hoch wrote: > Ok. I've build it now with the bz2 devel files from the i586 arch. > (not yet in the build service) > > Is there an easy way to test the 32bit verilog files? > I'm not an verilog user. Yes, run vvp32 instead of vvp. The reason for the "vvp32" is to have a 32bit runtime that

Re: gEDA-user: gEDA-dev: iverilog and Xilinx 8.2

Daniel O'Connor wrote: > I now get.. > [inchoate 9:43] ~/work/fpga/SA >iverilog -y . -y > $XILINX/verilog/src/unisims -y $XILINX/verilog/src/XilinxCoreLib SA_test2.v > /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: syntax error > /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: error: syntax error

Re: gEDA-user: Icarus Verilog Release 0.8.6

Dan McMahill wrote: > Stephen Williams wrote: >> -BEGIN PGP SIGNED MESSAGE- >> Hash: SHA1 >> >> >> I've made a new release on the Icarus Verilog v0_8-branch git branch. >> This is 0.8.6, which includes various safe fixes and updates to the >&

Re: gEDA-user: gEDA-dev: iverilog and Xilinx 8.2

Daniel O'Connor wrote: > [moved to -user] > On Sun, 2 Dec 2007, Stephen Williams wrote: >> 2) This looks like a problem long since fixed. Version? > > I originally had 0.8.5 - I tried 0.8.6 but no change. > [inchoate 13:55] ~/projects/verilog-0.8.6 >iverilog -V &

gEDA-user: Icarus Verilog Release 0.8.6

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I've made a new release on the Icarus Verilog v0_8-branch git branch. This is 0.8.6, which includes various safe fixes and updates to the stable release. The source tarball and release notes are here:

Re: gEDA-user: Icarus Verilog: library module search

Alan M. Feldstein wrote: > I'm using > > -y dir-path > > in the command file to add to the library module search path after using > an external tool to locate a module definitions in specific > subdirectories of > > $(DV_ROOT)/libs > > The problem is that such a subdirectory will of

Re: gEDA-user: list of cell types emitted by icarus synthesis?

IVL_LO_* for logic gates, and IVL_LPM_* for more complex gates. That is of course a proper superset of what might come out of a completed synthesis as a small handful of devices are purely virtual. Adam Megacz wrote: > Stephen Williams <[EMAIL PROTECTED]> writes: >> An appro

Re: gEDA-user: list of cell types emitted by icarus synthesis?

Adam Megacz wrote: > Does anybody know where I might find a comprehensive list of the EDIF > cell types emitted by icarus' synthesis back-end? I'd like to try to > get an idea of where the finish line is in terms of supporting all the > cell types it might throw at my stuff. An approximation of t

gEDA-user: Icarus Verilog Release 0.8.5

This is the first time I've used git to spit out a release. I have to say, using the git-gui to scan the commits really puts the summary of changes right there in my face. Writing release notes is tons easier this way. Anyhow, the release tarball is here:

Re: gEDA-user: Can't route

DJ Delorie wrote: > In theory, via-in-pad lets you bring an extra row out on the top > layer. It might mean the difference between 12 and 14 layers. Also, if you avoid masking the bottom side of the via, you suddenly have scope access to every pad of the BGA, which I've found to be amazingly use

Re: gEDA-user: icarus for-generate support

Matt Ettus wrote: > Got another one for you. I am now using the latest git version as of > this morning. I get the following assertion when trying to compile > the attached files. They are short, but I put them in a tarball. The > code shouldn't do anything useful yet, but I believe it is > syn

Re: gEDA-user: icarus for-generate support

Your example below is within the skills of Icarus Verilog, but there was a very recent fix for exactly this problem. According to my git logs, it was committed 6/11/2007, which is *after* the very last snapshot. So try the current git. (It should be in the present but stopped CVS as well.) Matt

Re: gEDA-user: Icarus Verilog going git.

Dave McGuire wrote: > On Jun 16, 2007, at 1:19 AM, Samuel A. Falvo II wrote: >> Well, yeah, it was authored by Linus Torvalds, so that's to be >> expected. I think it's gotten a _little_ looser since then, but it's >> still predominantly assuming a Posix-compatible environment. > >Not OS X or

gEDA-user: Why gperf (was Re: Icarus Verilog going git.)

Dave McGuire wrote: > On Jun 16, 2007, at 1:04 AM, Samuel A. Falvo II wrote: >>>Fortunately, gperf is an easy one to deal with. And damn cool to >>> *use*, too...I've used it in a number of projects and it has been >>> fantastic. >> I did not even know it existed until just now. >> >> It's sai

Re: gEDA-user: Icarus Verilog going git.

Samuel A. Falvo II wrote: > On 6/15/07, Stephen Williams <[EMAIL PROTECTED]> wrote: >> Well, I've made my choice and I'm starting the transition over >> to using git for Icarus Verilog. I've made my personal repository >> and I've made anonymous

gEDA-user: Icarus Verilog going git.

Well, I've made my choice and I'm starting the transition over to using git for Icarus Verilog. I've made my personal repository and I've made anonymous access to it at the url: git://icarus.com/~steve-icarus/verilog It this repository you'll be able to *immediately* pull anything that I push

Re: gEDA-user: Verilog to logic gates - how?

Predrag Bradaric wrote: > So, here is what I am trying to do and just don't know how! :) > I want to write a verilog 'program', compile it, synthesize it and as > a result get a netlist file (or what ever) that lists basic and > sequential logic > circuits with a description of connections between

Re: gEDA-user: [icarus] completely open source fpga toolchain

Adam Megacz wrote: > Stephen Williams <[EMAIL PROTECTED]> writes: >> The v0.8 releases of Icarus Verilog have decent synthesis. The >> synthesis is not at all Xilinx specific, but the code generators >> are. But they needn't be. The FPGA target generates EDIF, so if

gEDA-user: Looking for a gadget

I'm looking for a simple gadget that can connect two RS232 ports to an ethernet. I have a pair of solar grid-tie inverters in an under-the-house utility room. I have ethernet down there but no computers nearby and I would like to hook the RS232 monitoring ports to software or a workstation upstair

gEDA-user: Re: speaker source

DJ Delorie wrote: > FYI, this is what a prototype mp3 player module looks like: > http://www.delorie.com/electronics/alarmclock/mp3-proto.html > > You can see how small the test speakers are in that photo. We can also see that the desk is heaped up a couple of layers deep. Not unlike my desk, act

gEDA-user: Re: [icarus] completely open source fpga toolchain

This is pretty kool. You've got a big job in front of you! Adam Megacz wrote: > So, now that the abits work is published [1] I plan on turning my > attention to "connecting the dots", so to speak. > > I've pretty much resigned myself to the fact that I'll have to > implement PAR by hand (VPR has

gEDA-user: Re: iVerilog's Strengths [bug?]

[EMAIL PROTECTED] wrote: > module test; > tri blah; > > assign (pull1, strong0) blah = 0 ? 0 : 1; > assign blah = 0; > > initial > $display("Blah should be 0: %d", blah); > endmodule > > Output: > > Blah should be 0: x Bug. It appears tha

gEDA-user: Re: icarus and dual-port rams

Matt Ettus wrote: > I get the following errors when trying to compile a dual-ported ram in > icarus. I'm sure my syntax must be bad somewhere, but I can't see > where. This bug should have been fixed. The 2**FOO is exponentiation that was not understood until the fix to be a constant expression.

gEDA-user: Re: iverilog: Parameters of Parameters

[EMAIL PROTECTED] wrote: > In any case, as I stated in my last email, > this feature probably isn't good to add, > strictly because it seems to be nonstandard. > > However, the lack of such a feature shows > the poor thought of Verilog's designers. > > The burden is on the programmer, not > the t

gEDA-user: Re: iverilog: Parameters of Parameters

[EMAIL PROTECTED] wrote: > module A (input theInput, output theOutput); > parameter delay = 2; > > // Do something > > endmodule > > module B (input theInput, output theOutput); > parameter delay = a.delay + 5; > > A a(theInput, theOutput); > >

gEDA-user: Re: Reeling over Reals

Good bit of detective work here. It seems likely you can work around the assert by explicitly saving the $bitstoreal results in a temporary an passing that temporary into your task. No, this is not a threading issue, there is some funky recursion that seems to be going on here. I would look at th

gEDA-user: Re: BUGS: iverilog reals

Looks like there are some bug reports in here. I'm pretty busy with a big task at the moment so I may not get to these right away, so that makes filing bug reports even more important. [EMAIL PROTECTED] wrote: > The following compiles > (and probably shouldn't, unfortunately): > > module re

gEDA-user: Re: iverilog: Preprocessing requires \n

[EMAIL PROTECTED] wrote: > The preprocessor fails when a directive is on the last line (on a line > without a newline). > > PS > Should I just submit such information in a bug report? Yes, a bug report would be nice, with an example that demonstrates the problem. -- Steve Williams

gEDA-user: Re: Efficient Memories

On 5 Apr 2007, at 11:22:18 AM, Stephen Williams wrote: > >> [EMAIL PROTECTED] wrote: >>> I've made a BMP image format creating module for fun. >>> >>> I maintain a 640x480 24-bits per pixel buffer and then write the data >>> out to a file. >>&

gEDA-user: Re: Efficient Memories

[EMAIL PROTECTED] wrote: > I've made a BMP image format creating module for fun. > > I maintain a 640x480 24-bits per pixel buffer and then write the data > out to a file. > > At first I used a reg array, but came to find that each element of such > a structure > is expressed in vvp assembly as d

gEDA-user: Re: Icarus Verilog PLI example: PLI_INT32 vs static int

Günter Dannoritzer wrote: > I modified the vpi_user.c to not needing the other application that > comes along with that chapter 2 example and compiled it with: > > iverilog-vpi pow_vpi.c vpi_user.c > iverilog -opow_test.vvp pow_test.v > vvp -M. mpow_vpi pow_test.vvp > > The output I am gett

gEDA-user: Re: Icarus Verilog PLI example: PLI_INT32 vs static int

Günter Dannoritzer wrote: > Hi, > > I am trying out some examples from the Sutherland PLI book and for the > calltf, compiletf, and sizetf routines the book uses PLI_INT32 type as > return type. > > On the Icarus VPI page http://iverilog.wikia.com/wiki/Using_VPI page in > hello.c example I see th

gEDA-user: Re: Some Linux distros to consider

Chitlesh GOORAH wrote: > As from the next fedora buildsystem release (tonight): > Fedora users will be having: > geda-gattrib-20070216-1.fc6 > libgeda-20070216-1.fc6 > geda-gschem-20070216-1.fc6 > libgeda-devel-20070216-1.fc6 > libgeda-doc-20070216-1.fc6 > geda-gsymcheck-20070216-1.fc6 > geda-symbo

gEDA-user: Icarus Verilog release 0.8.4

This is a new release of the 0.8.4 stable branch of Icarus Verilog. The 0.8.4 release is for those people who are sticking with the stable branch in order to avoid the occasional breakages of the development snapshots, but still want some more important bug fixes. The release is here:

gEDA-user: Re: Icarus Verilog with Xilinx simprims...

Evan Lavelle wrote: > Günter Dannoritzer wrote: >> Andy Peters wrote: >>> Does iverilog support SDF backannotation? The SDF has the delay >>> information. >> >> Here are some information about that and a link to a previous discussion: >> >> http://iverilog.wikia.com/wiki/Graffiti#SDF_support > >

gEDA-user: Re: Icarus Verilog with Xilinx simprims...

CSB wrote: > First, I generate the post-fit verilog module from Xilinx ISE > project navigator. This is the .v file containing all the nets > and gates, for example X_AND2, etc... If I'm correct, those are > defined in the *.v files of the XILINX/verilog/src/simprims/ > directory, one file for each

gEDA-user: PCB GTK Layer controls

Are the Layers controls dialog box buttons connected to anything? I try to move one of the existing layers out of the group that it is in to a group of its own (I'm trying to create a ground plane) but it doesn't stick. It's as if the radio button of the group select are not connected to anything.

gEDA-user: Where are the bugs databases?

I'm fiddling with gschem/gattrib/gsch2pcb/pcb and find that I may want to report bugs. What I need now, though, is a place front and center that has links to the various bug reporting databases. I know that there are a few on sourceforge, but there is nothing written (other then mailing list lore)

gEDA-user: Re: Flame about XML (was: Some footprints I tried to create)

Michael Sokolov wrote: > Dan McMahill <[EMAIL PROTECTED]> wrote: > >> vi layout.pcb >> pcb -x gerber layout.pcb > > Thank you, Dan, for expressing it so succinctly! This is exactly how I > use PCB at the present moment. Of course it would be just a tad too > difficult to do the whole layout thi

gEDA-user: Re: How to program PAL/GAL?

Philipp Klaus Krause wrote: > Is Icarus PAL still alive? Not especially. No one seems to be programming pals these days, and using FPGAs instead. -- Steve Williams"The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.c

gEDA-user: Re: Nested for loop?

[EMAIL PROTECTED] wrote: > On Sat, Mar 10, 2007 at 10:11:32PM -0500, [EMAIL PROTECTED] wrote: >>> Nested for loops don't seem to work in iverilog. >>> it would seem that only the inner loop is updated. >>> >>>reg signed [7:0 ] x, y; >>>for (x = -128; x < 128; x = x + 1) > > Stop r

gEDA-user: Re: Nested for loop?

[EMAIL PROTECTED] wrote: > Nested for loops don't seem to work in iverilog. > it would seem that only the inner loop is updated. > > Consider the following: > > module TestMultiplier; > > reg signed [7:0 ] x, y; > wire signed [15:0] z; > > initial > begin > $dum

gEDA-user: Re: gEDA-announce: Information about Google Summer of Code and the gEDA Project

Stuart Brorson wrote: > * Any open-source organization can have several proposed projects for > a Google-supported student to work on. The list of projects is being > formulated and will be posted on the gEDA website soon. Once that's > done, students are invited to apply to work on one or anoth

gEDA-user: Re: gEDA-announce: Free Dog Meeting on March 8th in Reading, MA!

Stuart Brorson wrote: > The meeting will be an open and informal working session. Bring your > laptop *and* wireless card! Some items on the agenda are: > * Steve's FPGA design flow Is that me you are speaking of? Should I be trying to figure out irc stuffies? -- Steve Williams

gEDA-user: Re: google checkout buttons to implement SW development bounties

John Griessen wrote: > Stephen Williams wrote: >> al davis wrote: > >> An advantage of electronic payments is that they can be done >> internationally with little fuss by credit card. >> >>> I can't see paying just anyone who comes along for enhan

gEDA-user: Re: google checkout buttons to implement SW development bounties

al davis wrote: > Why all that overhead? > > The people who made the software have already established a > track record. Anyone funding it will do so based on that. We > don't need the middleman. They can just send a check. An advantage of electronic payments is that they can be done interna

gEDA-user: Re: google checkout buttons to implement SW development bounties

John Griessen wrote: > Creating google checkout buttons is easy -- if you have no shipping > costs, (as in FOSS added to project CVS or SVN repository), you could > have a series of them for small project chunks, and they get paid as you > go... > > Take for instance the $500 project. divide it

gEDA-user: Re: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)

David Kuehling wrote: >>>>>> "Stephen" == Stephen Williams <[EMAIL PROTECTED]> writes: >> Maybe we need to hire someone to implement the appropriate e-commerce >> site;-) > > Maybe just use an existing site? :) > > http://www.opensourcex

gEDA-user: Re: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)

al davis wrote: > On Monday 26 February 2007 21:46, Ales Hvezda wrote: >> 3) Hire a developer. I'm sure there are several developers >> here who are willing to fix your favorite pet peeve. But >> this, of course, won't be cheap, as everybody's free time is >> extremely valuable. > > Financing th

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