Hi,
(Sorry for the top post)
No autorouter is needed... Just place the generated symbols on a grid, so they
don't touch, and add wire stubs to each pin. Each wire should have a netname
attribute attached.
The netlister will connect all similarly named nets together.
Any reason you can't jus
John Griessen wrote:
> This is probably a Mike Jarabek question:
>
Could be... Sorry for the delay, got swamped.
> I don't get usable hierarchic netlist output when I have placed schematics
> and use the gnet-verilog.scm back-end.
> It drops the module definitions and end
Hi All,
DJ, it looks like it's time to add that single sided support to PCB:
http://blog.makezine.com/archive/2009/02/mobius_circuit.html
I just saw this, and could not resist sending it off. Not sure if the maker
here is on our list or not...
Mike Jarabek
http://www.sentex.ca/~mja
John Griessen wrote:
> I'm using Mike Jarabeck's gnetlist plugin and studying verilog ams with
> creating gnucap compatible netlists in mind.
>
> When I run:
> gnetlist -g verilog verilog_io.sch
>
That would be the right way to run it.
>
> I get unknown in one slot...
>
> /* Package instantiations
Kipton Moravec wrote:
> I have 1.4.0-20080127 installed.
>
> Installed it with synaptic manager with Ubuntu 8.04.
>
> I need to update convert_sym in the util package.
>
> I downloaded the latest version of convert_sym and made some changes. It
> will not let me compile because
>
> configure: erro
Kipton Moravec wrote:
> "Program name: convert_sym
> Written by: Mike Jarabek
> convert_sym takes ViewLogic Viewdraw schematic or symbol and outputs a
> gschem compatible file. This utility should be considered a work in
> progress. Be warned, this program has quite a few
des age,
especially if you use the PIN diode for power feedback.
I have even seen people drive these like an LED with a series ballast
resistor, but this does not protect the diodes from destruction as they
age, or protect them from over current.
> On Fri, Aug 29, 2008 at 10:46 PM, Mike Jar
Robert Butts wrote:
>
> Below is the link to the datasheet of a laser diode in using. It's
> not clear how I would wire this. Any suggestions on how to wire these?
>
> Digikey link:
> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=67-1500-ND
>
> Datasheet link: http://www.lum
>The code was designed for a CPLD, so perhaps there is a difference. In
>ISE, with the FPGA I'm putting down buffer symbols which tell it what
>kind of IO to use. If you could directly map the "INOUT" port to a pin
>on the chip (where "0" or "Z" output states would make sense), that
>works intuitiv
Hi,
The PS export code doesn't currently handle tabs. Except in the case where
the text is rendered as vectors. If you look in the gschemrc files you will
find the knob that controls this.
The other option is to use two text items and line them up manually.
--Original Message--
Hi,
You could try using a relative path, that is:
Replace "Romfile.txt" with "../sim/Romfile.txt"
This might get you past the problem, at the expense of forcing the directory
structure to always have the file in the 'sim' directory. I think the Xilinx
tools can deal with the slashes.
Hi,
VCD is fully specified in the Verilog LRM. It was also present in the Synopsys
Verilog-XL documentation, if you can find that.
--
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http
world.
--
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca/~mjarabek
--
-Original Message-
From
7;_' where
you want it to end.
--
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca/~mjarabek
--
-Origin
Benjamin
>
>
> ___
> geda-user mailing list
> geda-user@moria.seul.org
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
>
--
--
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca/~mjarabek
to pass and the rats nest will work too.
--
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca/~mjarabek
;real' camera stores.
--
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca/~mjarabek
--
-Original Message-
From: John Griessen <[EMAIL PROTECTED]>
Date: Tue, 17 Apr 2007 09:3
plots for me.
--
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca/~mjarabek
--
-Original Message-
ny changes. .
--
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca/~mjarabek
--
-Original Message-
From: Steven Michals
net)
Hope this helps. I think there is a getting started guide on the wiki for you.
--
Mike Jarabek
FPGA/ASIC Designer, DSP Firmware Designer
http://www.sentex.ca
the number of international characters.)
I think that I favour #1, but I have to think carefully about what
happens when someone actually wants to put a /Ydieresis in their
schematic...
--
------
Mike Jarabek
; v 20061020 1
> C 2000 0 0 0 0 title-A.sym
> ---File end---
>
> Try to print them with default settings.
Thanks, I will look into this. That bit of code had me drawing lots of
little vector drawings, I may have made a mistake somewhere.
--
---
ng routine that under certain circumstances
may
> cause a print to be miscentered.
Can you elaborate?
--
--
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
ehaviour
is configurable through the system-gschemrc. Look for the the
'line-style' rc command for the details.
--
--
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
since your last
install of the symbols package.
--
------
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
--
would recommend an approach that limits the
current to, say, about 10mA. Since this is a static signal, you can
probably simply connect it up via a resistor as you suggest.
--
--
ll get loaded if the
LD_LIBRARY_PATH is not set correctly, or you have edited ld.so.conf.
Mike
--
--
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
t
have the needed line in it. Are there any log messages that get printed
when you print?
--
--
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
--
clude both the schematic _and_ the postscript
output, in case there are locale issues with the number printing.
Thanks,
Mike
--
------
Mike Jarabek
FPGA/ASIC Designer
perhaps an FPGA for generating
> > VGA (640x480) video.
> >
>
> this would work - but is probably 1 device more than required.
> 1 is usually easier than 2.
> john
>
>
> > Thanks.
> >
>
>
>
> _______
ors could have larger values and the
capacitors smaller values if the inverters are CMOS.
Does a Schmidt input inverter cost too much?
--
------
Mike Jarabek
;-)
>
> (ok, so it's more than just a *soldering* challenge ;)
--
------
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
--
h directory to create
symbols from text files that drive gmk_sym.
source-library adds a path to search for schematics and
component-library adds a path to search for the symbols.
Hope this helps.
Mike
--
anks.
Mike
--
--
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
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Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
-
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--
------
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
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--
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Mike Jarabek
@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
--
------
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
--
___
geda-user mailing list
Jarabek wrote:
>
> > Odd.. Do you get this with with GhostScript or with the actual printer?
>
> With 'gv' and 'ps2pdf'.
>
--
---
Mike Jarabek
t;
> Any suggestions to make it all come out looking good?
If there's a bug in the output, I will fix it, if there is a workaround
that does not break anything else for your printer, I can add it.
Mike
--
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