With my setting of having the polygons on an extra layer I'm not
able to place thermals. When trying this, the command is simply
ignored.
The thermal tool places thermals to the active layer. You need to have
the layer that the polygon is actually on as the active layer in ord
I thought it was a very well-known feature; it was reported in 2007
([1]http://sourceforge.net/tracker/?func=detail&aid=1800872&group_id
=73743&atid=538811);
Yes, but that bug report came with a request explicitly asking that it
not be fixed!
References
1.
http://sourcef
I'm not going to stop working on the toporouter (greenlight?) just
because Google didn't fund us. If people keep hassling me, I'll
probably
find the time for small commits here and there.. e.g., most of my
work
last year was an answer to some scathing criticism from Ha
Can you guys keep this on the geda-dev list in future.. it is always
fun
to see how things are progressing.
Certainly, if Anthony and I discuss anything now that GSoc is not to
be.
Previously, I couldn't subscribe or send to the geda-dev list (or user
for that matter). T
> I submitted my first PCB bug report to SF last month (#2946254),
and
> shortly after added a patch that fixed the problem. I must admit
that
> the lack of response was discouraging - but I fully appreciate
that
> the developers are time poor (I am also!).
On Fri, 2010-03-05 at 00:28 +, Kai-Martin Knaak wrote:
> On Wed, 03 Mar 2010 20:40:54 +, Peter Clifton wrote:
>
> > Perhaps the pin identifier U102-J1-1 is causing issues.
>
> So this may be another incarnation of the hyphen-nastiness? Would
it be
> po
Hi,
First time using TSSOP48.
All rats, except those to/from TSSOP48, were successfully
autorouted.
Is this a limitation in version 20080202 of pcb, or am I missing
something?
Stan
The most likely reason is that the pins themselves are violating the
spacing
Is there any way to get better resolution? One degree is 25 mils at
my radius.
Sure, draw yourself a nice short straight segment. If your arc is extra
ordinarily thick, draw a trapezoidal polygon instead.
The point here is that even a 1 degree arc "at your radius" is
virtual
Hi!
> Do you mean that you want the simple PCB to be a fragment which
gets
> inserted into other designs? (option 2).
This one.
Pcb can load a .pcb file with the "load element to buffer" command,
which you can thing rotate, move to the other side, etc and then paste
Okay, so, how can I increase the clearance on all holes without
doing each
and every one individually?
Select whatever you need larger clearances around, then do
:ChangeClearSize(selected,+x,mil)
where x is the amount of extra clearance you need (in mils) to make
the sl
> > Is there some way I can easily get rid of the little slivers of
copper
> > left between traces when doing pours?
>
> Not without adjusting the clearance on the adjacent lines to
squeeze out
> the slivers. I've considered several times how to fix this, and
>> Can you confirm that version still works as you wanted?
>
> It does -- sort of.
>
> The command
>
> pcb -x eps --action-string 'DISPLAY(Value)' --eps-file foo.eps bar.pcb
>
> does indeed output a layout with values displayed, even if the last saved
> version of pcb showed refdeses.
>
> However,
> Does geda have a .pcb file viewer, such as is output by the ExpressPCB free
> software for windows? I've got a small tabletop milling machine, and have
> been asked to do a board that is about half the size of a postage stamp.
>
> And, if so, can it convert a .pcb into a couple of .ngc's for fee
> Stefan Salewski wrote:
>
> I wonder if the PCB autorouter should be more closely bound to the
> gschem schematics. For example, in the schematics we may specify
> priority of nets (fast signals, power, ...), trace width or clearance
> for net segments. Maybe by attributes? I have no idea how co
A bunch of fixes and enhancements to the original pcb autorouter
should now be available in the git repository. Here is a short how-to
for using the autorouter
(1) turn off visibility of any layers you don't want the router using
(2) turn of via visibility if you don't want it to
--- Ben Jackson <[EMAIL PROTECTED]> wrote:
>...
> The code that tries to walk around creating
> the joined contour
> doesn't find a starting point, so the combination is
> "nothing" and thus
> the hole vanishes.
I've fixed it (and probably a couple of other related
degenerate touching conditions
--- Martin Maney <[EMAIL PROTECTED]> wrote:
>... I used it with the pin
> slightly reduced (1),
> and the clearances work fine, but on the wrong
> sides...
Actually this is simply that you have the layer named
"component" on the solder side and the layer named
"solder" on the component side. Tha
--- steve manley <[EMAIL PROTECTED]> wrote:
> Is there a hotkey or other technique to manually set
> a X Y coordinate
> for a part, or via, without editing the main PCB
> source file? There
> doesn't appear to be anything obvious in either the
> manual or the
> FAQ, but that doesn't mean it
Hi Ralf,
Try again. I did fix one error with the previous
patch; now the other is fixed too. Your test example
works now (at least for me).
harry
--- [EMAIL PROTECTED] wrote:
> Thank you for looking into it.
>
> Hmm, updating CVS fond this in polygon.c:
>
> Well, it is still happening. test
--- DJ Delorie <[EMAIL PROTECTED]> wrote:
>
> > What happens here is that the clearance of the pad
> is increased, but
> > the copper moves into the clearance of the
> adjacent pad.
>
> I've reproduced this. Harry, could this be a
> clipper bug?
Yep, it's fixed in cvs now.
h.
_
The clearances can be "tweaked" while observing them
using the check polygons setting. There is no "all
that" involved in the "tweaking" process.
There is a danger to morphing and directly exporting a
gerber however: A restored region could intersect
multiple "joined" line and thus cause a change
--- DJ Delorie <[EMAIL PROTECTED]> wrote:
> Does it convert them to independent polygon objects,
> or just tag it to
> be not-split? In this case, it would be better to
> leave it as a big
> rectangle and do the clearance on the fly, so one
> could edit the board
> and have the polygon follow it
The "PolyArea" is value specifies the minimum area a
poly region must have to survive a "MorphPolygon()"
operation.
Use the ":MorphPolygon(Object)" command to "restore"
the dead copper areas larger than PolyArea to the
board. This command converts the disjoint copper areas
into separate polygons.
--- Peter Clifton <[EMAIL PROTECTED]> wrote:
> Does anyone care to comment / speculate how much a
> standard can cover by
> Copyright? Whether symbols looking similar (or the
> same, even) are in
> breach of Copyright? If one symbol on its own isn't,
> is there some
> "literary work" in the databa
I've fixed the problem in rats.c; Just grab the latest
cvs.
h.
--- Seb James <[EMAIL PROTECTED]> wrote:
> In that case I have the changes you made, and I am
> still seeing the rats
> nest problem.
No need
I noticed the problem is occuring during an extremely
high zoom in. pcb used to have code to clip the zoomed
lines to the screen in order to prevent integer
overflow. With the advent of hid that was removed and
now zooming in runs the risk of overflow with its
unlimited zoom capability.
It's very
> Ok, wart city.
>
> Why is it 'Edit|Move selected to current layer' for
> some things and
> 'Select|Move selected elements to other side' for
> elements?
>
> Why is there "moving to layer", "mirror" and "flip"?
>
> Why is mirror only for things buffers, moving only
> for lines and text
> and
--- DJ Delorie <[EMAIL PROTECTED]> wrote:
> Lesstif has a "thindraw polygons" option that does
> basically that.
> Unfortunately, the clipper makes it useless because
> it doesn't know
> about the flag, so you see hundreds of polygon slice
> outlines. I need
> to move all the thindraw stuff to o
--- Craig Niederberger <[EMAIL PROTECTED]> wrote:
> 1. Is it possible when autorouting traces in PCB to
> have some automatically
> set to one set of thicknesses, drill hole sizes,
> etc. and others
> automatically set to another set of thicknesses,
> drill hole sizes, etc? Or
> must I always s
> Because the postscript and pdf prints, on screen,
> have faint lines
> between slices, and I didn't know if the DRCbots
> were going to
> complain about them.
Strange. I'm sure the postscript is drawing those
faint lines but they shouldn't be visible since they
are on top of or beneath a solid
-> That's one. Another is that the rats for a net
> don't go away unless you
> can get your line to end exactly the right place,
> which doesn't work for
> me even with "snap to pad".
That's pretty hard to believe. The connectivity is
checked by a rigurous intersection test, no particular
points
--- Lares Moreau <[EMAIL PROTECTED]> wrote:
> No! it's not implemented yet.
>
> This is what I have started to implement. Let me
> know what you think.
>
I think before putting much effort in to this, the
patch contributed to sourceforge should be evaluated.
>From my looking at the patch itsel
--- Dan McMahill <[EMAIL PROTECTED]> wrote:
> Hello,
>
> I have uploaded a new pcb snapshot to sourceforge.
The change list fails to mention one of the new
features is a change of cursor shape to visually
indicate when the arrow tool will grab the end-point
of a line before you grab it.
__
--- Ben Jackson <[EMAIL PROTECTED]> wrote:
> ... I would like the ratsnesting to
> work in a sane
> fashion and I'd like auto DRC to let me actually
> draw traces to pads in
> the same net...
>
Please explain what is not sane about the rats nest.
The auto DRC prevents making connections that a
I have fabricated a board that had multiple clipped
polygons on both sides with fairly complex features.
It came out perfect. I fabbed it through pcbexpress.
If it looks correct with a trusted gerber viewer, I'd
say you can fabricate with confidence.
--- DJ Delorie <[EMAIL PROTECTED]> wrote:
>
--- Ben Jackson <[EMAIL PROTECTED]> wrote:
> Why isn't that the default? [lines, arcs clear
polys]
It used to be and might still be. This is a preference
that you can set. If a default installation doesn't
have that as the default it's probably because someone
else argued that the default shou
--- Hans Nieuwenhuis <[EMAIL PROTECTED]> wrote:
> Hi,
>
...
> - Routestyles can be adjusted on a net level basis
> in manual and
> autorouting
>
...
> Routestyles:
> So far I have them working ok just for manual
> routing, autorouter does
> not work yet.
The autorouter already completely honor
--- DJ Delorie <[EMAIL PROTECTED]> wrote:
> > Is there a better place to post bugs?
>
> There's a sourceforge bug tracker. Both that and
> the list have pros
> and cons:
>
> list: pro: your bug gets seen. con: your bug gets
> lost or forgotten
>
> tracker: pro: your bug gets remembered. con
--- KURT PETERS <[EMAIL PROTECTED]> wrote:
> I'm trying to autoroute only a selected group of
> rats. I selected them
> using SHIFT-click, and tried to autoroute selected
> rats (ALT-R).
> I get the message: The rats nest is stale!
> Aborting autoroute.
> So... I pressed O, and tried again.
In general you don't want a solid connection between a
pad and plane - without thermal relief it is difficult
to solder the connection. So odds are you want a
thermal relief, which presently you must manually draw
for pads.
With that said, you can create polygons that have no
clearances (for anyth
--- Tomaz Solc <[EMAIL PROTECTED]> wrote:
> After experimenting a bit with this, I found out
> that the mark is always
> placed where the "select" menu currently is. This is
> probably the point
> where the user interface last "saw" the mouse cursor
> in the viewport.
>
Before the introduction o
--- Lares Moreau <[EMAIL PROTECTED]> wrote:
> OKay really weird.. IT's a bug in the GTK version.
> If you select the label then try to move it, it will
> not move.
> However if you deselect the label it can be moved
> easily. Odd..
>
> -Lares
Actually whenever you want to move one single thin
--- DJ Delorie <[EMAIL PROTECTED]> wrote:
>
> > 1) Long lines do funny things if zoomed in a lot.
>
> I've recently seen short lines and arcs get exploded
> in the lesstif
> version too, but haven't tracked it down yet.
The "new" GUI drawing code simply scales the line and
then converts the (n
--- DJ Delorie <[EMAIL PROTECTED]> wrote:
> Lesstif, definitely. It's based on Xt, like Xaw, so
> you can control
> it through .Xdefaults to look as modern or as
> "ancient" as you like.
> I use it with fvwm, with a minimalist colored
> scheme.
>
> The Lesstif HID is designed to give maximum
I'm not sure if this is really fair to call a bug in
CircuitCAM. It's a little ambiguous as to whether
multiple layers of the same design should have a
common aperture definitions.
pcb's gerber driver that I wrote (before the HID was
introduced) used a common table for all gerber files
within the
Tuck Hartshorn wrote:
(btw, why is there no ":DisplayFlag(selected,join)" ?)
What would you have this command do?
You can get a report on any individual track with the ctrl-r key.
The actual flag is named "clearline" and is logically opposite from the
"join" notion that we used to name th
Tuck Hartshorn wrote:
On Friday 22 December 2006 20:37, DJ Delorie wrote:
latest as in cvs?
I got cvs but it failed to make completely. The current cvs is missing
some .pngs in the ./doc dir, namely puller.png and thermal.png
But, I thought the binary might be ok, anyway. And, it
Are there plans to introduce visual
handles at the end of the lines?
I have checked in changes to the CVS tree that create a cursor change
indicating when dragging will move the line end-point.
I've also cut the slop range in half, which helps the useability quite a
bit too.
harry
Steve Meier wrote:
I think at this point, in order to avoid confussion.
1) That gaf and pcb need to state if they consider the distributed
symbols and land patterns to be code.
I have never considered land patterns to be code. I'd be perfectly happy
for a font-like exception being clearly s
John Griessen wrote:
So. with those ideas in mind, a GUI or hotkey set of commands to
switch between different weightings of costs for different signal paths
would be good. Different rules for RF and short med speed digital paths,
and audio and heat dissipating power zones.
switch easily betwe
DJ Wrote:
>Have you tried just naming the pins all the same?
>
>The autorouter might not do the right thing, but DRC shouldn't
>complain.
Just for clarification, he means NUMBERING the pins the same.
Pcb element pins (and pads) have both names and numbers. The
numbers are what are used for check
Tomaz Solc wrote:
Is anyone interested in the output produced by xev? It is a bit too long
to send to the mailing list.
If you annotate it (i.e. label the points before/after you got the
bad scroll I'll look at it.
___
geda-user mailing list
ge
Tomaz Solc wrote:
Do you have any idea what application would be stealing the focus? I'm
not running anything special - just the stock GNOME installation that
comes with Debian. Gschem and other tools don't seem to have any
problems with this.
I have no idea really, but you might learn somethi
Tomaz Solc wrote:
As far as I can see lesstif doesn't have this bug. But as I said, this
behavior is not deterministic, so maybe it's just less common than in GTK.
I don't see this behavior with either gui ever. Here is something I'd
like you to try:
Go to the pcb/src directory and run:
Levente wrote:
Hi all,
Is there any way to switch off clipping in PCB?
I'm not sure what you mean. You can make any polygon non-clippable (i.e.
solid, nothing will clear any copper from it) with the "s" key. Does
that help?
___
geda-user mai
Dan McMahill wrote:
It had never occurred to me to use anything but an upper case alpha
character followed by a numeric value for a refdes, but students have a
habit of trying the unexpected. It threw me for quite a while trying to
understand what pcb was complaining about, since it referred to
DJ Delorie wrote:
Tips like this really help cut down the learning curve.
The curve would be shorter if it just didn't do that, of course.
With the current CVS code, it doesn't do that.
Is their a way to assign a "PCB layer" or set of copper to a
specific net? So for instance my G
Christian Treldal wrote:
søn, 29 10 2006 kl. 00:36 -0400, skrev DJ Delorie:
PolyArea[2.00]
Take this line out.
Tnx. Right on the spot; but wasn't it clever if PCB wasn't afraid of
those lines, or deleted them automatically. It makes it easier to update
old project
Stefan Salewski wrote:
Hello,
two weeks ago I send my gerbers to board manufacturer
www.bilex-lp.com.
Just get the board back: Looks fine, but polygons building ground
plans on solder side are missing, so board is useless.
PNG pictures of pcb layout are available at
http://www.ssalewski.d
Harry Eaton wrote:
The new polygon clipping code will dice up any polygon that has holes
in it into smaller ones that don't have holes and they just touch,
they don't overlap.
I should clarify this statement. That is true of the Gerber output, but
not the other types of output,
Dave N6NZ wrote:
In fooling with various practice layouts (partial layouts, actually) I
think I have the basics of polygons and rectangles sorted out. Now
I'm wondering about the practicalities is adjoining poly's.
Here is the situation: In my design, there wants to be a polygon patch
of an
Levente wrote:
I think you should morph the polygon into its pieces, then use the f-key
to highlight those that are connected
This is what I did on the top side, since a big polygon was not drawn.
Anyways, thanks for your help, and again, for implementing this clipping thing!
I thi
David Carr wrote:
Just curious,
How are you handling arcs in the polygons? Are you using line
segments as an approximation or are you actually using an arc
primitive? If you are using line segments, does the number of
segments vary on the diameter or is it fixed?
Your 100K vertex comment
Levente wrote:
I've tested this clipping toy for a while. I think the best thing would be if there was a
way to recalculate dead areas; hence for example, if you add a via in a dead area, and in
the other side if there is some GND present, the area can be again filled. So somehow it
should be
Levente,
I should point out that bf1.pcb has two identical copies of a
self-intersecting polygon (that's bad) at lines 8427 and 8432.
I think you want to delete one of the polys and drop the last point in
the poly.
harry
___
geda-user mailing
Peter Clifton wrote:
Fixes are in. Grab the latest CVS and give it a go.
Is this still the clipper branch of CVS, or HEAD?
This is the HEAD. Clipper is dead now that it is merged.
h.
___
geda-user mailing list
geda-user@moria.seul.or
Levente wrote:
...
Please find the pcb file via this link.
http://web.interware.hu/lekovacs/cuccok/hardware/bf1.pcb
What an excellent example of Swiss Cheese! There was a bug in the layer
group loop macro using the PCB group settings instead of the one in the
file loading.
It took a ver
DJ Delorie wrote:
Don't forget the chemicals, tanks, protective gloves, resist,
photomask (or equivalent).
I'm all set on that. I did the two prototypes for the smd challenge
myself, for example, that's 6 mil rules.
How do you put on your LPI soldermask? Do you use an old turntable to
DJ Delorie wrote:
Plus the usual problem of obtaining the thin outer clads, and precise
enough drilling.
Don't forget the chemicals, tanks, protective gloves, resist, photomask
(or equivalent).
___
geda-user mailing list
geda-user@moria.seul.
Vaughn Treude wrote:
Hello everyone:
I've been checking my board layout with the Design Rule Checker command
in PCB. I was encountering some mysterious behavior and wondering if
anybody could explain this a little.
1. The default minimum spacing is 10 mils, yet DRC flags everything that
is exa
Let's suppose for example I've just drawn a new line and overshot
the target. I don't seem to be able to just select that unconnected
endpoint and pull it back to where the place where it should
connect. Well, actually I CAN select the line, but when I drag it
always makes the entire new line
Jeff VR wrote:
I'm looking for some help in debugging this problem. Is there an
intermediate step I can run to try and figure out if the problem is
with the footprint or my schematic? What triggers the m4 library to
kick in?
All elements are loaded through m4, but most newlib elements don'
Unfortunately, I have family commitments so I won't be able to
participate in the code sprint.
I have been sprinting on my own quite a bit recently solving the
long-standing problem of dead copper in polygons.
I have alpha-quality code up on sourceforge now and it could use some
testing, so if y
Kai-Martin Knaak wrote:
On Wed, 20 Sep 2006 21:00:40 +0100, Peter Clifton wrote:
You mean "grips" at the end of tracks when you hover over them?
Exactly :-)
Next step would be an additional grip in the middle of the track.
Drag this grip to keep the ends of the track in place and mo
DJ Delorie wrote:
No, but gpcb for gnu pcb might.
Although, are we really part of the GNU project? We can't just say
"we're gnu!" without getting accepted by them first.
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/
Dave N6NZ wrote:
Just getting serious about going for my first layout using pcb. I have
done some PC layout before, so my questions are all about how this
particular software works, not pc layout in general.
I have a test file with two parts and four nets the successfully
netlist (yay!) and
Kai-Martin Knaak wrote:
in closely the program requires that you grab it more accurately;
- the center can be hard to accurately estimate and when zoomed
^^^
Why is this so? It sort of nullifies the benefit of zooming in.
Vaughn Treude wrote:
Hello all,
I'm new to gEDA; I've been playing with it for a few weeks now, mostly
gschem and pcb. Whereas the gschem interface seems reasonably standard,
pcb is often maddeningly arcane. I understand that this program has
evolved over many years, so perhaps that explains i
Dan McMahill wrote:
Bonus points to anyone who can name the real inventor of the mixer in
question here. Hint: It wasn't Gilbert even though it's called a
Gilbert cell.
H. Jones I believe. Bob Widlar didn't design that particular cell
structure nor specifically generalize the trans-linea
Stefan Salewski wrote:
Hello,
if someone is interested to verify or investigate the problem of
pcb (PCB version 20060422) with ground-planes and autorouter
usage.
I have just verified that the current CVS version routes your test board
just fine. There is no need to place vias for the SMD
Stefan Salewski wrote:
if someone is interested to verify or investigate the problem of
pcb (PCB version 20060422) with ground-planes and autorouter
usage:
A number of bug fixes to the autorouter were made in July so you should
try using the latest CVS code.
__
81 matches
Mail list logo
