Sir,
Thought I would respond to your query.
Harold Skank
On Wed, 2008-06-04 at 09:55 +, Kai-Martin Knaak wrote:
> I am curious, just how heterogeneous the group of geda users and
> developers is. So I thought, I'd start this little non-random sample poll
> in the mailing list:
>
> * W
People,
I thought I sent this earlier, but it appears to have gotten lost
somewhere.
I don't know what's happened, but I'm having terrible problems getting
gschem up and running after upgrading to Fedora Core-8 on my 64-bit AMD.
I've attached a copy of gnetlist.log. I hope you can look at it and
People,
I don't know what's happened, but I'm having terrible problems getting
gschem up and running after upgrading to Fedora Core-8 on my 64-bit AMD.
I've attached a copy of gnetlist.log. I hope you can look at it and
give me some idea just what I've done wrong.
Harold
gEDA/gschem version
DJ (or whomsoever),
People,
I'm running the cvs/lesstif version of pcb-20070912 (because the
download version won't start properly). I'm having problems with the
commands not displaying results fully. For example the commands
Connects -> Optomize ratsnest will display ratsnest information on
the first request;
On Thu, 2007-10-25 at 14:12 -0400, DJ Delorie wrote:
> Could you send me (or post) your board?
Sorry, propriety issues here.
Harold Skank
>
>
> ___
> geda-user mailing list
> geda-user@moria.seul.org
> http://www.seul.org/cgi-bin/mailman/listinfo/
On Thu, 2007-10-25 at 11:25 -0400, DJ Delorie wrote:
> > 1) In an effort to get around some problems with polygons, I tried
> > to install PCB-20070912. Things seemed to go OK, but when I brought
> > the package up, my board appeared on-screen, but the CPU never
> > returned.
>
> What do you mean
People,
I running PCB-200702NN. Several problems!
1) In an effort to get around some problems with polygons, I tried to
install PCB-20070912. Things seemed to go OK, but when I brought the
package up, my board appeared on-screen, but the CPU never returned.
I'm running a 64-bit AMD with Fedora
Dan,
I've awaited this release for some time now, as I've been having
difficulty with some polygon issues on a large design. However,
following download, I was some surprised that I could not get the file
to compile.
I should mention that I'm running Fedora-7 on an AMD-64, and I was
attempting t
> On Sun, 2007-09-09 at 08:19 -0500, Harold D. Skank wrote:
> > Thanks, that's a thought. How do I get into the 32-bit mode?
> >
> > Harold Skank
>
> You'd have to recompile PCB.
>
> Before running configure, export the "CFLAGS" variable
On Sat, 2007-09-08 at 11:16 -0400, DJ Delorie wrote:
> > What I find is that frequently when I start a job (most recently miter),
> > the job starts OK, then the monitor shows that memory consumption starts
> > to grow until I see of the order of 99.0-99.5% memory commitment.
>
> Any messages in t
Thanks, that's a thought. How do I get into the 32-bit mode?
Harold Skank
On Sat, 2007-09-08 at 10:01 -0400, al davis wrote:
> On Saturday 08 September 2007, Harold D. Skank wrote:
> > I need to emphasize that I have my machine loaded to maximum
> > memory capacity.
People,
I'm having a pretty tough time here. I have a design using a Xilinx
Vertex-5 part with over 1100 pins. Other connectors have over 200 pins
as well, with 431 lines in the netlist file, and 14 to 16 layers.
My system is running Fedora-7, and the latest gEDA release (I think).
Specifically
People,
First some question, later some comments.
Question: In building footprints for FPGA's and high density
connectors, I have used via's in order to insure that a pad exists on
every layer, assuming that the router had access to these pads. Yet I
find that the auto-router won't connect to t
counted
for a 5 mil trace and 5 mil space you're back to a single trace between
pins.
Harold
On Sat, 2007-07-14 at 16:15 -0700, Steve Meier wrote:
> Harold,
>
> Can you check that again. 45 mills is 1.143 mm.
>
> Thanks,
>
> Steve Meier
>
> On Sat, 2
uses 1020 pin fpgas and was layed out on 12
> layers. One key is to be willing to swap io pins at layout time to
> minimize the need for traces to cross each other.
>
> Harold D. Skank wrote:
> > Mr. Jackson,
> >
> > I VERY MUCH appreciate your response and commen
atest number of layers I have had to use
in the past was 13. However, the router I was using was more
sophisticated (and VERY much more expensive).
So, 24 layers are a bit intimidating.
Harold Skank
On Fri, 2007-07-13 at 19:55 -0700, Ben Jackson wrote:
> On Fri, Jul 13, 2007 at 07:40:12
People,
I'm dying here.
I'm on a critical job, pretty large, sufficient that I had to recompile
for 24 route layers. Following the re-compile, I seem to be OK for
everything until I attempt to start a route, at which point I get the
"stale ratsnest" message.
I've delt with this message before,
DJ,
I'm beginning to feel a little dense. I re-ran configure as you
indicated below, but as far as I can tell, lesstif is not running. I
even went so far as to create a /home/lesstif_user directory, and did
the lesstif "configure-make-make install" operations in that directory,
then modified the
DJ,
I installed lesstif by downloading the source for lesstif-0.95.0 (which
seems to be the latest stable release) and the compile/make process
seemed to go OK. However, the file configuration to switch from gtk to
lesstif (for me at least) was less than straight forward.
Could you encapsulate t
DJ
OK, that worked and I now have 32 layers. Now (particularly on the
layers> screens, what do I do to be able to view
everything? With my current settings, even though I have 32 columns, I
can only see about the top 17, maybe 18 layers. And I can't reach the
confirmation button in the lower r
People,
I'm working with PCB, and my understanding was that I could increase the
number of layers available by re-compiling the program. I've used the
16 layers available (running default pcb-20070208) and I need to
increase the number of layers available to 32. Just how do I do this?
Harol
Harold Skank again.
On Sat, 2007-03-31 at 23:20 +0100, Peter Clifton wrote:
> I'm hoping to conduct a brief census of people who use multiple pages in
> gschem. I'm working on some code-changes to libgeda which may change the
> navigation model slightly, and wanted to see how it is used now.
>
>
Harold Skank here.
On Sun, 2007-04-01 at 00:03 +0200, Tomaz Solc wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> Hi
>
> > Is there some change in the current CVS release of PCB that causes the
> > earlier "20060822" version to not be able to read in a file saved by the
> > current C
People,
Please ignore my last posting. It seems I had some kind of line-wrap
problem in my project file for the "gsch2pcb" command. Once I got that
corrected, the netlist appears to be correct and things look OK now.
Sorry about the confusion, and I thank you people for a very usable
product (p
People,
Seems like I've been here before, but I can't seem to remember the
issues.
As briefly as possible, the problem is that I have a large schematic,
some 10 pages that include 8 large connectors, and 2 Xilinx, 1100 pin
fpga's. Currently, the only net that I have connected is "GND." When I
d
People (Stuart and Dan),
I appreciate your recent responses on my symbol/pcb-footprint problems.
I seem to have it resolved now, but I VERY little understanding about
what happened.
As I indicated earlier, I was running a CentOS system (an enterprise
RedHat derivative). Not only was I having pro
Dan,
Comments inserted below.
Harold Skank
On Sat, 2007-02-24 at 15:04 -0500, Dan McMahill wrote:
> Harold D. Skank wrote:
> > Dan,
> >
> > Sorry, I inadvertently sent you a copy of project1 using only 2 of the
> > symbol slots, Test_2.sch and Test_3.s
below.
Harold Skank
On Sat, 2007-02-24 at 12:33 -0500, Dan McMahill wrote:
> Harold D. Skank wrote:
> > Dan & Co.
> >
> > I have attached all the files revelant to this problem below, i.e. the
> > pcb footprint, the *.sym files from gEDA, the schematic and project
> >
Skank
On Sat, 2007-02-24 at 11:17 -0500, Stuart Brorson wrote:
> On Sat, 24 Feb 2007, Harold D. Skank wrote:
>
> > In order to make the information more readable, I have
> > broken the symbols into slots, 4 in the smaller case and 6 in the larger
> > case. Since none of th
People,
I need some help here. I'm trying to work with _LARGE_ symbols and
footprints. In the smaller case, over 1100 pins and in the larger case
over 1700 pins. In order to make the information more readable, I have
broken the symbols into slots, 4 in the smaller case and 6 in the larger
case.
t; could run it with --log, then send me the Install.log file it
> generates, then I could take a look to see where the installer died.
>
> Thanks,
>
> Stuart
>
>
> On Fri, 23 Feb 2007, Harold D. Skank wrote:
>
> > Stuart,
> >
> > I ran across your n
Stuart,
I ran across your new CD in looking through some gEDA stuff yesterday.
I thought that it might assist in my own problem, so I downloaded it and
attempted its installation. I might add that I've been a gEDA user for
many years now, and your release of a CD in *.iso format has been a
great
People,
I just created a 4-slot symbol and associated 1153 pin footprint for a
Xilinx element that I need to route. This morning I set out to test
these elements to see if they worked together OK. Well -
I created a dummy schematic composed of the 4 slot elements, and
connected the power and gr
Kurt,
My system searches for the m4's, but I've changed the extension in the
library so it never finds it.
Works for me.
Harold Skank
On Thu, 2006-12-21 at 20:26 -0500, KURT PETERS wrote:
> As luck would have it, I can't seem to get it to NOT use the m4's first.
> Does anyone know how
DJ,
Thanks for the info, that took care of the problem.
Harold Skank
On Tue, 2006-12-19 at 20:10 -0500, DJ Delorie wrote:
> > I'm running the 20060907 release of the gEDA tools. I'm getting
> > complaints from board houses that the vias placed on the board
> > (either auto or manual) ha
People,
I'm running the 20060907 release of the gEDA tools. I'm getting
complaints from board houses that the vias placed on the board (either
auto or manual) have no solder mask clearance (i.e. the vias and the
mask diameters are the same).
I realize that I can modify this situation by manually
People,
I'm using the PCB package from the 20060907 gEDA disk release (thanks to
Stuart Brorson).
In the course of my current design effort, I elected to move some bypass
capacitors to the back side (solder) of the board. No problem so far.
When I routed the board I found that router was attemp
People,
Sorry about that. It appears that I simply hadn't zoomed in enough.
The grid _IS_ there.
Harold Skank
On Fri, 2006-10-06 at 09:28 -0500, Harold D. Skank wrote:
> People,
>
> I can't find this reference in my mail notes, but I seem to recall a
> recent t
People,
I can't find this reference in my mail notes, but I seem to recall a
recent thread of problems from pcb-20060822 mentioning that the grid was
not visible in the most recent release of PCB. I have updated to the
200609?? version of PCB, and I am having the same problem.
Since I cannot fin
Samuel,
I have worked with least two different options you might be able to use.
First of all, I haven't tried this, but I believe that you can compile
Xilinx FPGA's directly from Icarus, as this program apparently was done
in cooperation with Xilinx. I have used Xilinx FPGA's, and I can
recommen
On Mon, 2006-08-28 at 11:29 -0400, Stuart Brorson wrote:
> Hi Guys --
>
> I have an electronics-type question, and perhaps I can try to tap into
> the knowledgebase on geda-user.
>
> I need to use some MOVs on my AC input power lines to cut down voltage
> transients which seem to make some of our
gEDA people in general,
This e-mail is in the nature of a "well done!" for your gEDA work. I'm
a hardware designer by training, and among other things I managed a
design system for a university electronics design group for some 10 to
15 years. Following my retirement, I began to use the gEDA to
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