defined functions library. I'm working on it
adding new features. If you have some particular in mind - let me know
please.
Thanks,
Alex.
On 04/17/2011 01:15 PM, rickman wrote:
On 4/4/2011 11:44 PM, Kai-Martin Knaak wrote:
A.Burinskiy wrote:
I did not saw satisfactory analog viewe
fficult to implement. In comparison, waveform viewers are relatively
easy and are being used all the time by almost every engineer working
in the field.
Thanks,
Andrzej
On Mon, Apr 4, 2011 at 8:45 PM, A.Burinskiy wrote:
Hi Kaimartin,
I did not saw satisfactory analog viewer for ngspice. Could y
:
A.Burinskiy wrote:
Due to name conflict I rename program zview to ngscope, did minor
corrections and submit it to sourceforge again.
Just curious: Why are there so many projects for viewers of simulation
data? I'd personally see the more immediate need in a better integration
of simulation
Hello,
Due to name conflict I rename program zview to ngscope, did minor
corrections and submit it to sourceforge again.
Thanks,
Alex.
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Hello,
Sorry for inconvenience, for some reason file was uploaded partially.
Please try again. md5sum in the readme. Will place screenshots soon.
Thanks,
Alex.
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Dear gEDA community,
I publish program on sourceforge.org that displays ngspice raw files.
Project name is zview. Appreciate any feedback.
Thanks,
Alex.
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Hi Al,
I have difficulty getting raw file as an output of simulation using
version that is shipped with Fedora 11. Does something changed since
that time? Or how I could get raw file out of simulation? (I'm going to
try big simulation that produces a lot of data)
Thanks,
Alex.
On 09/28/2009 0
John,
It is not a big deal to write a parser. The big deal is creating
meaningful language. Flexible enough, yet not overloaded with features,
transparent and logical, understandable not only for designer, but to
end user too. My problem is that I'm newbee for the PCB. Just started
using comme
On 08/10/2009 06:03 AM, John Doty wrote:
> On Aug 9, 2009, at 9:59 PM, A.Burinskiy wrote:
>
>
>> John,
>>
>> Do you mean that one day source= attribute is reference to schematic,
>> another day it is something else?
>>
>
> No, I mean that man
John,
Do you mean that one day source= attribute is reference to schematic,
another day it is something else? We have to stick to some reasonable
meaning of all attributes, at list to be able to exchange libraries and
collect our work over the years, isn't it?
Talking about ynetlist: it has exa
09 03:17 AM, r wrote:
> On Fri, Jul 31, 2009 at 8:49 PM, A.Burinskiy wrote:
>
>> Dear gEDA community members,
>>
>> I created yet another netlister for gschem. Netlister supports flattened
>> or hierarchical netlist, handles slotting and global net names. Will
/31/2009 04:42 PM, Dan McMahill wrote:
> A.Burinskiy wrote:
>
>> Dear gEDA community members,
>>
>> I created yet another netlister for gschem. Netlister supports flattened
>> or hierarchical netlist, handles slotting and global net names. Will be
>> glad to h
tlist
>
> At least gEDA users have plenty of choices now.
>
> On Fri, Jul 31, 2009 at 12:49 PM, A.Burinskiy wrote:
>
>> Dear gEDA community members,
>>
>> I created yet another netlister for gschem. Netlister supports flattened
>> or hierarchical netlist,
that you are going to use with pcb format, may
be I will be able to dig from that side to find what I have to put into
output file.
Alex.
On 07/31/2009 02:46 PM, Kai-Martin Knaak wrote:
> On Fri, 31 Jul 2009 12:49:57 -0700, A.Burinskiy wrote:
>
>
>> I created yet another netli
Dear gEDA community members,
I created yet another netlister for gschem. Netlister supports flattened
or hierarchical netlist, handles slotting and global net names. Will be
glad to hear any feedback. The source located in:
http://sourceforge.net/projects/ynetlist/files/
Thanks,
Alex.
___
John,
Could you please explain in detail, what does your comment mean?
/* Note that there was never any serious difficulty doing this with gnetlist -g
spice-sdb and a makefile.
*/
Thanks,
Alex.
On 06/30/2009 11:48 AM, John P. Doty wrote:
> Anthony Shanks wrote:
>
>> http://spnet.code-fusio
Take a look at my latch example on my website for
>> what the properties of subckts look like.
>>
>> Net stitch failure happens usually when there is a net without a
>> netname attached to one of the nets its connected too. There is no
>> autonet name feature yet but I
t a
>> netname attached to one of the nets its connected too. There is no
>> autonet name feature yet but I plan to add it.
>>
>> Also which devices in your schematic don't have refdes?
>>
>> -Anthony
>>
>> On Tue, Jun 23, 2009 at 1:59 PM, A.Burinskiy
o
autonet name feature yet but I plan to add it.
Also which devices in your schematic don't have refdes?
-Anthony
On Tue, Jun 23, 2009 at 1:59 PM, A.Burinskiy wrote:
Hi Anthony,
The reason for the message
-E- Fatal Error: Invalid Component attr "C 42200 44200 1 0 0 gnd-1.sym
for spnet. Take a look at my latch example on my website for
>> what the properties of subckts look like.
>>
>> Net stitch failure happens usually when there is a net without a
>> netname attached to one of the nets its connected too. There is no
>> autonet name feature
(right now):
>
> C 47000 49500 1 0 0 spice-lib.sym
> C 5 44900 1 0 0 v2i_2v.sym
>
> What are these? I assume the spice-lib.sym is a subckt netlist but I
> don't know what the other is.
>
> A quick fix in your case with the ground symbol is just to add the
> attribut
RCE
CURRENT_SOURCE
PIN
As stated I will add suport for [N|P]MOS_TRANSISTOR in the next
release as a 4 terminal mosfet device. Besides this, do you have any
components in your schematic that is not on the above list?
BTW, thanks for all your help in debugging.
Hi Anthony,
Yes, the cause of segfault are empty strings at the end of file. Do you
support comment out in .spnetlibs? I will go ahead and try your new code.
Thanks,
Alex
On 06/23/2009 03:03 AM, Anthony Shanks wrote:
> Wow. I guess I have a lot to learn as far as releasing code and
> compiling
Library: "tube"
-I- Adding Library: "xilinx"
-I- Combining Cells
-E- Fatal Error: Invalid Component.
Thanks,
Alex.
On 06/23/2009 01:10 AM, Anthony Shanks wrote:
> Thats really odd, I copied your line directly in my spnetlibs file and
> it worked fine. Maybe it&#x
to retrieve the libs which is
> a little cleaner (I worte this function a long time ago and haven't
> looked at it since) and uploaded it to the site (same version). Please
> re-download it and recompile it and let me know if it still give you
> this error.
>
> -Anthony
>
Hi Anthony,
Thanks a lot, now spNet compiles well.
When I run it I have following error:
$ spnet if.sch
spNet v0.9.1
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-E- Invalid lib file. Syntax: library: PATH "LibName"
[al...@bazilik buck1]$ more ~/.spnetlibs
library: /home/username/tsmc "
config.log? I'll get back to you in a few hours since I'm still at
work.
On Mon, Jun 22, 2009 at 3:47 PM, A.Burinskiy wrote:
Hi Anthony,
Thank you very much for the spNet. I'm trying to compile your tool. The
result is below:
$ make
Making all in src
make[1]: Entering directo
Hi Anthony,
Thank you very much for the spNet. I'm trying to compile your tool. The
result is below:
$ make
Making all in src
make[1]: Entering directory
`/home/alexb/Download/geda/spnet/spnet-0.9.1/src'
gcc -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\"
-DPACKAGE_STRING=\"\
Hi,
I'm using gnetlist -g spice-sdb ...
1. Netlister doesn't exctract subcircuits as a subcircuits, but correct
refdes instead.
It puts, for example MX1/M23 instead of
.subckt ...
M23
.ends
X1
2. netlister also doesn't correct Resistors. It is supposed that refdes
will be corrected as RX1
Whatever I'm doing in ngspice, I've get warnings about memory
$ more rtest2.cir
* Spice netlister for gnetlist
V2 1 0 DC 1.5V
V1 2 0 DC 0.5V
R1 2 1 rsh=1K w=100u l=10u tc1=3e-3 tc2=5e-7 narrow=0.05u
.dc temp -40 125 1
.print dc i(v1)
.END
[al...@bazilik geda]$ ngspice rtest2.cir
Warning - a
Hi,
In the manual parameter RSH declared, but in reality doesn't work.
$ more rtest2.cir
* Spice netlister for gnetlist
V2 1 0 DC 1.5V
V1 2 0 DC 0.5V
R1 2 1 rsh=1K w=100u l=10u tc1=3e-3 tc2=5e-7 narrow=0.05u
.dc temp -40 125 1
.print dc i(v1)
.END
[al...@bazilik geda]$ ngspice rtest2.cir
Warnin
I wrote simple command file:
$more com
source rtest3.cir
run
plot v(1,2)/i(v1)
save
$ ngspice -b com
Warning - approaching max data size: current size = 15.960 kB, limit = 0
bytes
Warning - approaching max data size: current size = 15.960 kB, limit = 0
bytes
Warning - approaching max data size: c
Please find patch file attached. I'm trying to add vc1,2 to res model.
Notation
R1 2 1 w=10u l=100u vc1=7e-5 vc2=1e-3
But
.model rmod (
+ VC1=7e-5
+ VC2=1e-3
+ )
R1 2 1 rmod w=10u l=100u vc1=7e-5 vc2=1e-3
Doesn't work. What I'm doing wrong?
Thanks,
Alex.
Common subdirectories:
ngspice-origina
Hi Stuart,
Thank you very much for the instructions. Following your instruction I
produced next patch and new symbol.
Thanks,
Alex.
--- geda-gnetlist-1.5.2/scheme/gnet-spice-sdb.scm2009-06-11
04:42:06.063911837 -0700
+++ geda-gnetlist/scheme/gnet-spice-sdb.scm2009-06-17
17:28:10.2360
Hi, I'm trying to make library include symbol, somewhat similar to
spice-include-1.sym. I created symbol:
v 20090328 2
B 0 400 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 100 300 9 10 0 1 0 0 1
device=library
T 100 500 9 10 1 1 0 0 1
refdes=A?
T 600 500 9 10 1 0 0 0 1
SPICE LIBR
T 500 200 8 10 1 1
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