On Wed, Nov 14, 2007 at 12:50:50AM -0500, DJ Delorie wrote:
>
> > BTW, any idea why shift-paste buffer does not replace the first time?
>
> First I've heard of it. ...tests... Works for me the first time.
Oh, I see what it is now, if the single-click into the window brings
focus, you can place
> BTW, any idea why shift-paste buffer does not replace the first time?
First I've heard of it. ...tests... Works for me the first time.
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On Tue, Nov 13, 2007 at 07:37:20AM -0500, DJ Delorie wrote:
>
> > I just noticed by chance (turned off the silk layer while looking)
> > that the silkscreen on the SSOP28 footprint overlaps the pads.
>
> I just fixed this a few days ago.
BTW, any idea why shift-paste buffer does not replace the
The bounding box math was still based on the old thermals. I checked
in a fix.
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Hi,
I have created the following element and I anticipated it to be 500 mil
dia so I expected to have the mounting hole 250 mil from the edges of
the pcb in each corner. The best I can get is about 320 mil as there is
a mysterious box round the element when selected. I need to have the
mo
John Doty wrote:
> "Do nothing gracefully".
>
>
I was going to get around to that ... tomorrow.
Steve m.
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On Nov 13, 2007, at 5:37 PM, Transistor Toaster wrote:
> Thanks Peter, I just put those in. Do you know if there's a DRC to
> flag
> errors on pins that are left totally unconnected (i.e. not even the NC
> symbol)?
>
Yes, there is, drc2 does that. Very annoying. Unconnected pins are
not erro
Unless something has changed recently, be aware that gnetlist will connect
all NC pins together on a net called No-Connect. You may need to manually
delete it from the netlist. If you make it "graphical" as Ben suggests, the
DRC may not see it(?) and thus can't flag it as an error. (Please chime
On Tue, Nov 13, 2007 at 05:51:05PM -0500, Transistor Toaster wrote:
> Hello,
> For unused pins in gschem, is there a no connect symbol? If so could
> somebody tell me where to find it?
I didn't find those others, I made this. The graphical=1 keeps things
from moaning.
v 20070526 1
P 0 100 100 10
On Tue, 2007-11-13 at 19:37 -0500, Transistor Toaster wrote:
>
> Thanks Peter, I just put those in. Do you know if there's a DRC to
> flag
> errors on pins that are left totally unconnected (i.e. not even the NC
> symbol)?
> Frank
Sorry, I don't know.. perhaps some of the DRC proponents will ans
Thanks Peter, I just put those in. Do you know if there's a DRC to flag
errors on pins that are left totally unconnected (i.e. not even the NC
symbol)?
Frank
On Wed, 14 Nov 2007 00:16:32 +, "Peter Clifton" <[EMAIL PROTECTED]>
said:
>
> On Tue, 2007-11-13 at 17:51 -0500, Transistor Toaster wr
On Tue, 2007-11-13 at 17:51 -0500, Transistor Toaster wrote:
> Hello,
> For unused pins in gschem, is there a no connect symbol? If so could
> somebody tell me where to find it?
> Thanks,
> Frank
There are a few...
under the "misc" library:
nc-bottom-1.sym
nc-left-1.sym
nc-right-1.sym
nc-top-1.
Hello,
For unused pins in gschem, is there a no connect symbol? If so could
somebody tell me where to find it?
Thanks,
Frank
--
Transistor Toaster
[EMAIL PROTECTED]
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On Tue, Nov 13, 2007 at 02:43:41PM -0500, DJ Delorie wrote:
> > behaviour if i export in gerber format...
>
> Yes. PCB always exports your whole work area, whether it has zero,
> one, or many outlines defined in it.
...and having a gerber with silk outside the board and an origin away
from 0 is
> > You're not missing anything. The "outline" layer is for the fab, not
> > for pcb itself. It lets you have an area outside the finished board
> > to work with, for example.
>
> OK, that's why i can place components outside this area, but as showed
> in the attachment (fab.ps and outline.ps),
On Tue, 2007-11-13 at 07:38 -0500, DJ Delorie wrote:
> You're not missing anything. The "outline" layer is for the fab, not
> for pcb itself. It lets you have an area outside the finished board
> to work with, for example.
OK, that's why i can place components outside this area, but as showed
in
On Tue, Nov 13, 2007 at 08:37:20AM -0500, John Luciani wrote:
>
> How different Is the SSOP from the TSSOP?
> I have a TSSOP-65P-640L1-28N on my site.
>From a JEDEC definition:
SSOP: Shrink Small-Outline Package; 0.65-mm lead pitch; 5.3-mm wide body
(MO-150; variation AA (8-ld)).
TSSOP: Thin S
On Tue, 2007-11-13 at 11:44 -0500, Dave McGuire wrote:
> On Nov 13, 2007, at 9:16 AM, Ian Chapman wrote:
> > Stupid question, using gerbv in ubuntu I go
> > Applifations/Education/Gerber viewer and I get the program up and
> > running. From gerbv I do File/Open project and according to man I
On Nov 13, 2007, at 9:16 AM, Ian Chapman wrote:
> Stupid question, using gerbv in ubuntu I go
> Applifations/Education/Gerber viewer and I get the program up and
> running. From gerbv I do File/Open project and according to man I
> should load the project file.
As an aside...why would it
On Tuesday 13 November 2007, Peter TB Brett wrote:
>On Tuesday 13 November 2007 13:31:40 ED wrote:
>> Not sure if its what you were looking for, however we have been playing
>> with these FTDI chips for a little while now and they have been working
>> great. Basically you plug this little beast in
On Tuesday 13 November 2007 13:31:40 ED wrote:
> Not sure if its what you were looking for, however we have been playing
> with these FTDI chips for a little while now and they have been working
> great. Basically you plug this little beast in and get a virtual serial
> port. Works as a USB to se
On Tue, 2007-11-13 at 09:31 -0500, Stuart Brorson wrote:
> Thanks for the kudos, but the real hero is Stefan, who wrote the
> program.
Sure, but thanks for answering my (unasked) question ;)
> I'll be checking in some patches and then spinning 1.0.3 any day now.
> (Dealing with this was part of
Thanks for the kudos, but the real hero is Stefan, who wrote the
program.
I'll be checking in some patches and then spinning 1.0.3 any day now.
(Dealing with this was part of our Free Dog gathering last Sun.)
After that we'll open up a quick discussion about future features in
gerbv, as well as w
On Tue, 2007-11-13 at 09:19 -0500, Stuart Brorson wrote:
> To view a Gerber file, do a right mouse button on one of the numbered
> buttons on the right, then use the pop-up menu to open the Gerber file
> you want to see. Then right mouse on the next button, and open the
> next layer, etc.
Stuart
To view a Gerber file, do a right mouse button on one of the numbered
buttons on the right, then use the pop-up menu to open the Gerber file
you want to see. Then right mouse on the next button, and open the
next layer, etc.
When you are done, you can save your layer arrangement as a gerbv
projec
Hi,
Stupid question, using gerbv in ubuntu I go
Applifations/Education/Gerber viewer and I get the program up and
running. From gerbv I do File/Open project and according to man I
should load the project file.
My question what is the project file and what do I put in it so as to
v
On Nov 13, 2007 2:29 AM, Ben Jackson <[EMAIL PROTECTED]> wrote:
> Anyone got a better SSOP? I bet John Luciani has some almost-perfect
> TSSOP scripts to modify. :)
Thanks.
How different Is the SSOP from the TSSOP?
I have a TSSOP-65P-640L1-28N on my site.
(* jcl *)
--
http://www.luciani.or
Not sure if its what you were looking for, however we have been playing
with these FTDI chips for a little while now and they have been working
great. Basically you plug this little beast in and get a virtual serial
port. Works as a USB to serial converter. Drivers for Linux, Mac, and
XP, Vi
You're not missing anything. The "outline" layer is for the fab, not
for pcb itself. It lets you have an area outside the finished board
to work with, for example.
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> I just noticed by chance (turned off the silk layer while looking)
> that the silkscreen on the SSOP28 footprint overlaps the pads.
I just fixed this a few days ago.
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This is the kind of thing B&B Electronics does. Check this page:
http://www.bb-elec.com/product_family.asp?FamilyId=19&Trail=2&TrailType=Top
Stuart
On Mon, 12 Nov 2007, Matt Ettus wrote:
> Anybody know of an RS232 to TTL level translator board or kit that
> comes complete? Possibly in a box?
Hi all,
I have followed some thread in the mailing list archive about outline
layer within pcb but...
So i have added a layer named "outline", i drawn a rectangle on it with
10mil line thickness, but now when i export as ps or even gerber, pcb
doesn't take my outline specification into account. I
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