Re: gEDA-user: Re: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)

Stephen Williams wrote: DJ Delorie wrote: Thank you Steve. Not speaking for the PCB developers, but I'm sure they appreciate the bug reports; I know I do. We appreciate all the feedback, with the understanding that we can only get to a tiny percentage of it at a time, as there's only a few o

Re: gEDA-user: Re: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)

> I'll tell you what. I'll pay you to fix your bugs if you pay me > to fix mine. Deal? :-) Fixing my own bugs is usually at the top of *my* todo list. But my comment... > We appreciate all the feedback, ... applies to more than just bug fixes. We also appreciate feedback about design choices

gEDA-user: Re: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)

DJ Delorie wrote: >> Thank you Steve. Not speaking for the PCB developers, but I'm sure they >> appreciate the bug reports; I know I do. > > We appreciate all the feedback, with the understanding that we can > only get to a tiny percentage of it at a time, as there's only a few > of us, and we o

Re: gEDA-user: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)

> Thank you Steve. Not speaking for the PCB developers, but I'm sure they > appreciate the bug reports; I know I do. We appreciate all the feedback, with the understanding that we can only get to a tiny percentage of it at a time, as there's only a few of us, and we only do this as a hobby. _

Re: gEDA-user: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)

[snip] >OK, "wart alert". I go into preferences and I expect to see the [snip] > >I'll file bug reports for these. Thank you Steve. Not speaking for the PCB developers, but I'm sure they appreciate the bug reports; I know I do. Just a reminder that there are really only three ways to get mis

gEDA-user: Re: PCB question

DJ Delorie wrote: >> I'm puzzled by this response. Under File->Preferences in the >> Library tab there is an entry box for "Element directories" that >> asks for a colon separated list of directories. Where does this >> list get stored? > > These are the times I like it when I'm wrong. Both gtk a

Re: gEDA-user: DRC problem at close pads

Dan McMahill wrote: David Kuehling wrote: "DJ" == DJ Delorie <[EMAIL PROTECTED]> writes: http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png Could you post (or send me privately) the .pcb file? Here is a simplified file that only contains the problematic footprint. Quite p

Re: gEDA-user: PCB question

DJ Delorie wrote: OK, I'm an idiot. How do I create a local (as in local to my design directory) library of PCB footprints? All the documentation I see suggests that it will automatically search in the "packages" directory in the current workig directory. No?! When you say "it will automaticall

Re: gEDA-user: Re: PCB question

> I'm puzzled by this response. Under File->Preferences in the > Library tab there is an entry box for "Element directories" that > asks for a colon separated list of directories. Where does this > list get stored? These are the times I like it when I'm wrong. Both gtk and lesstif allow colon-se

gEDA-user: Re: PCB question

DJ Delorie wrote: >> OK, I'm an idiot. How do I create a local (as in local to my design >> directory) library of PCB footprints? All the documentation I see >> suggests that it will automatically search in the "packages" >> directory in the current workig directory. No?! > > Note that a local dir

Re: gEDA-user: PCB question

> Agh can I add that as a wart? Yup :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user

Re: gEDA-user: PCB question

On Mon, Feb 26, 2007 at 07:59:02PM -0500, DJ Delorie wrote: > > Note that a local directory *overrides* the global one, as pcb only > supports one library at a time (er, one each of m4 and newlib). Agh can I add that as a wart? I don't remember this happening to me, but it might explain why

Re: gEDA-user: PCB question

> OK, I'm an idiot. How do I create a local (as in local to my design > directory) library of PCB footprints? All the documentation I see > suggests that it will automatically search in the "packages" > directory in the current workig directory. No?! Note that a local directory *overrides* the gl

gEDA-user: PCB question

OK, I'm an idiot. How do I create a local (as in local to my design directory) library of PCB footprints? All the documentation I see suggests that it will automatically search in the "packages" directory in the current workig directory. No?! -- Steve Williams"The woods are lovel

Re: gEDA-user: nets in symbols

Marc Moreau wrote: On Mon, 26 Feb 2007 16:06:57 + Seb James <[EMAIL PROTECTED]> wrote: Instead of using the nets GND and +5V, I have gnd_left and gnd_right and +5v_left and +5v_right. Can I redefine the nets for those pins after I placed the symbol in my schematic? Looking at your s

Re: gEDA-user: DRC: "Element Z50 has 5 silk lines which are too thin"

David Kuehling wrote: Hi, just another strange DRC error. This is caused by the oldlib-generated footprint "SMT_DIODE 15 8": Rules are minspace 5.92, minoverlap 5.91 minwidth 5.91, minsilk 7.09 min drill 1.00, min annular ring 15.75 Element Z50 has 5 silk lines which are too thin near

Re: gEDA-user: DRC problem at close pads

David Kuehling wrote: "DJ" == DJ Delorie <[EMAIL PROTECTED]> writes: http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png Could you post (or send me privately) the .pcb file? Here is a simplified file that only contains the problematic footprint. Quite possibly this is just a pr

Re: gEDA-user: nets in symbols

Gah! Attaching .sym's help. -Lares ATMega640-1280-2560_ADC.sym Description: Binary data ATMega640-1280-2560_IO1.sym Description: Binary data ATMega640-1280-2560_IO2.sym Description: Binary data ATMega640-1280-2560_pwr.sym Description: Binary data pgp0b6ysaTX1h.pgp Description: PGP signa

Re: gEDA-user: nets in symbols

On Mon, 26 Feb 2007 16:06:57 + Seb James <[EMAIL PROTECTED]> wrote: > Problem 2 > -- > I am placing this symbol in a design which is split into two regions, with > opto-isolators connecting them. This means I have two ground nets, and I also > have two 5V nets. > > Instead of using

gEDA-user: Master Parts List

I am putting together a master parts list table for my component database. I am trying to determine a good format for component part numbers. Are there any industry standards for this type of information? IPC documentation? I was thinking of starting with some of the IPC-7351 component category t

Re: gEDA-user: new boards!

> The teardrops look nice, DJ. Thanks! I've had traces detach from pins during rework, I'm hoping that the teardrops avoid the hard inside corners that sometimes lead to failure. Plus they're pretty :-) > What are the 3 long pads that appear next to some of the 20 pin and > 32 pin footprints (

Re: gEDA-user: new boards!

DJ Delorie wrote: Just showed up today... The teardrops look nice, DJ. What are the 3 long pads that appear next to some of the 20 pin and 32 pin footprints (on the top)? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cg

gEDA-user: new boards!

Just showed up today... http://www.delorie.com/house/furnace/pcb2/ First observations: pcb-pool's drills (m32c board) were off center a bit, coming close to touching the edges of the copper. Advanced Circuit's drills seem to be much more accurately aligned. I put "1 2 3 4" on each layer, it tu

Re: gEDA-user: Installer suddenly dying on Mandriva 2007.0

Al Hooton wrote: This is on a vanilla install of Mandriva 2007.0. I have looked through the list archives, the INSTALL information and googled around, but I'm stuck. Hopefully somebody here has the answer as to why the installer just suddenly gives up near the beginning of things.

Re: gEDA-user: dinotrace (Re: Which are the biggest looking gEDA warts?)

Hi Dan and all, On Monday 26 February 2007 17:20, Stephen Williams wrote: > Is it wrapped up into any Linux packages? Can you convince Werner > to include it in his set of tools that he packages for SuSE? How > 'bout Stuart's big build CD? > > Really, in the Linux world, dinotrace seems to be a we

Re: gEDA-user: Which are the biggest looking gEDA warts? REQUEST TRACKER

Adding attributes requires too much mouse work (selecting, careful pointing to position the attribute, then you use both hands to type a net name, hand back to mouse, etc). Use gattrib. That's what it's for. One Gripe... gattib: You can't use it like you expe

Re: gEDA-user: dinotrace (Re: Which are the biggest looking gEDA warts?)

About dinotrace How 'bout Stuart's big build CD? Good idea. I just added it to the ToDo list. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user

gEDA-user: DRC: "Element Z50 has 5 silk lines which are too thin"

Hi, just another strange DRC error. This is caused by the oldlib-generated footprint "SMT_DIODE 15 8": Rules are minspace 5.92, minoverlap 5.91 minwidth 5.91, minsilk 7.09 min drill 1.00, min annular ring 15.75 Element Z50 has 5 silk lines which are too thin near location (1942.91,1350.3

Re: gEDA-user: DRC problem at close pads

> "DJ" == DJ Delorie <[EMAIL PROTECTED]> writes: >> http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png > Could you post (or send me privately) the .pcb file? Here is a simplified file that only contains the problematic footprint. Quite possibly this is just a problem with the footpr

Re: gEDA-user: DRC: "Line with insufficient clearance inside polygon"

> "DJ" == DJ Delorie <[EMAIL PROTECTED]> writes: >> the DRC tells me "Line with insufficient clearance inside polygon". >> If I do Ctrl+R on the line in question, the clearance is correctly >> shown as 5.91mils (actually 0.15mm). 0.15mm is also my configured >> DRC clearance. > Look for tiny

gEDA-user: dinotrace (Re: Which are the biggest looking gEDA warts?)

Dan McMahill wrote: > Stephen Williams wrote: >> But instructions for using dinotrace with Icarus Verilog are >> certainly welcome: I recommend starting >> with a note in the FAQ page that would point to a dinotrace page. > > u are instructions needed? I've update

Re: gEDA-user: nets in symbols

On Monday 26 February 2007 16:06, Seb James wrote: > Hi again, > > I defined a new symbol, for the Mesa Electronics 7I33 daughter board. > > This has 104 pins, of which about half connect to ground. > > The start of the symbol file is appended to the end of this email, and I > attached the complete

gEDA-user: nets in symbols

Hi again, I defined a new symbol, for the Mesa Electronics 7I33 daughter board. This has 104 pins, of which about half connect to ground. The start of the symbol file is appended to the end of this email, and I attached the complete symbol file. If you look at the first 15 lines or so, you'll

Re: gEDA-user: DRC: "Line with insufficient clearance inside polygon"

> the DRC tells me "Line with insufficient clearance inside polygon". If > I do Ctrl+R on the line in question, the clearance is correctly shown as > 5.91mils (actually 0.15mm). 0.15mm is also my configured DRC clearance. Look for tiny traces under the pads. Hide the pins/pads layer to see the

gEDA-user: DRC: "Line with insufficient clearance inside polygon"

Hi, the DRC tells me "Line with insufficient clearance inside polygon". If I do Ctrl+R on the line in question, the clearance is correctly shown as 5.91mils (actually 0.15mm). 0.15mm is also my configured DRC clearance. Might that just be a rounding error which I can ignore? regards, David --

Re: gEDA-user: DRC problem at close pads

> http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png Could you post (or send me privately) the .pcb file? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user

Re: gEDA-user: gnetlist -gdrc2 output

Seb James wrote: I tried that, but it seems that the component doesn't have an explicit refdes of "U?". I suppose that somewhere there is a component which is missing the refdes altogether. If you search all your output files, ( -o drc_output.txt >drc_stdout.txt 2>drc_stderr.txt), for the sa

gEDA-user: PCB Element Positions

I created a script that outputs PCB element positions relative to the lower-left corner of the outline (that is defined in the outline layer). I found this useful when I needed to verify that a series of PCBs would mate. The script and the documentation is at http://www.luciani.org/geda/util/uti

Re: gEDA-user: Which are the biggest looking gEDA warts?

Dan McMahill wrote: No back-annotation. So, any volunteers? In pcb, ":Renumber()", then use the pcb_backannotate script. Try "pcb_backannotate --help" to get you going. I'm booked. Someone else? John G ___ geda-user mailing list geda-u

Re: gEDA-user: gnetlist -gdrc2 output

On Monday 26 February 2007 14:09, John Luciani wrote: > On 2/26/07, Seb James <[EMAIL PROTECTED]> wrote: > > Checking slots... > > ERROR: Multislotted reference U? has no slot attribute defined. > > > > It would be very useful if the schematic on which the U? element appears > > was printed. The pr

Re: gEDA-user: gnetlist -gdrc2 output

On Monday 26 February 2007 14:09, John Luciani wrote: > On 2/26/07, Seb James <[EMAIL PROTECTED]> wrote: > > Checking slots... > > ERROR: Multislotted reference U? has no slot attribute defined. > > > > It would be very useful if the schematic on which the U? element appears > > was printed. The pr

gEDA-user: DRC problem at close pads

Hi, I'm very close to having my first EDA design ready for production. I'm currently trying to make the PCB Design Rule Checker accept the PCB layout without complaining. There is one case where it complains about copper areas being to close, that I don't understand. Just look at the followin

Re: gEDA-user: gnetlist -gdrc2 output

On 2/26/07, Seb James <[EMAIL PROTECTED]> wrote: Checking slots... ERROR: Multislotted reference U? has no slot attribute defined. It would be very useful if the schematic on which the U? element appears was printed. The program where this should happen is get-drc2.scm. Having only programmed a

gEDA-user: gnetlist -gdrc2 output

Hello, I'm at the stage of processing my design through gnetlist so I can track down all the errors. I'm having a little trouble with the output generated by a call like: gnetlist -v -g drc2 pedio_5i20Aconn.sch pedio_5i20Bconn.sch ... (lots more .sch files) ... -o drc_output.txt >drc_stdout.tx

Re: gEDA-user: Which are the biggest looking gEDA warts?

Dan McMahill wrote: Dan McMahill wrote: Andy Peters wrote: On Feb 25, 2007, at 4:53 PM, Ben Jackson wrote: On Sun, Feb 25, 2007 at 05:07:59PM -0600, John Griessen wrote: No back-annotation. This is VERY important to me. As part of general cleanup after finishing a layout,

Re: gEDA-user: Which are the biggest looking gEDA warts?

Dan McMahill wrote: Andy Peters wrote: On Feb 25, 2007, at 4:53 PM, Ben Jackson wrote: On Sun, Feb 25, 2007 at 05:07:59PM -0600, John Griessen wrote: No back-annotation. This is VERY important to me. As part of general cleanup after finishing a layout, I renumber all of the re