Hi Mike,
Thanks for your comments.
Please find my comments inlined.
- Thanks and regards,
Sameera D.
On Monday 11 May 2015 10:09 PM, Mike Stump wrote:
On May 11, 2015, at 4:05 AM, sameera wrote:
+(define_insn "*join2_loadhi"
+ [(set (match_operand:SI 0 "regist
Gentle reminder!
- Thanks and regards,
Sameera D.
On Monday 30 March 2015 04:58 PM, sameera wrote:
Hi!
Sorry for delay in sending this patch for review.
Please find attached updated patch.
In P5600, 2 consecutive loads/stores of same type which access contiguous
memory locations are
On Tuesday 21 April 2015 12:39 AM, Matthew Fortune wrote:
Sameera Deshpande writes:
Gentle reminder!
Thanks Sameera. Just a couple of comments inline below and a question
for Catherine at the end.
- Thanks and regards,
Sameera D.
On Monday 30 March 2015 04:58 PM, sameera wrote:
Hi
On Monday 11 May 2015 05:43 PM, Matthew Fortune wrote:
Hi Sameera,
Sameera Deshpande writes:
Changelog:
gcc/
* config/mips/mips.md (JOIN_MODE): New mode iterator.
(join2_load_Store): New pattern.
(join2_loadhi): Likewise.
(define_peehole2): Add
/mips-protos.h (mips_load_store_bonding_p): New prototype.
*config/mips/mips.c(mips_load_store_bonding_p): New function.
- Thanks and regards,
Sameera D.
On Tuesday 24 June 2014 04:12 PM, Sameera Deshpande wrote:
Hi Richard,
Thanks for the review.
Please find attached updated patch
On Mon 9 Apr, 2018, 2:06 PM Sameera Deshpande,
wrote:
> Hi Richard,
>
> I do not see the said patch applied in ToT yet. When do you expect it
> to be available in ToT?
>
> - Thanks and regards,
> Sameera D.
>
> On 30 March 2018 at 17:01, Sameera Deshpande
> wrot
Hi!
Please find attached the patch implementing vld1_*_x3, vst1_*_x2 and
vst1_*_x3 intrinsics as defined by Neon document.
Ok for trunk?
- Thanks and regards,
Sameera D.
gcc/Changelog:
2017-11-14 Sameera Deshpande
* config/aarch64/aarch64-simd-builtins.def (ld1x3): New
Hi!
Please find attached the patch to add support of ARMv8.4 in saphira
for Qualcomm server part. Tested on aarch64, without any regressions.
Ok for trunk?
--
- Thanks and regards,
Sameera D.
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index
On Tue 29 May, 2018, 9:19 PM Siddhesh Poyarekar, <
siddhesh.poyare...@linaro.org> wrote:
> On 29 May 2018 at 21:17, James Greenhalgh
> wrote:
> > On Tue, May 29, 2018 at 05:01:42AM -0500, Sameera Deshpande wrote:
> >> Hi!
> >>
> >> Please find at
hich is
incorrect.
I am looking at TARGET_MACHINE_DEPENDENT_REORG macro instead like few
other architectures, to emit far branches.
Is that approach acceptable?
PS: I am waiting for customer's approval for attaching the test case.
--
- Thanks and regards,
Sameera D.
On 30-Jan-2018 2:37 AM, "Richard Sandiford"
wrote:
Sameera Deshpande writes:
> Hi!
>
> I am seeing multiple assembler errors with error message "Error:
> conditional branch out of range" for customer code.
>
> The root cause of the bug is that conditional
On 30 January 2018 at 09:28, Sameera Deshpande
wrote:
> On 30-Jan-2018 2:37 AM, "Richard Sandiford"
> wrote:
>
> Sameera Deshpande writes:
>> Hi!
>>
>> I am seeing multiple assembler errors with error message "Error:
>> conditional branch out o
, eliminated the
attribute completely, and computed the offset from insn_addresses
instead.
Ok for trunk?
gcc/Changelog
2018-02-13 Sameera Deshpande
* config/aarch64/aarch64.md (far_branch): Remove attribute. Eliminate
all the dependencies on the attribute from RTL patterns
On 14 February 2018 at 14:00, Sameera Deshpande
wrote:
> Hi!
>
> Please find attached the patch to fix bug in branches with offsets over 1MiB.
> There has been an attempt to fix this issue in commit
> 050af05b9761f1979f11c151519e7244d5becd7c
>
> However, the far_branch attri
On 27 February 2018 at 18:25, Ramana Radhakrishnan
wrote:
> On Wed, Feb 14, 2018 at 8:30 AM, Sameera Deshpande
> wrote:
>> Hi!
>>
>> Please find attached the patch to fix bug in branches with offsets over 1MiB.
>> There has been an attem
Ping!
On 28 February 2018 at 16:18, Sameera Deshpande
wrote:
> On 27 February 2018 at 18:25, Ramana Radhakrishnan
> wrote:
>> On Wed, Feb 14, 2018 at 8:30 AM, Sameera Deshpande
>> wrote:
>>> Hi!
>>>
>>> Please find attached the patch to fi
15/03/18 15:27, Sameera Deshpande wrote:
>>
>> Ping!
>>
>> On 28 February 2018 at 16:18, Sameera Deshpande
>> wrote:
>>>
>>> On 27 February 2018 at 18:25, Ramana Radhakrishnan
>>> wrote:
>>>>
>>>> On Wed, Feb 14, 2018
, Sudakshina Das wrote:
> Hi Sameera
>
> On 22/03/18 02:07, Sameera Deshpande wrote:
>>
>> Hi Sudakshina,
>>
>> As per the ARMv8 ARM, for the offset range (-1048576 ,1048572), the
>> far branch instruction offset is inclusive of both the offsets. Hence,
>> I am usi
Hi Sudakshina,
That testcase cannot be addwd as of now, as it needs approval from client.
On Thu 29 Mar, 2018, 9:01 PM Sudakshina Das, wrote:
> Hi Sameera
>
> On 29/03/18 11:44, Sameera Deshpande wrote:
> > Hi Sudakshina,
> >
> > Thanks for pointing that out.
>> I have tested it for gcc testsuite and the failing testcase. Ok for trunk?
>>
>> On 22 March 2018 at 19:06, Sudakshina Das wrote:
>>> Hi Sameera
>>>
>>> On 22/03/18 02:07, Sameera Deshpande wrote:
>>>>
>>>> Hi Sudakshina,
>
Hi Richard,
The testcase is working with the patch you suggested, thanks for
pointing that out.
On 30 March 2018 at 16:54, Sameera Deshpande
wrote:
> On 30 March 2018 at 16:39, Richard Sandiford
> wrote:
>>> Hi Sudakshina,
>>>
>>> Thanks for pointing tha
Hi Christophe,
Please find attached the updated patch with testcases.
Ok for trunk?
- Thanks and regards,
Sameera D.
2017-12-14 22:17 GMT+05:30 Christophe Lyon :
> 2017-12-14 9:29 GMT+01:00 Sameera Deshpande :
>> Hi!
>>
>> Please find attached the patch implementing vld
Hi Richard,
I do not see the said patch applied in ToT yet. When do you expect it
to be available in ToT?
- Thanks and regards,
Sameera D.
On 30 March 2018 at 17:01, Sameera Deshpande
wrote:
> Hi Richard,
>
> The testcase is working with the patch you suggested, thanks for
> p
On 7 April 2018 at 01:25, Christophe Lyon wrote:
> Hi,
>
> 2018-04-06 12:15 GMT+02:00 Sameera Deshpande :
>> Hi Christophe,
>>
>> Please find attached the updated patch with testcases.
>>
>> Ok for trunk?
>
> Thanks for the update.
>
> Since th
On 10 April 2018 at 20:07, Sudakshina Das wrote:
> Hi Sameera
>
>
> On 10/04/18 11:20, Sameera Deshpande wrote:
>>
>> On 7 April 2018 at 01:25, Christophe Lyon
>> wrote:
>>>
>>> Hi,
>>>
>>> 2018-04-06 12:15 GMT+02:00 Sameera Deshp
On 11 April 2018 at 15:53, Sudakshina Das wrote:
> Hi Sameera
>
>
> On 11/04/18 09:04, Sameera Deshpande wrote:
>>
>> On 10 April 2018 at 20:07, Sudakshina Das wrote:
>>>
>>> Hi Sameera
>>>
>>>
>>> On 10/04/18 11:20, Sameera
On Fri 13 Apr, 2018, 8:04 PM James Greenhalgh,
wrote:
> On Fri, Apr 06, 2018 at 08:55:47PM +0100, Christophe Lyon wrote:
> > Hi,
> >
> > 2018-04-06 12:15 GMT+02:00 Sameera Deshpande <
> sameera.deshpa...@linaro.org>:
> > > Hi Christophe,
> > >
&
finally rename the register is made - where the note can
be altered with new regname.
Other notes need not be changed, as they don't hold renamed register
information.
Ok for trunk?
Changelog:
2018-10-09 Sameera Deshpande diff --git a/gcc/regrename.c b/gcc/regrename.c
index 8424093..a3446a2 1
On 13 April 2018 at 20:21, James Greenhalgh wrote:
> On Fri, Apr 13, 2018 at 03:39:32PM +0100, Sameera Deshpande wrote:
>> On Fri 13 Apr, 2018, 8:04 PM James Greenhalgh,
>> mailto:james.greenha...@arm.com>> wrote:
>> On Fri, Apr 06, 2018 at 08:55:47PM +0100, Chr
On 1 May 2018 at 05:05, Sameera Deshpande wrote:
> On 13 April 2018 at 20:21, James Greenhalgh wrote:
>> On Fri, Apr 13, 2018 at 03:39:32PM +0100, Sameera Deshpande wrote:
>>> On Fri 13 Apr, 2018, 8:04 PM James Greenhalgh,
>>> mailto:james.greenha...@arm.com>> w
On Tue 22 May, 2018, 9:26 PM James Greenhalgh,
wrote:
> On Mon, Apr 30, 2018 at 06:35:11PM -0500, Sameera Deshpande wrote:
> > On 13 April 2018 at 20:21, James Greenhalgh
> wrote:
> > > On Fri, Apr 13, 2018 at 03:39:32PM +0100, Sameera Deshpande wrote:
> > >> O
-pairing): New option.
* config/mips/mips.c (mips_option_override): New exception.
*config/mips/mips.h (ENABLE_LD_ST_PAIRING): New macro.
- Thanks and regards,
Sameera D.
load-store-pairing.patch
Description: load-store-pairing.patch
>
> Are QImodes not paired in the same way? If so, it'd be worth adding a
> comment above the define_mode_iterator saying that QI is deliberately
> excluded.
The P5600 datasheet mentions bonding of load/stores in HI, SI, SF and DF modes
only. Hence QI mode is excluded. I will add the comment on the iterator.
- Thanks and regards,
Sameera D.
eliminated this mode iterator.
>
> Outer (parallel ...)s are redundant in a define_insn.
Removed.
>
> It would be better to add the mips_load_store_insns for each operand
> rather than multiplying one of them by 2. Or see the next bit for an
> alternative.
Using the alternati
Hi!
Please find attached the patch to add a pipeline description for the
Qualcomm Saphira core. It is tested with a bootstrap and make check,
with no regressions.
Ok for trunk?
gcc/
Changelog:
2018-10-26 Sameera Deshpande
* config/aarch64/aarch64-cores.def (saphira): Use saphira pipeline
On Tue, 9 Oct 2018 at 04:08, Eric Botcazou wrote:
>
> > Other notes need not be changed, as they don't hold renamed register
> > information.
> >
> > Ok for trunk?
>
> No, REG_DEAD & REG_UNUSED note must be recomputed by passes consuming them.
>
On Fri, 26 Oct 2018 at 13:33, Sameera Deshpande
wrote:
>
> Hi!
>
> Please find attached the patch to add a pipeline description for the
> Qualcomm Saphira core. It is tested with a bootstrap and make check,
> with no regressions.
>
> Ok for trunk?
>
> gcc/
>
On Tue, 30 Oct 2018 at 16:16, Richard Earnshaw (lists)
wrote:
>
> On 30/10/2018 10:09, Sameera Deshpande wrote:
> > On Tue, 9 Oct 2018 at 04:08, Eric Botcazou wrote:
> >>
> >>> Other notes need not be changed, as they don't hold renamed register
>
On Wed, 31 Oct 2018 at 00:37, James Greenhalgh wrote:
>
> On Tue, Oct 30, 2018 at 05:12:58AM -0500, Sameera Deshpande wrote:
> > On Fri, 26 Oct 2018 at 13:33, Sameera Deshpande
> > wrote:
> > >
> > > Hi!
> > >
> > > Please find at
atcher automatically?
Also, can you please comment on usability or scalability of this approach
across all the architectures or point me to appropriate people in the group
with whom I can discuss target specific vectorization issues?
- Thanks and regards,
Sameera D.Index: gcc/Makefile.in
=
promotion? If not, will push this patch on the branch that we have
created - unified-autovect.
- Thanks and regards,
Sameera D.Index: gcc/Makefile.in
===
--- gcc/Makefile.in (revision 243687)
+++ gcc/Makefile.in (working copy)
@@ -15
regards,
Sameera D.
Changelog:
gcc/
* config/mips/mips.c (mips_return_in_memory) : Restrict V4SFmode to be
returned in registers.
gcc/testsuite/
* gcc.target/mips/msa-fp-cc.c : New testcase.
Hi Matthew,
Please find attached updated patch as per our offline discussion.
I have disabled return in registers for all vector float types, and updated the
test case accordingly.
Ok for trunk?
- Thanks and regards,
Sameera D.
From: Sameera
Hi!
I have created new branch unified-autovect based on ToT.
Please find attached the patch adding information about new branch
"unified-autovect" in the documentation.
Is it ok to commit?
- Thanks and regards,
Sameera D.
unified-autovec-doc.patch
Description: unified-autovec-doc.patch
f that
can be done, I can eliminate the table here.
Updated ChangeLog entry:
2011-09-28 Ian Bolton
Sameera Deshpande
* config/arm/arm-protos.h (load_multiple_operation_p): New
declaration.
(thumb2_expand_epilogue): Likewise.
(thumb2_output_return)
>
>
> I don't believe REG_FRAME_RELATED_EXPR does the right thing for
> anything besides prologues. You need to emit REG_CFA_RESTORE
> for the pop inside an epilogue.
Richard, here is updated patch that uses REG_CFA_RESTORE instead of
REG_FRAME_RELATED_EXPR.
The patch is tested with check-
Hi Ramana,
Please find attached reworked patch. The patch is tested with check-gcc,
check-gdb and bootstrap with no regression.
Ok?
- Thanks and regards,
Sameera D.diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 05c9368..334a25f 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc
ng %P.
>
Paul,
Thanks for your comment. Please find attached reworked patch. The patch
is tested with check-gcc without regression.
- Thanks and regards,
Sameera D. diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 23a29c6..2c38883 100644
--- a/gcc/config/arm/arm-pr
e/vector-compare-1.c compilation, -O3
-fomit-frame-pointer -funroll-loops with error message
/tmp/ccC13odV.s: Assembler messages:
/tmp/ccC13odV.s:544: Error: co-processor offset out of range
This seems to be uncovered latent bug, and I am looking into it.
- Thanks and regards,
Sameera D.diff -
ith no regression.
- Thanks and regards,
Sameera D.diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index deee78b..4a86749 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -15960,6 +15960,135 @@ bad_reg_pair_for_thumb_ldrd_strd (rtx src1, rtx src2)
|| (REGNO
ot;}, {\"d1\"}, {\"d2\"}, {\"d3\"},
>
> I'm not keen on having this table. Generally the register names should
> be configurable depending on the assembler flavour and this patch
> defeats that. Is there any way to rewrite this code so that it can use
> the standard operand methods for generating register names?
The updated patch was resent after comments from Ramana and Paul which
eliminates this table.
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01009.html
I will take care of other formatting issues and will resend the patch.
>
> In summary, this is mostly OK, apart from the last two items.
>
> R.
- Thanks and regards,
Sameera D.
On Thu, 2011-11-10 at 13:44 +, Richard Earnshaw wrote:
> On 28/09/11 17:15, Sameera Deshpande wrote:
> > Hi!
> >
> > This patch generates Thumb2 epilogues in RTL form.
> >
> > The work involves defining new functions, predicates and patterns along with
The patch is tested with arm-eabi with no regressions.
ChangeLog:
2011-09-28 Ian Bolton
Sameera Deshpande
* config/arm/arm-protos.h (load_multiple_operation_p): New
declaration.
(thumb2_expand_epilogue): Likewise.
(thumb2_output_return
Ping!
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01854.html
On Wed, 2011-09-28 at 17:15 +0100, Sameera Deshpande wrote:
> Hi!
>
> This patch generates Thumb2 epilogues in RTL form.
>
> The work involves defining new functions, predicates and patterns along with
> few change
Ping!
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01855.html
On Wed, 2011-09-28 at 17:15 +0100, Sameera Deshpande wrote:
> Hi!
>
> This patch generates ARM epilogue in RTL form.
>
> The work defines new functions and reuses most of the static functions and
> patterns defin
This series of 5 patches generate LDRD/STRD instead of POP/PUSH in
epilogue/prologue for ARM and Thumb-2 mode of A15.
Patch [1/5] introduces new field in tune which can be used to indicate
whether LDRD/STRD are preferred over POP/PUSH by the specific core.
Patches [2-5/5] use this field to determ
cortex-a15:
2011-10-11 Sameera Deshpande
* config/arm/arm-cores.def (cortex_a15): Update.
* config/arm/arm-protos.h (struct tune_params): Add new field...
(arm_gen_ldrd_strd): ... this.
* config/arm/arm.c
thumb2 epilogue in A15:
2011-10-11 Sameera Deshpande
* config/arm/arm-protos.h (bad_reg_pair_for_thumb_ldrd_strd):
New
declaration
.
Changelog entries for the patch for STRD generation for a15-thumb2:
2011-10-11 Sameera Deshpande
* config/arm/arm.c (thumb2_emit_strd_push): New
PUSHed.
The patch is tested with check-gcc, check-gdb and bootstrap with no
regression.
Changelog entry for Patch to emit STRD for ARM prologue in A15:
2011-10-11 Sameera Deshpande
emit LDRD for ARM epilogue in A15:
2011-10-11 Sameera Deshpande
* config/arm/arm.c (arm_emit_ldrd_pop): New static function.
(arm_expand_epilogue): Update
h this fix.
gcc/ChangeLog entry:
2011-11-17 Sameera Deshpande
* config/arm/arm.md (arm_movdi): Update NEG_POOL_RANGE.
(movdf_soft_insn): Likewise.
* config/arm/fpa.md (thumb2_movdf_fpa): Likewise.
* config/arm/neon.md (neon_mov): Likewise.
* config/arm/vfp.md
On Fri, 2011-11-18 at 21:45 +, Ramana Radhakrishnan wrote:
> On 5 October 2011 17:04, Sameera Deshpande wrote:
> > Ping!
> >
> > http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01855.html
>
>
> This should now be rebased given your other changes to the Thumb2
&
On Tue, 2011-11-22 at 01:55 +, Xinyu Qi wrote:
> At 2011-11-19 07:11:17,"Ramana Radhakrishnan"
> wrote:
> > On 10 November 2011 18:07, Sameera Deshpande
> > wrote:
> > > Please find attached the reworked patch.
> >
> > OK but for a very s
On Fri, 2011-11-18 at 23:12 +, Ramana Radhakrishnan wrote:
> On 17 November 2011 15:16, Sameera Deshpande
> wrote:
> > Hi!
> >
> > Please find attached the patch updating NEG_POOL_RANGE from 1008 to
> > 1020 -(8 + ).
>
> This is OK - can you add a comment
guards dereferences
of 'fn' in dump_gimple_call ().
Tests in gcc-dg/vect failing with 'segmentation fault', pass with this
patch.
gcc/Changelog entry:
2011-11-24 Sameera Deshpande
* gimple-pretty-print.c (dump_gimple_call): Check if fn is NULL
before dereferenci
...@google.com
+Sameera Deshpandesameera.deshpa...@arm.com
Fran�ois Dumont fdum...@gcc.gnu.org
Benoit Dupont de Dinechin benoit.dupont-de-dinec...@st.com
Michael Eager ea...@eagercon.com
On Tue, 2011-11-22 at 10:37 +, Ramana Radhakrishnan wrote:
> Xinyu: I seem to have mis-remembered that one of your patches was
> turning on Thumb2 for wMMX.
> >
> > Ramana, in that case, should I add the change you suggested in ARM RTL
> > epilogue patch only?
>
> The comment in Thumb2 epilog
On Wed, 2011-11-30 at 19:43 +, Jason Merrill wrote:
> On 11/24/2011 05:42 AM, Sameera Deshpande wrote:
> > - if (TREE_CODE (fn) == ADDR_EXPR)
> > + if (fn != NULL && TREE_CODE (fn) == ADDR_EXPR)
> > fn = TREE_OPERAND (fn, 0);
> > -
Hi!
Please find attached revised LDRD generation patch for A15 Thumb-2 mode.
Because of the major rework in ARM and Thumb-2 RTL epilogue patches,
this patch has undergone some changes.
The patch is tested with check-gcc, bootstrap and check-gdb without
regression.
Ok for trunk?
-- diff --git a
Hi Ramana,
Please find attached revised LDRD generation patch for A15 ARM mode.
Because of the major rework in ARM RTL epilogue patch, this patch has
undergone some changes.
The patch is tested with check-gcc, bootstrap and check-gdb without
regression.
Ok for trunk?
-- diff --git a/gcc/config
Hi,
Please find attached the patch fixing bug 49069.
This patch is tested with check-gcc on trunk and 4.6 without regression.
OK for trunk?
Is it fine to backport to 4.6 branch?
ChangeLog:
2012-01-24 Sameera Deshpande
PR target/49069
gcc/config/arm/arm.md (cstoredi4): Handle
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