"vect" {
target vect_strided5 && vect_load_lanes } } } */
Could you verify it whether it work for you ?
Thanks.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-10-06 22:29
To: Juzhe-Zhong; gcc-patches@gcc.gnu.org
CC: rguent...@suse.de; jeffreya...@gmail.com; richard.sandif...@arm.com
OK.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-10-07 11:18
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Fix scan-assembler-times of RVV test case
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Adjust
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-07 14:25
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add more run test for FP rounding autovec
From: Pan Li
For _Float16 types, add run test for:
* ceil
* floor
* nearbyint
* rint
These testcases cause multiple FAILs:
I think you should
/* { dg-do run { target { riscv_v && riscv_zvfh_hw && riscv_zfh_ok } } } */
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-07 14:25
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH
Also I have reverted your commit:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=066a43ce72ab6559ba14af9628df19daa0b85cdf
Plz test the patch and verify it doesn't cause any FAILs if the toolchain
doesn't have "zvfh_zfh".
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Da
Hi, Jeff.
Address your comments and fix on V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632239.html
I think it look reasonable good for a long term maintenance now.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-10-07 23:09
To: Juzhe-Zhong; gcc-patches
CC
Hi, Richi and Robin.
Turns out COND(_LEN)?_ADD can't work.
Is this patch Ok ? Or do you have another solution to change the dump check for
RVV?
Thanks.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-08 09:33
To: gcc-patches
CC: rguenther; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Su
Yes. We do have && enable char -> long conversion (vsext.vf8/vzext.vf8)
Thanks for the comment, I will adapt test as you suggested.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 15:31
To: Jeff Law
CC: Juzhe-Zhong; gcc-patches; richard.sandiford
Subject: Re: [PATCH
o-strict-align) is not appropriate, which means I
need additional compile option.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 16:01
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Support movmisalign of RVV VLA
Thanks Richi.
I will try to figure out a better way to adapt the tests without adding riscv*
specific targets variant.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 16:17
To: Juzhe-Zhong
CC: gcc-patches; jeffreyalaw
Subject: Re: [PATCH] TEST: Fix XPASS of outer loop
,
OPTAB_DIRECT);
For srl, you should use:
rtx tmp
= expand_binop (Pmode, lshiftrt_optab, op_1,
gen_int_mode (8, Pmode), NULL_RTX, 0,
OPTAB_DIRECT);
For or, you should use:
expand_binop (Pmode, ior_optab, tmp, dest, NULL_RTX, 0,
OPTAB_DIRECT);
juzhe.zh...@rivai.ai
Thanks Robin. Could you send V3 to Richi ? And commit it if Richi is ok with
that.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-09 18:26
To: Andreas Schwab; juzhe.zhong
CC: rdapp.gcc; gcc-patches; rguenther; jeffreyalaw
Subject: Re: [PATCH V2] TEST: Fix vect_cond_arith_* dump checks
eneficial we support high stride lane load/store
which can help us vectorize more cases.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 20:41
To: Juzhe-Zhong
CC: gcc-patches; jeffreyalaw
Subject: Re: [PATCH] RISC-V Regression test: Fix FAIL of fast-math-slp-38.c for
RVV
On Mon, 9
LGTM now.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-09 21:09
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Refine bswap16 auto vectorization code gen
From: Pan Li
Update in v2
* Remove emit helper functions.
* Take
(Mostly just using different approach to vectorize it (cause dump FAIL) because
of some changing I have done previously in the middle-end).
So enabling "vec_pack" for RVV will fix some FAILs but increase some other
FAILs.
CC to Richi to see more reasonable suggestions.
juzhe.zh...@rivai.a
Great ! I am gonna wait for Richi's approval.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-10-10 17:40
To: Juzhe-Zhong; gcc-patches@gcc.gnu.org
CC: rguent...@suse.de; jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV
On 10/10/2023
LGTM on my side.
IMHO, we need to support attribute (rvv_vector_bits) which depend on this
patch, am I right?
If yes, will you support this feature in GCC-14 release?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-10-10 12:13
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp
It's weird. Could you give me the FAILs report?
juzhe.zh...@rivai.ai
From: Maciej W. Rozycki
Date: 2023-10-10 18:18
To: 钟居哲
CC: gcc-patches; Jeff Law; rdapp.gcc; kito.cheng
Subject: Re: 回复: [PATCH] RISC-V/testsuite: Enable `vect_pack_trunc'
On Mon, 9 Oct 2023, Maciej W. Roz
Thanks. Committed.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-11 14:54
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Enable full coverage vect tests
Hi Juzhe,
seems OK to me. We don't support most of the pat
ou think we don't need to add check_effective_target_riscv_v
every time.
So, feel free to adjust it (remove check_effective_target_riscv_v) and send a
patch.
But I hope you can adjust each set of tests carefully to make every thing
consistent.
Thanks.
juzhe.zh...@rivai.ai
From: Maci
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-11 16:49
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP lrint/lrintf auto vectorization
From: Pan Li
This patch would like to support the FP lrint/lrintf auto vectorization
Refine the codes in V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632619.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-11 17:03
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix incorrect index(offset) of
Oh. Yes.
Address comment:
V3: https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632623.html
Use if (inner_offsize < BITS_PER_WORD)
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-11 17:50
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject:
uild-gcc-newlib-stage1/gcc'
make[1]: *** [Makefile:4648: all-gcc] Error 2
make[1]: Leaving directory
'/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh-lp64d-medany-newlib-spike-debug/build-gcc-newlib-stage1'
make: *** [Makefile:590: stamps/build-gcc-newlib-stage1] Error 2
juzhe.zh...@rivai.ai
Plz revert it. It blocks development of all targets.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2023-10-12 09:03
To: juzhe.zh...@rivai.ai
CC: gcc-patches; jeffreyalaw; Kito.cheng; kito.cheng; Robin Dapp
Subject: Re: RISC-V: Support CORE-V XCVMAC and XCVALU extensions
On Wed, Oct 11, 2023
LGTM。 Thanks。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-12 09:52
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP irintf auto vectorization
From: Pan Li
This patch would like to support the FP irintf auto vectorization
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-12 11:28
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP llrint auto vectorization
From: Pan Li
This patch would like to support the FP llrint auto vectorization.
* long long
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-12 16:59
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP lround/lroundf auto vectorization
From: Pan Li
This patch would like to support the FP lround/lroundf auto vectorization
n SLP failed:
Build SLP failed: invalid type of def
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-12 17:44
To: 钟居哲
CC: gcc-patches; richard.sandiford
Subject: Re: Re: [PATCH] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721]
On Thu, 12 Oct 2023, ??? wrote:
> Thanks Richi point
ly. */
gcc_assert ((STMT_VINFO_TYPE (SLP_TREE_REPRESENTATIVE (node))
> assert FAILed.
== shift_vec_info_type)
&& j == 1);
continue;
}
Could you help me with that?
juzhe.zh...@rivai.ai
From: Richa
o->ops);
SLP_TREE_DEF_TYPE (invnode) = oprnd_info->first_dt;
oprnd_info->ops = vNULL;
children.safe_push (invnode);
continue;
}
It seems that we handle vect_constant_def same as vect_external_def.
So failed to SLP ?
juzhe.zh...@rivai.ai
t; ?
But I don't know how to adjust that.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-12 17:55
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford
Subject: Re: Re: [PATCH] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721]
On Thu, 12 Oct 2023, juzhe.zh.
The mask node is NULL since the caller :
if (mask_index >= 0
&& !vect_check_scalar_mask (vinfo, stmt_info, slp_node, mask_index,
&mask, NULL, &mask_dt, &mask_vectype))
return false;
pass NULL to mask_node.
OK.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 09:38
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP lfloor/lfloorf auto vectorization
From: Pan Li
This patch would like to support the FP lfloor/lfloorf auto vectorization
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 10:22
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Leverage stdint-gcc.h for RVV test cases
From: Pan Li
Leverage stdint-gcc.h for the int64_t types instead of typedef.
Or we may
Hi, Richi.
As you suggest, I keep MAK_LEN_GATHER_LOAD (...,-1) format and support SLP for
that in V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632846.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-12 19:14
To: juzhe.zh...@rivai.ai
CC: gcc-patches
Thanks. Committed.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-10-13 14:01
To: Juzhe-Zhong
CC: GCC Patches; Jeff Law; Richard Biener
Subject: Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
LGTM
Juzhe-Zhong 於 2023年10月12日 週四 22:45 寫道：
Like ARM SVE and GCN, add RVV
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 14:15
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP llround auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 15:20
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP llceil auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
Ok
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 16:06
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP iceil auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 16:23
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP ifloor auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 17:49
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test for FP llfloor auto vectorization
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as
Thanks Robin.
Committed.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-16 17:12
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Use VLS modes if the NITERS is known and smaller
than VLS mode elements.
Hi Juzhe,
this LGTM
V2: https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633120.html
with some bug fix.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-16 11:57
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix unexpected big LMUL choosing in
ich simplify
COND_LEN_ADD (mask, a, 0, b, len, bias) into LEN_VCOND_MASK (mask, a, b, len,
bias)
I think upstream GCC could consider this approach.
Thanks.
juzhe.zh...@rivai.ai
);
+ gcc_assert (match_p);
+ }
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633209.html
Assert we always match mask_vectype.
Tested on RISC-V and bootstrap && regtest on X86 passed.
Could you confirm it ?
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-10-
OK
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 17:57
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Fix failed testcase when use -cmodel=medany
This little path fix a failed testcase when use -cmodel=medany.
gcc
Committed.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-17 15:30
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Enable more tests for dynamic LMUL and bug
fix[PR111832]
Last time, Robin has mentioned that dynamic LMUL will
delete_list;
All of them add "m_" prefix.
earliest_fusion_worthwhile_p -> successors_probability_equal_p
calculate_dominance_info (CDI_POST_DOMINATORS); > remove
free_dominance_info (CDI_POST_DOMINATORS); ---> remove
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-
LGMT this patch.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
This sub-patch remove the method about
() const
+ {
+gcc_assert (!empty_p ());
+return infos.is_empty () ? m_info : infos[infos.length () - 1];
+ }
Change it into get_exit_info (be consistent with mode-switching naming which
also uses LCM).
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; ki
LGTM on algorithm of local analysis.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 05/14] RISC-V: P5: combine phase 1 and 2
This sub-patch combine phase 1 and 2 to use the
compute_vsetvl_lcm_data -> compute_lcm_local_properties
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 06/14] RISC-V: P6: Add computing reaching definition data
f
and the output is not used between the start of
- the block and the occurrence. */
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 06/14] RISC-V: P6: Add computing
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 07/14] RISC-V: P7: Move earliest fuse and lcm code to
pre_vsetvl class
This patch adjust move the code phase 2 and 3
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 08/14] RISC-V: P8: Unified insert and delete of vsetvl insn
into Phase 4
This sub-patch move the modification of rtl
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 09/14] RISC-V: P9: Cleanup post optimize phase
This sub-patch deletes partial post optimize code(which implement
in the
OK
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 12/14] RISC-V: P12: Delete riscv-vsetvl.h
This sub-patch delete the unused header file riscv-vsetvl.h
since we no need
OK
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 13/14] RISC-V: P13: Reorganize functions used to modify RTL
This sub-patch reoriganize the functions that used to modify
OK
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 14/14] RISC-V: P14: Adjust and add testcases
This sub-patch adjust some testcases and add some bugfix
testcases.
PR
Forget about this patch.
Commit log code example is wrong, fixed it in V2：
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633420.html
Thanks.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-18 18:21
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe
10e20: 02d606d7vadd.vv v13,v13,v12
10e24: fdc5bneza1,10ddc
The vncvt.x.x.w consume e16m1 VTYPE vsetvl but it shouldn't, it should be e8mf2.
This issue is fixed by recent refactor patch.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date:
LGTM popcount patch.
juzhe.zh...@rivai.ai
ocation,
+"incompatible vector types for invariants\n");
+ return false;
+ }
Bootstrap and Regression on x86 passed.
Thanks.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-18 20:36
To: gcc-patches
CC: richard.sandiford; rg
Ping。Ok for trunk？
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-26 19:35
To: gcc-patches
CC: kito.cheng; palmer; rdapp.gcc; jeffreyalaw; kito.cheng; pan2.li; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
From: Juzhe-Zhong
This patch support FMA auto
This is existing bug in GCC 13. I think I should split into 2 patches.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-29 11:17
To: juzhe.zhong
CC: gcc-patches; kito.cheng; palmer; rdapp.gcc; jeffreyalaw; pan2.li
Subject: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
LGTM
This patch is fixing VSETVL PASS bug. Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-26 11:01
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; pan2.li;
Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
Yes.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-29 12:36
To: juzhe.zh...@rivai.ai
CC: Kito.cheng; Robin Dapp; gcc-patches; jeffreyalaw; palmer; palmer; pan2.li
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
Ok, and just make sure this only appear for trunk
Hi, this patch is same implementation as FMA which has been merged.
Ok for trunk?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-29 14:53
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add RVV FNMA auto
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-29 12:35
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV
auto-vectorization support
From: Juzhe-Zhong
Nx4x2SF,VNx5x2SF,VNx6x2SF,VNx7x2SF,VNx8x2SF,\
VNx2x1SF,VNx3x1SF,VNx4x1SF,VNx5x1SF,VNx6x1SF,VNx7x1SF,VNx8x1SF")
(const_int 32)
(eq_attr "mode" "VNx1DI,VNx2DI,VNx4DI,VNx8DI,VNx16DI,\
VNx1DF,VNx2DF,VNx4DF,VNx8DF,VNx16DF,\
VNx2x8DI,VNx2x4DI,VNx3x4DI,VNx4x4DI,\
Ok. LGTM as long as you change the patch as I suggested.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-30 14:51
To: juzhe.zh...@rivai.ai
CC: gcc-patches; palmer; kito.cheng; jeffreyalaw; Robin Dapp; pan2.li
Subject: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V
Hi, this patch is bootstrapped PASS.
Ok for trunk ?
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-25 23:26
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH] VECT: Add SELECT_VL support
From: Ju-Zhe Zhong
This patch is adding SELECT_VL middle
on CPU with vector length=128. However, LLVM can
run on any RVV CPU with vector length >= 128.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-30 15:27
To: Kito Cheng; gcc-patches; palmer; kito.cheng; juzhe.zhong; jeffreyalaw;
pan2.li
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: B
th RVV vector-length >= 128 bits.
This is what this patch want to do.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 15:13
To: Kito Cheng
CC: gcc-patches; palmer; kito.cheng; juzhe.zhong; jeffreyalaw; rdapp.gcc;
pan2.li
Subject: Re: [PATCH] RISC-V: Basic VLS code gen
SELECT_VL patch).
>> In general I don't have a good overview of which optimizations we gain by
>> such an approach or rather which ones are prevented by VLA altogether?
These patches VLS modes can help for SLP auto-vectorization.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 20
nfo
+LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo) = true;
I should add direct_supportted_p (SELECT_VL...) to this is that right?
I have send SELECT_VL patch. I will add this in next SELECT_VL patch.
Let's wait Richard's more comments.
Thanks.
juzhe.zh...@rivai.ai
From: Richard
ew RVV patterns with new VLS modes
(The patterns are same as VLA patterns, just modes are different).
Then emit codegen this VLS RVV patterns.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 17:29
To: juzhe.zh...@rivai.ai
CC: Robin Dapp; Kito.cheng; gcc-patches; palmer; kito.cheng; j
VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI
"TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128")
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI
"TARGET_MIN_VLEN > 32") (VNx32SI "TA
not familiar with SCEV and I am not sure how to do that SCEV can
analysis the decrement IV.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 17:50
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; linkw
Subject: Re: Re: decremnt IV patch create fails on PowerPC
O
ve a try and send a patch.
Thank you so much.
By the way, could you take a look at SELECT_VL patch?
I guess you want to defer it to Richard and I will wait but still I think your
comment is very important.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 18:00
To: Kewen.Lin
CC:
he.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-30 17:50
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; linkw
Subject: Re: Re: decremnt IV patch create fails on PowerPC
On Tue, 30 May 2023, juzhe.zh...@rivai.ai wrote:
> Ok.
>
> It seems that for this conditions:
>
as this flow is better to power (SCEV）。
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-30 19:31
To: juzhe.zhong
CC: gcc-patches; rguenther; linkw
Subject: Re: [PATCH] VECT: Change flow of decrement IV
juzhe.zh...@rivai.ai writes:
> From: Ju-Zhe Zhong
>
> Follow Rich
by SELET_VL).
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-30 19:31
To: juzhe.zhong
CC: gcc-patches; rguenther; linkw
Subject: Re: [PATCH] VECT: Change flow of decrement IV
juzhe.zh...@rivai.ai writes:
> From: Ju-Zhe Zhong
>
> Follow Richi's suggestion, I change
ter well reviewed) or
we should extend SCEV/IVOPTS ?
Thanks.
juzhe.zh...@rivai.ai
From: 钟居哲
Date: 2023-05-30 23:05
To: rguenther
CC: richard.sandiford; gcc-patches; linkw
Subject: Re: Re: [PATCH] VECT: Change flow of decrement IV
More information of power's testcase:
Before this patch:
t
a/show_bug.cgi?id=109971,
Kewen is happy with this patch, turns out this patch can fix power's issue.
So, Let's wait for Richard's comments.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-31 14:41
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; gcc-patches; linkw
Su
ich PASS ? "ivopts" PASS?
Is that right that we can enhance analysis when we see the statement as follows:
remain = remain - step and step is coming from a MIN_EXPR (remain, vf).
Then what we need to do?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-31 15:28
To: Ri
we can make this patch merged and record the enhancement of SCEV in
bugzilla to see we can improve that in the future.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-31 15:38
To: Richard Sandiford
CC: juzhe.zh...@rivai.ai; gcc-patches; linkw
Subject: Re: [PATCH] VECT: Change
Oh, it's correct fix. Thanks for catching this.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-05-31 15:38
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; gcc-patches; rguenther
Subject: Re: [PATCH] VECT: Change flow of decrement IV
> Hi, Richi.
>
>>> Note with SELECT
Thanks Richard.
Seems that this patch's approach is ok to trunk?
Maybe the only thing we should do is to wait Kewen's testing feedback, am I
right ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-31 17:01
To: Richard Biener via Gcc-patches
CC: Richard Biener; j
Bootstrapped and Regression on X86 no surprise different.
Looking forward Kewen's test report for this patch.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-31 23:08
To: gcc-patches
CC: richard.sandiford; rguenther; linkw; Ju-Zhe Zhong
Subject: [PATCH V2] VECT: Change fl
Thanks kewen.
I have send V3 patch. Could you comment that ?
I want to make sure you do support that patch.
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-06-01 12:32
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; rguenther; gcc-patches
Subject: Re: [PATCH V2] VECT: Change flow of
This patch is no difference from V2.
Just add PR tree-optimization/109971 as Kewen's suggested.
Already bootstrapped and Regression on X86 no difference.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-01 12:36
To: gcc-patches
CC: richard.sandiford; rguenther; link
he.zh...@rivai.ai
From: Li, Pan2
Date: 2023-06-01 14:57
To: juzhe.zh...@rivai.ai
Subject: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16
in riscv like x86_64 and arm.
FYI.
-Original Message-
From: Gcc-patches On Behalf
Of Jin Ma via Gcc-patches
Sent: Thursday, J
LGTM.
We are waiting for FP16 vector to start floating-point auto-vectorizations
Thanks so much.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-01 15:17
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH] RISC-V: Introduce vfloat16m{f}*_t and their machine
Thanks Kewen. Let's wait for Richard and Richi.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-06-01 13:24
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; rguenther; gcc-patches
Subject: Re: [PATCH V3] VECT: Change flow of decrement IV
Hi,
on 2023/6/1 13:00, juzhe.zh...@rivai.ai
Hi， forget about this patch.
Just go directly the V2 patch with same title.
That's the last patch I fine tune for integer widening auto-vectorization.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-01 15:31
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffre
Oh. Yes. Thanks for catching this!
Will send V2 soon.
juzhe.zh...@rivai.ai
From: KuanLin Chen
Date: 2023-06-02 09:26
To: gcc-patches; juzhe.zhong
CC: kito.cheng; palmer; rdapp.gcc; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add _mu C++ overloaded intrinsics for load &&
viota &&a
egister pressures.
So, for such combining, I would like take a another approach to combine this
pattern carefully with accurate register pressure calculation.
However, for this patch.
vext.vf2 + vext.vf2 + vadd ==> vwadd.vv is always better.
I don't think it is possible that using vwadd.
Thanks. I am gonna wait for Jeff or Kito final approve.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-02 15:18
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Add pseudo vwmul.wv pattern to enhance
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