Re: [PATCH] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

> > > > The sequence '0x92,0xa2,0x38,0' means the vlenb register, '0x34' means > > the literal 4, '0x1e' means the multiply operation. But in fact, the > > vlenb register value just need to multiply the literal 2. > > > > gcc/ChangeLog: &

Re: [PATCH] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

rminate_value): gcc/testsuite/ChangeLog:         * gcc.target/riscv/rvv/base/scalable_vector_cfi.c: New test. Signed-off-by: Zhijin Zeng ---  gcc/config/riscv/riscv.cc                     |  4 +--  .../riscv/rvv/base/scalable_vector_cfi.c      | 32 +++  2 files changed, 34 insertions(+

Re: [PATCH] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

iteral 4, '0x1e' means the multiply operation. But in fact, the vlenb register value just need to multiply the literal 2. gcc/ChangeLog:         * config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): gcc/testsuite/ChangeLog:         * gcc.target/riscv/rvv/base/scalable_vector

Re: [PATCH] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

This is my first time submitting a patch to gcc and sincerely thank you all for your help. Zhijin > From: "Li, Pan2" > Date:  Sat, Aug 17, 2024, 12:15 > Subject:  RE: [PATCH] RISC-V: Fix factor in dwarf_poly_indeterminate_value > [PR116305] > To: "Li, Pan2"

[RFC][PATCH] RISC-V: Support TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN

I can't find the vector function name mangling of risc-v, so in order to support TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN, TARGET_SIMD_CLONE_ADJUST and TARGET_SIMD_CLONE_USABLE, I add risc-v vector function mangling rules as follow:     _ZGVNv_     'x' is the LMUL, if the LMUL is 1/2/4/

Re: [RFC][PATCH] RISC-V: Support TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN

I create a pr in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/455, maybe we can discuss it there. Zhijin, Thanks. > From: "Kito Cheng" > Date:  Tue, Nov 26, 2024, 23:41 > Subject:  Re: [RFC][PATCH] RISC-V: Support > TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMD

Re: [PATCH v2] RISC-V: Fix riscv_modes_tieable_p

I'm so sorry that I didn't describe the patch clearly. I refactored the patch and added some new  changes. Initially I split them into two patches, which is probably not right. Thanks, Zhijin >From ca072f040c876df4117f475eeb74c7eb8882bed8 Mon Sep 17 00:00:00 2001 From: Zhijin Ze

Re: [PATCH v3] RISC-V: Fix riscv_modes_tieable_p

Compared to the patch v2, I added Zfinx check and Zfh check. Please help to review again. Thanks, Zhijin >From 9ddb402cebe868050ebc2f75e4d87238161411b4 Mon Sep 17 00:00:00 2001 From: Zhijin Zeng Date: Sat, 11 Jan 2025 12:09:11 +0800 Subject: [PATCH] RISC-V: Fix mode compatibility betw

[PATCH] RISC-V: Fix riscv_modes_tieable_p

Integer values and floating-point values need to be converted by fmv series instructions. So if mode1 is MODE_INT and mode2 is MODE_FLOAT, we should return false in riscv_modes_tieable_p, and vice versa. gcc/ChangeLog:         * config/riscv/riscv.cc (riscv_modes_tieable_p): gcc/testsuite/Change

Re: [PATCH v2] RISC-V: Do not lift up vsetvl into non-transparent blocks [PR119547].

LGTM. Thank you. Zhijin Zeng. > From: "Robin Dapp" > Date:  Wed, Apr 9, 2025, 20:09 > Subject:  [PATCH v2] RISC-V: Do not lift up vsetvl into non-transparent > blocks [PR119547]. > To: "gcc-patches" > Cc: , , , > , , , > , "Vineet Gupta"