On 05/11/15 14:57, Jiong Wang wrote:
Marcus Shawcroft writes:
+#ifdef HAVE_AS_TINY_TLSGD_RELOCS
+ return SYMBOL_TINY_TLSGD;
+#else
+ return SYMBOL_SMALL_TLSGD;
+#endif
Rather than introduce blocks of conditional compilation it is better
to gate different behaviours with a test on a
11-23 Richard Biener
Jiong Wang
gcc/
PR tree-optimization/68137
PR tree-optimization/68326
* tree-vrp.c (adjust_range_with_scev): Call drop_tree_overflow if the
final min and max are not infinity.
gcc/testsuite/
* gcc.dg/pr68139.c: New testcase.
--
Regards,
Jiong
diff --
On 24/11/15 10:18, Richard Earnshaw wrote:
I presume you are aware of the canonicalization rules for add? That is,
for a shift-and-add operation, the shift operand must appear first. Ie.
(plus (shift (op, op)), op)
not
(plus (op, (shift (op, op))
R.
Looks to me it's not optimal to gener
On 24/11/15 13:23, Richard Earnshaw wrote:
On 24/11/15 13:06, Jiong Wang wrote:
On 24/11/15 10:18, Richard Earnshaw wrote:
I presume you are aware of the canonicalization rules for add? That is,
for a shift-and-add operation, the shift operand must appear first. Ie.
(plus (shift (op, op
On 13/11/15 15:21, Jiong Wang wrote:
On 05/11/15 14:57, Jiong Wang wrote:
Marcus Shawcroft writes:
+#ifdef HAVE_AS_TINY_TLSGD_RELOCS
+ return SYMBOL_TINY_TLSGD;
+#else
+ return SYMBOL_SMALL_TLSGD;
+#endif
Rather than introduce blocks of conditional compilation it is better
to gate
The same skip should be applied to big-endian for tiny and large code model.
Applied to trunk as obvious r231413.
2015-12-08 Jiong Wang
gcc/testsuite/
* gcc.target/aarch64/got_mem_hoist_1.c (dg-skip-if): Match big-endian as well.
diff --git a/gcc/testsuite/gcc.target/aarch64
ret
Added new tests. Built and regression tested on aarch64-none-elf.
Best Regards,
Yuliang Wang
gcc/ChangeLog:
2019-09-23 Yuliang Wang
* config/aarch64/aarch64-sve.md (asrd3): New pattern for ASRD.
* config/aarch64/iterators.md (UNSPEC_ASRD): New unspec.
(ASRDIV)
add z0.s, z0.s, z1.s
...
after ssraz0.s, z1.s, #{IMM}
Unsigned:
beforelsr z0.s, z0.s, #{IMM}
add z0.s, z0.s, z1.s
...
after usraz0.s, z1.s, #{IMM}
Built and regression tested on aarch64-none-elf.
Best Regards,
Yuliang Wang
Hi Richard,
I have renamed the optabs and associated identifiers as per your suggestion.
Thanks.
Regards
Yuliang
gcc/ChangeLog:
2019-09-27 Yuliang Wang
* config/aarch64/aarch64-sve.md (sdiv_pow23):
New pattern for ASRD.
* config/aarch64/iterators.md (UNSPEC_ASRD
Apologies for the accidental change, and added the underscore.
Regards
Yuliang
gcc/ChangeLog:
2019-09-27 Yuliang Wang
* config/aarch64/aarch64-sve.md (sdiv_pow23):
New pattern for ASRD.
* config/aarch64/iterators.md (UNSPEC_ASRD): New unspec.
* internal
Thanks for the corrections, updated.
Regards
Yuliang
(no ChangeLog updates)
-Original Message-
From: Richard Sandiford
Sent: 27 September 2019 11:20
To: Yuliang Wang
Cc: gcc-patches@gcc.gnu.org; nd
Subject: Re: [AArch64][SVE] Utilize ASRD instruction for division and remainder
Hi,
The new test added as part of r276174 fails on an ilp32 target, which this
patch fixes. Thanks to Christophe Lyon for pointing this out.
Regression tested on aarch64-none-elf.
Best Regards,
Yuliang Wang
gcc/testsuite/ChangeLog:
2019-10-04 Yuliang Wang
* gcc.target/aarch64
Hi Christophe,
Thanks for pointing this out, uploaded a fix.
Regards,
Yuliang
From: Christophe Lyon
Sent: 04 October 2019 09:25
To: Richard Sandiford
Cc: Yuliang Wang ; gcc-patches@gcc.gnu.org; nd
Subject: Re: [AArch64][SVE2] Shift-Right Accumulate combine patterns
On Fri, 27 Sep 2019 at
y -> NBSL x, y, x
NAND x, y -> NBSL x, y, y
Built and tested on aarch64-none-elf.
Best Regards,
Yuliang Wang
gcc/ChangeLog:
2019-10-16 Yuliang Wang
* config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3)
(aarch64_sve2_nor, aarch64_sve2_nand)
(aarch64_
Hi Richard,
Thanks for the suggestions, updated.
Regards,
Yuliang
gcc/ChangeLog:
2019-10-17 Yuliang Wang
* config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3)
(aarch64_sve2_nor, aarch64_sve2_nand)
(aarch64_sve2_bsl, aarch64_sve2_nbsl)
(aarch64_sve2_bsl1n
Thanks very much, updated.
Regards,
Yuliang
gcc/ChangeLog:
2019-10-17 Yuliang Wang
* config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3)
(aarch64_sve2_nor, aarch64_sve2_nand)
(aarch64_sve2_bsl, aarch64_sve2_nbsl)
(aarch64_sve2_bsl1n, aarch64_sve2_bsl2n
;
Built and tested on aarch64-none-elf.
Regards,
Yuliang Wang
gcc/ChangeLog:
2019-10-17 Yuliang Wang
* match.pd (/* (x & ~m) | (y & m) -> ... */): Modified fold pattern.
* genmatch.c (convert3): New convert operation to support the above.
gcc/
;
Built and tested on aarch64-none-elf.
Regards,
Yuliang Wang
gcc/ChangeLog:
2019-10-17 Yuliang Wang
* match.pd (/* (x & ~m) | (y & m) -> ... */): Modified fold pattern.
* genmatch.c (convert3): New convert operation to support the above.
gcc/
On 2022/11/16 10:10, Lulu Cheng wrote:
v2 -> v3:
1. Remove preldx support.
---
Enable sw prefetching at -O3 and higher.
Co-Authored-By: xujiahao
gcc/ChangeLog:
* config/loongarch/constraints.md (ZD): New constraint.
* config/loongarch/loo
On 2023-04-22 08:08 Jeff Law wrote:
>
>
>
>On 3/23/23 19:53, Feng Wang wrote:
>> This patch optimize the combine processing for sext.b/h in rv64.
>> Please refer to the following test case,
>> int sextb32(int x)
>> { return (x << 24) >> 24; }
>&g
On 2023/4/26 17:53, Lulu Cheng wrote:
Hi, ruoyao:
The performance of spec2006 is finished. The fixed-point
400.perlbench has about 3% performance improvement,
and the other basics have not changed, and the floating-point tests
have basically remained the same.
Nice to know!
On 2023/4/26 18:14, Lulu Cheng wrote:
在 2023/4/26 下午6:02, WANG Xuerui 写道:
On 2023/4/26 17:53, Lulu Cheng wrote:
Hi, ruoyao:
The performance of spec2006 is finished. The fixed-point
400.perlbench has about 3% performance improvement,
and the other basics have not changed, and the
From: wangfeng
There is no Immediate operand of ins "rol" accroding to the B-ext,
so the immediate operand should be loaded into register at first.
But we can convert it to the ins "rori" or "roriw", and then one
immediate load ins can be reduced.
Please refer to the following use cases:
unsigne
on 2022-11-28 23:39 Jeff Law wrote:
>
>
>On 11/27/22 19:14, Feng Wang wrote:
>> From: wangfeng
>>
>> There is no Immediate operand of ins "rol" accroding to the B-ext,
>> so the immediate operand should be loaded into register at first.
>> But we
The first patch is
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/607332.html.
Accroding to Jeff's suggestion I added some conditions when reverse the rotate
shift during RTL expansion and RTL optimization.
wangfeng (1):
RISC-V: Optimze the reverse conditions of rotate shift
gcc/conf
From: wangfeng
There is no Immediate operand of ins "rol" according to the B-ext,
so the immediate operand should be loaded into register at first.
But we can convert it to the ins "rori" or "roriw", and then one
immediate load ins can be reduced.
So I added some conditions when reverse the rotat
This patch optimize load one byte or halfword from memory in rv64.
Please refer to the following test case for loading one byte.
int sextb32_memory(int* x)
{ return (*x << 24) >> 24; }
The build flags are "-march=rv64g -mabi=lp64d -O2"
The current compilation results are as follows,
slliw a0,a0,0
This patch optimize the combine processing for sext.b/h in rv64.
Please refer to the following test case,
int sextb32(int x)
{ return (x << 24) >> 24; }
The rtl expression is as follows,
(insn 6 3 7 2 (set (reg:SI 138)
(ashift:SI (subreg/s/u:SI (reg/v:DI 136 [ xD.2271 ]) 0)
(co
Hi Juzhe,
Thank you for your reply, I'm really doing some optimization work right now.
I am very interested in the question you have raised, and I will take the time
to try to optimize it.
I hope I can communicate with you and learn from you more in the future.
Thanks.
HO) is to walk
>through the optimizer pipeline to see where it can potentially be
>eliminated. In general, the earlier in the optimizer pipeline the
>extension can be eliminated, the better.
>
>Jeff
Hi Jeff，Do you think my patch modification is suitable?What else needs to be
improved？
Thanks.
Feng Wang
Hi,
Just some minor fixes ;-)
On 2023/4/18 14:15, Lulu Cheng wrote:
---
htdocs/gcc-13/changes.html | 39 ++
1 file changed, 39 insertions(+)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index f3b9afed..c75e341b 100644
--- a/htdocs/
Hi,
Thanks for helping confirming on GCC and porting this! I'd never know
even GCC lacked this adaptation without someone actually checking... Too
many things are taken for granted these days.
On 2023/4/18 20:17, Xi Ruoyao wrote:
According to Xuerui's LLVM changeset [1], doing so can make a
On 2023/4/18 20:45, Xi Ruoyao wrote:
On Tue, 2023-04-18 at 20:39 +0800, WANG Xuerui wrote:
Hi,
Thanks for helping confirming on GCC and porting this! I'd never know
even GCC lacked this adaptation without someone actually checking... Too
many things are taken for granted these days.
On
On 15/06/17 15:12, Wilco Dijkstra wrote:
This results in smaller code and unwind info.
I have done a quick test on your updated patch through building latest linux
kernel.
Dwarf frame size improved (~ 5% smaller) as using sp to address locals doesn't
need to update CFA register etc.
Though th
will never be called.
This patch just move the else condition in make_decl_rtl to make all register
type declaration to get the
same rtx, it this a reasonable fix?
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On
> Behalf Of T
.md (neon_copysignf): New pattern for vector copysignf.
gcc/testsuite/
* gcc.target/arm/vect-copysignf.c: New testcase.
commit 533b209f1899a1070394506ab32cc640de6a58e3
Author: Jiong Wang
Date: Thu Aug 14 11:54:41 2014 +0100
vect copysignf.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/ar
Ping? Still on the trunk now.
> -Original Message-
> From: Tony Wang [mailto:tony.w...@arm.com]
> Sent: Tuesday, August 12, 2014 9:32 AM
> To: gcc-patches@gcc.gnu.org
> Subject: [PING v2][Patch]Fix ICE for gcc.dg/noncompile/920507-1.c
>
> Ping 2, and pasted my obser
for *a function with frame size >= 512 and there is outgoing area*,
aarch64 gcc is generate wrong .cfi_def_cfa_offset for the last
stack adjustment instruction in epiloue.
given a simple testcase
test.c
===
int
main (int argc, char **argv)
{
char a[600];
int b = 0x10;
printf ("%d, %d, %d,
st follow their pattern to avoid the test case on
target using wrapper.
gcc/gcc/testsuite/ChangeLog:
2014-08-20 Tony Wang
* g++.dg/tls/thread_local6.C: Skip this test case when
target uses dejagnu wrapper.
diff --git a/gcc/testsuite/g++.dg/tls/thread_local6.C
b/gcc/tests
rol whether to split the
section of a function pair into two
part.
gcc/libgcc/ChangeLog:
2014-08-21 Tony Wang
* config/arm/lib1funcs.S (FUNC_START): Add conditional section
redefine for macro L_arm_muldivsf3 and L_arm_muldivdf3
(SYM_END, ARM_SYM_START): Add macros use
-8-21 Tony Wang
* config/arm/ieee754-sf.S: Expose symbols around fragment boundaries as
function symbols.
* config/arm/ieee754-df.S: Same with above
BR,
Tony
libgcc_mul_div_code_size_reduction_2.diff
Description: Binary data
Step 3: Test cases to verify the code size reduction.
gcc/gcc/testsuite/ChangeLog:
2014-08-21 Tony Wang
* gcc.target/arm/size-optimization-ieee-1.c: New test case
* gcc.target/arm/size-optimization-ieee-2.c: New test case
* lib/gcc-dg.exp: Add new function scan-symbol
++-v3/ChangeLog:
2014-08-21 Tony Wang
* testsuite/18_support/nested_exception/62154.cc: Disable
this test case when target don't have atomic buildins.
diff --git a/libstdc++-v3/testsuite/18_support/nested_exception/62154.cc
b/libstdc++-v3/testsuite/18_support/nested_exception/62
Hi Mike
> Hum, another solution might be to wrap _exit as well. The patch is so simple
> and short, I'll approve the
posted
> patch; it is a nice step forward. I'll let you contemplate if you want to
> try a wrap on _exit.
>
Thanks for your reply, and I also thought of your suggestion to wr
e fix?
gcc/libstdc++-v3/ChangeLog:
2014-8-25 Tony Wang
PR target/56846
* libsupc++/eh_personality.cc: Return with CONTINUE_UNWINDING
when meet with the unwind state pattern:
_US_VIRTUAL_UNWIND_FRAME |
_US_FORCE_UNWIND
On 22/08/14 23:05, Richard Henderson wrote:
Don't continually re-read data from cfun->machine.
* config/aarch64/aarch64.c (aarch64_expand_prologue): Load
cfun->machine->frame.hard_fp_offset into a local variable.
---
gcc/config/aarch64/aarch64.c | 14 +++---
1 file cha
thanks,
verified no regression on aarch64-none-elf bare-metal check-gcc/check-gdb.
-- Jiong
On 22/08/14 23:05, Richard Henderson wrote:
Delay cfi restore opcodes until the stack frame is deallocated.
This reduces the number of cfi advance opcodes required.
We perform a similar optimization in
Ping?
> -Original Message-
> From: Tony Wang [mailto:tony.w...@arm.com]
> Sent: Thursday, August 21, 2014 2:15 PM
> To: 'gcc-patches@gcc.gnu.org'
> Subject: [PATCH 1/3,ARM,libgcc]Code size optimization for the fmul/fdiv and
> dmul/ddiv function in libgcc
>
Ping?
> -Original Message-
> From: Tony Wang [mailto:tony.w...@arm.com]
> Sent: Thursday, August 21, 2014 2:15 PM
> To: 'gcc-patches@gcc.gnu.org'
> Subject: [PATCH 2/3,ARM,libgcc]Code size optimization for the fmul/fdiv and
> dmul/ddiv function in libgcc
>
Ping?
> -Original Message-
> From: Tony Wang [mailto:tony.w...@arm.com]
> Sent: Thursday, August 21, 2014 2:15 PM
> To: 'gcc-patches@gcc.gnu.org'
> Subject: [PATCH 3/3,ARM,libgcc]Code size optimization for the fmul/fdiv and
> dmul/ddiv function in libgcc
>
On 26/08/14 14:37, Jiong Wang wrote:
thanks,
verified no regression on aarch64-none-elf bare-metal check-gcc/check-gdb.
-- Jiong
On 22/08/14 23:05, Richard Henderson wrote:
Delay cfi restore opcodes until the stack frame is deallocated.
This reduces the number of cfi advance opcodes required
On 28/08/14 17:48, Richard Henderson wrote:
On 08/26/2014 05:58 AM, Jiong Wang wrote:
there is a field "hardfp_offset" in aarch64_frame, and I think that field is
not used and not initialized correctly.
how about hoisting the calculation to aarch64_layout_frame to avoid duplicated
On 03/09/14 11:33, Marcus Shawcroft wrote:
On 20 August 2014 09:43, Jiong Wang wrote:
gcc/
* config/aarch64/aarch64.c (aarch64_expand_epilogue): Remove redundant cfa
offset update.
OK
/Marcus
thanks for review.
this fix is included in Richard H's patch at
https://gcc.gnu.org/m
Ping?
> -Original Message-
> From: Tony Wang [mailto:tony.w...@arm.com]
> Sent: Monday, August 25, 2014 6:33 PM
> To: 'gcc-patches@gcc.gnu.org'; 'd...@debian.org';
> 'aph-...@littlepinkcloud.com'; Richard Earnshaw; Ramana
> Radhakrishnan
&g
Ping 2?
> -Original Message-
> From: Tony Wang [mailto:tony.w...@arm.com]
> Sent: Thursday, August 28, 2014 2:02 PM
> To: 'gcc-patches@gcc.gnu.org'
> Cc: Richard Earnshaw; Ramana Radhakrishnan
> Subject: RE: [PATCH 1/3,ARM,libgcc]Code size optimization for th
Ping 2?
> -Original Message-
> From: Tony Wang [mailto:tony.w...@arm.com]
> Sent: Thursday, August 28, 2014 2:02 PM
> To: 'gcc-patches@gcc.gnu.org'
> Cc: Richard Earnshaw; Ramana Radhakrishnan
> Subject: RE: [PATCH 2/3,ARM,libgcc]Code size optimization for th
Ping 2?
> -Original Message-
> From: Tony Wang [mailto:tony.w...@arm.com]
> Sent: Thursday, August 28, 2014 2:02 PM
> To: 'gcc-patches@gcc.gnu.org'
> Cc: Richard Earnshaw; Ramana Radhakrishnan
> Subject: RE: [PATCH 3/3,ARM,libgcc]Code size optimization for th
trunk?
gcc/gcc/testsuite/ChangeLog:
2014-09-04 Tony Wang
* gcc.target/arm/xordi3-opt.c: Disable this
test case for thumb1 target.
* gcc.target/arm/iordi3-opt.c: Ditto.
diff --git a/gcc/testsuite/gcc.target/arm/iordi3-opt.c
b/gcc/testsuite/gcc.target/arm/iordi3-opt.c
this patch enabled stack shrink-wrap support on AArch64.
no regression on aarch64-none-elf bare-metal.
aarch64 bootstrap OK.
ok to install?
2014-09-04 Renlin Li
gcc/
* config/aarch64/aarch64.md (return): New expand.
(simple_return): Likewise.
* config/aarch64/aarch64.c (aarch64_use_retur
check-gcc.
both aarch64 and x86-64 bootstrap OK.
ok for install?
2014-09-04 Jiong Wang
gcc/
* shrink-wrap.c (rtx_search_arg): New structure type.
(rtx_search_arg_p): New typedef.
(count_reg_const): New callback function.
(move_insn_for_shrink_wrap): Relax the restriction on src operand.
On 05/09/14 20:48, Jeff Law wrote:
On 09/04/14 08:15, Jiong Wang wrote:
this patch relax the restriction on src to accept any one of the following:
+ REG
+ CONST_OBJ, like SYMBOL_REF
+ combination of single REG and any other CONST_OBJs.
(reg def/use calculation will not
On 08/10/14 15:00, Maxim Ostapenko wrote:
Hm, as I see, others testsuites such as gfortran.exp, go.exp etc. do not
call restore_ld_library_path at all. Perhaps we could simply follow this
way?
Would failing tests still fail if remove restore_ld_library_path from
{asan, tsan, ubsan}_finish?
Hi
On 30/09/14 19:36, Jiong Wang wrote:
2014-09-30 17:30 GMT+01:00 Jeff Law :
On 09/30/14 08:37, Jiong Wang wrote:
On 30/09/14 05:21, Jeff Law wrote:
I do agree with Richard that it would be useful to see the insns that
are incorrectly sunk and the surrounding context.
So I must be missing
will cause it work on your and my test
environment but fail on others. because looks like
these restore_ld_library_path is added deliberately.
Regards,
Jiong
-Maxim
On 10/08/2014 06:30 PM, Jiong Wang wrote:
On 08/10/14 15:00, Maxim Ostapenko wrote:
Hm, as I see, others testsuites su
On 10/10/14 16:59, Richard Henderson wrote:
On 10/08/2014 08:31 AM, Jiong Wang wrote:
Ping ~
And as there is NONDEBUG_INSN_P check before move_insn_for_shrink_wrap invoked,
we could avoid creating new wrapper function by invoke single_set_2 directly.
I'm committing the following to fix
When testing arm-linux-gnueabihf triple with configure options
--with-mode=thumb(that makes -mthumb option default).
some testcase is failed with error message "sorry, unimplemented:
Thumb-1 hard-float VFP ABI".
I found gcc compiler show this error message when :
1. -mthumb is used with -march=armv
On 23/09/14 16:22, Stubbs, Andrew wrote:
Maybe the original patch is better? Or maybe it should reconfigure the FPU
instead of erroring out? But reconfigure it to what?
Andrew,
are you still working on this?
a bunch of tests on my local environment failed because of the reason James m
On 15/10/14 17:58, Andrew Stubbs wrote:
On 15/10/14 17:34, Jiong Wang wrote:
On 23/09/14 16:22, Stubbs, Andrew wrote:
Maybe the original patch is better? Or maybe it should reconfigure the
FPU instead of erroring out? But reconfigure it to what?
Andrew,
are you still working on this
the cause should be one minor bug in prepare_cmp_insn.
the last mode parameter "pmode" of "prepare_cmp_insn" should match the
mode of the first parameter "x", while during the recursive call of
"prepare_cmp_insn",
x is with mode of targetm.libgcc_cmp_return_mode () while pmode is assign to
word
Hi,
This patch is used to tune the gcc for Cortex-M7.
The performance of Dhrystone can be improved by 1%.
The performance of Coremark can be improved by 2.3%.
Patch also attached for convenience.
Is it ok for trunk?
Thanks and Best Regards,
Hale Wang
gcc/ChangeLog
2014-10-11 Hale Wang
Attach the patch.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Hale Wang
> Sent: Tuesday, October 21, 2014 5:49 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] Add arm_cortex_m7_tune.
>
> Hi,
. As for non-OS,
there will be no such a limit.
Some test cases are also added in the testsuite to verify this function.
Is it ok for trunk?
Thanks and Best Regards,
Hale Wang
gcc/ChangeLog:
2014-08-29 Hale Wang
* config/arm/arm-cores.def: Add support for
-mcpu=cortex-m0.small
this patch update arm testcases for recently gnu11 change.
ok for trunk?
thanks.
gcc/testsuite/
* gcc.target/arm/20031108-1.c: Add explicit declaration.
* gcc.target/arm/cold-lc.c: Likewise.
* gcc.target/arm/neon-modes-2.c: Likewise.
* gcc.target/arm/pr43920-2.c: Likewise.
* gcc.target
Update testcases for recent gnu11 changes.
ok for trunk?
thanks.
gcc/testsuite/
* gcc.target/aarch64/pic-constantpool1.c: Add explicit declaration.
* gcc.target/aarch64/pic-symrefplus.c: Likewise.
* gcc.target/aarch64/reload-valid-spoff.c: Likewise.
* gcc.target/aarch64/vect.x: Likewise
On 19/08/14 17:30, Mike Stump wrote:
On Aug 19, 2014, at 6:12 AM, Kyrill Tkachov wrote:
So how about this?
Ok. Thanks.
looks like this patch only fixed one invoke path.
currently, "gcc-dg-prune" may be invoked directly *or* via
${tool}_check_compile:
and "gcc-dg-prune" is implemented to
On 21/10/14 15:13, Ramana Radhakrishnan wrote:
On 21/10/14 14:48, Jiong Wang wrote:
this patch update arm testcases for recently gnu11 change.
ok for trunk?
This is OK bar the minor nit in the ChangeLog below - as a follow up it
would be nice to see if we can use the ACLE feature macros
On 20/10/14 19:21, Andrew MacLeod wrote:
creates cfg.h, cfganal.h, lcm.h, and loop-unroll.h to house the
prototypes for those .c files.
cfganal.h also gets "struct edge_list" and "class control_dependences"
definitions since that is where all the routines and manipulators are
declared.
loo
On 21/10/14 17:30, Andrew MacLeod wrote:
Try the following patch.
Apparently missed because that target is not in contrib/config-list.mk
and no other target must have enabled that code path. Seems to work now.
checked in as obvious.
verified OK, thanks.
Regards,
Jiong
Andrew
config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define
__ARM_FEATURE_IDIV__.
Also fixed the missing '\' on the last line as obvious
2014-10-22 Jiong Wang
gcc/
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Add missing '\'.
PR 63574 ICE building libjava (segfault) on arm-linux-gnueabihf is
caused by this commit.
from the backtrace, the ICF pass is trying to compare two label tree
node without type info.
while looks like "compare_operand" expect the type info always be not
empty before invoking "func_checker::compati
we should not add explicit declaration there.
arm_neon.h contains those prototype already. they will be available if the
compiler configuration is with related builtin predefine, for example
__ARM_FEATURE_CRYPTO.
so, actually, if there is any warning when compile these test programs, they
are
a furhter cleanup under aapcs sub-directory.
ok for trunk?
gcc/testsuite/
* gcc.target/arm/aapcs/abitest.h: Declare memcpy.
diff --git a/gcc/testsuite/gcc.target/arm/aapcs/abitest.h b/gcc/testsuite/gcc.target/arm/aapcs/abitest.h
index 06a92c3..7bce58b 100644
--- a/gcc/testsuite/gcc.target/arm/
ping~
thanks.
Regards,
Jiong
On 17/10/14 13:04, Jiong Wang wrote:
the cause should be one minor bug in prepare_cmp_insn.
the last mode parameter "pmode" of "prepare_cmp_insn" should match the
mode of the first parameter "x", while during the recursive call of
On 24/10/14 12:50, Marek Polacek wrote:
diff --git a/gcc/testsuite/gcc.target/arm/aapcs/abitest.h
b/gcc/testsuite/gcc.target/arm/aapcs/abitest.h
index 06a92c3..7bce58b 100644
--- a/gcc/testsuite/gcc.target/arm/aapcs/abitest.h
+++ b/gcc/testsuite/gcc.target/arm/aapcs/abitest.h
@@ -49,6 +49,8 @@
On 24/10/14 19:41, Jeff Law wrote:
On 10/24/14 08:09, Jiong Wang wrote:
ping~
thanks.
Regards,
Jiong
On 17/10/14 13:04, Jiong Wang wrote:
the cause should be one minor bug in prepare_cmp_insn.
the last mode parameter "pmode" of "prepare_cmp_insn" should match t
On 27/10/14 15:30, Ilya Palachev wrote:
Hi all,
The attached patch is an attempt to fix the bug PR ipa/63576.
As it is said in the comment to the bug,
Jan Hubicka wrote:
THen you need to sum counts (instead of taking ones from BB) and
turn them back to frequencies (because it is profile only
t is reasonable because size of mul is far
smaller than size of div.
ChangLog changes are:
***gcc/libgcc/ChangeLog***
2014-05-28 Tony Wang
* config/arm/lib1funcs.S (FUNC_START): Add conditional section
redefine for macro L_arm_muldivsf3 and L_arm_muldivdf3
Bootstrapped on x86_6
For AArch64, there may have been an odd num core registers need to be saved.
This small patch ensure we remain 16 byte aligned for subsequent STP writes of
D registers.
OK for trunk?
thanks.
gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Make sure start offset
for vector regist
/test_frame_13.c: Likewise.
* gcc.target/aarch64/test_frame_14.c: Likewise.
* gcc.target/aarch64/test_frame_15.c: Likewise.
commit ec07ddf26d31696b61d6ffbff52227bb5e86bd2a
Author: Jiong Wang
Date: Fri Jun 6 10:18:19 2014 +0100
[AArch64] Add a set of stack layout testcases.
The following
This patch add predicate for storewb_pair/loadwb_pair, because aarch64
register pair push and pop instructions only accept constant offset
within certain range.
OK for trunk?
Thanks.
gcc/ChangeLog:
2014-06-12 Renlin Li
* config/aarch64/aarch64.c (offset_7bit_signed_scaled_p): Rename to
and new lto tests are added in gcc.target/arm/lto.
Bootstrap and no make check regression on X86-64.
Patch also attached for convenience. Is It ok for trunk?
Thanks and Best Regards,
Hale Wang
c-family/ChangeLog
2014-06-18 Hale Wang
PR lto/61123
*c.opt
> -Original Message-
> From: Mike Stump [mailto:mikest...@comcast.net]
> Sent: 2014年6月19日 1:42
> To: Richard Biener
> Cc: Hale Wang; Mike Stump; GCC Patches
> Subject: Re: [PATCH] PR61123 : Fix the ABI mis-matching error caused by
LTO
>
> On Jun 18, 2014, at
> -Original Message-
> From: Jakub Jelinek [mailto:ja...@redhat.com]
> Sent: 2014年6月21日 5:24
> To: Hale Wang
> Cc: 'Mike Stump'; Richard Biener; Mike Stump; GCC Patches
> Subject: Re: [Committed] [PATCH] PR61123 : Fix the ABI mis-matching error
> caused b
> -Original Message-
> From: Terry Guo [mailto:flame...@gmail.com]
> Sent: Wednesday, April 22, 2015 3:24 PM
> To: Segher Boessenkool
> Cc: l...@redhat.com; Hale Wang; GCC Patches; Richard Sandiford
> Subject: Re: Ping^3 : [PATCH] [gcc, combine] PR46164: Don't c
Jeff Law writes:
> For all kinds of reassociation we have to concern ourselves with adding
> overflow where it didn't already occur. Assuming a 32 bit architecture
> we could get overflow if A is 0x7fff, b is -4 and and c = 3
>
> 0x7fff + -4 = 0x7ffb
> 0x7ffb + 3 = 0x7ffe
>
> -Original Message-
> From: Segher Boessenkool [mailto:seg...@kernel.crashing.org]
> Sent: Thursday, May 14, 2015 9:29 PM
> To: Hale Wang
> Cc: l...@redhat.com; GCC Patches; Richard Sandiford; 'Terry Guo'
> Subject: Re: [PATCH] [gcc, combine] Backport to GCC
p, we use pseudo pic reg, and let
register allocator to use any one possible.
Binutils correspondent
test done
=
gcc bootstrap OK on aarch64 board with BOOT_CFLAGS="-O2 -fpic".
built glibc under -fpic, code size slightly smaller.
Ok for trunk?
2015-05-20 Jiong. Wang
gcc/
Shawcroft
Jiong Wang
gcc/
* config/aarch64/aarch64-protos.h (arch64_symbol_type): Rename
SYMBOL_SMALL_TPREL to SYMBOL_TLSLE.
(aarch64_symbol_context): Ditto.
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Ditto.
(aarch64_expand_mov_immediate): Ditto.
(aarch64_pri
Similar to the rename from SYMBOL_SMALL_TPREL to SYMBOL_TLSLE, this
patch rename the rtl pattern name.
ok for trunk?
2015-05-19 Jiong Wang
gcc/
* config/aarch64/aarch64.md (tlsle_small): Rename to tlsle.
(tlsle_small_): Rename to tlsle_.
* config/aarc64/aarch64.c
Add new unspec name UNSPEC_TLSLE, use it for all tlsle pattern.
ok for trunk?
2015-05-19 Jiong Wang
gcc/
* config/aarch64/aarch64.md (UNSPEC_TLSLE): New enumeration.
(tlsle): Use new unspec name.
(tlsle_): Ditto.
--
Regards,
Jiong
diff --git a/gcc/config/aarch64/aarch64.md b/gcc
301 - 400 of 1056 matches
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