[PATCH, ARM] Improved core -> NEON extend

this patch is ready to merge as well at this point. ] Tested on arm-linux-gnueabi. OK for mainline? Bye, Ulrich 2012-11-13 Andrew Stubbs Ulrich Weigand gcc/ * config/arm/arm.md (zero_extenddi2): Add extra alternatives for NEON registers. Add a

Re: VEC re-write [patch 01/25]

enabled). "affine_fn" is defined in tree-data-ref.h as: typedef vec affine_fn; which apparently is no longer a POD type? Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [PR middle-end/55398] Convert vec<> into a POD

ld public. > > Rename field vec_ to vec_PRIVATE_. > > Update all users. > > (va_heap::release): Do nothing if V is NULL. > > (va_stack::release): Likewise. > > Committed as rev 193667. This fixed the spu-elf build failure. Thanks! Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [patch] [s390] add multiarch definitions for s390-linux-gnu

Matthias Klose wrote: > 2012-11-14 Matthias Klose > > * config/s390/t-linux64: Add multiarch names in MULTILIB_OSDIRNAMES. This is OK. Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[PING, PATCH, ARM] Improved core -> NEON extend

http://gcc.gnu.org/ml/gcc-patches/2012-11/msg00984.html Ping. Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[RFC] Wrong register numbers in .dwarf_frame on Linux/PowerPC

t with GCC 4.0 and 4.1 unless we want to add a special hack for that. 3. Like 2., but remove the condition code hack: simply use identical numbers in .eh_frame and .dwarf_frame. This would make PowerPC like other Linux platforms in that respect. Thoughts? Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [RFC] Wrong register numbers in .dwarf_frame on Linux/PowerPC

Mark Kettenis wrote: > > Date: Mon, 26 Nov 2012 20:10:06 +0100 (CET) > > From: "Ulrich Weigand" > > > > Hello, > > > > I noticed what appears to be a long-standing bug in generating .dwarf_frame > > sections with GCC on Linux on PowerPC. >

Re: [RFC] Wrong register numbers in .dwarf_frame on Linux/PowerPC

eh_frame and .dwarf_frame. The only other such platforms I'm aware of are Darwin on 32-bit i386, and some other operating systems on ppc (AIX, Darwin, BSD). Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [RFC] Wrong register numbers in .dwarf_frame on Linux/PowerPC

David Edelsohn wrote: > On Mon, Nov 26, 2012 at 2:10 PM, Ulrich Weigand wrote: > > > So I'm wondering where to go from here. I guess we could: > > > > 1. Bring GCC (and gas) behaviour in compliance with the documented ABI > >by removing the #undef DBX

Re: [PATCH] DATA_ALIGNMENT vs. DATA_ABI_ALIGNMENT (PR target/56564)

ent for every use, too.) Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[PATCH, rs6000] Rename GCC version in warning messages

@ -10428,7 +10428,7 @@ warned = true; inform (input_location, "the ABI of passing homogeneous float aggregates" - " has changed in GCC 4.10"); + " has changed i

Re: [PATCH 1/9] Gccgo port to s390[x] -- part I

ething like: #if defined(__powerpc64__) && _CALL_ELF != 2 defering_fn = *(void **)defering_fn; #endif to __go_set_defering_fn (or possibly __go_can_recover). [ Since the runtime is compiled for the target with the appropriate ABI setting, the #if works as intended when in runtime code. ] Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno

r numbers and does not know how > to map them to hardware registers. As I understand it, the change was supposed to only affect GCC internals, all externally generated debug info was supposed to remain unchanged. If there are changes in debug info, something must have gone wrong. Bye, Ulrich

[PATCH, rs6000] Keep TOC register live in TLS lo_sum patterns

de : SImode); @@ -11311,7 +11315,8 @@ (define_insn "*tls_got_tprel_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") -(unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] +(unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") + (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGOTTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "l %0,%2@got@tprel@l(%1)" -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[commit] Fix SPU breakage (Re: [patch] Stop using JUMP_INSN for jump table data)

d (new_insn); + INSN_LOCATION (new_insn) = UNKNOWN_LOCATION; + return; + } + p = get_pipe (insn); if ((CALL_P (insn) || JUMP_P (insn)) && SCHED_ON_EVEN_P (insn)) new_insn = emit_insn_after (gen_lnop (), insn); -- Dr. Ulrich Weigand GNU Toolchain for

Re: var-tracking and s390's LM(G)

on s390 otherwise: http://gcc.gnu.org/ml/gcc-patches/2003-05/msg00904.html And the background of the bug here: http://gcc.gnu.org/ml/gcc/2003-05/msg00536.html Actually, now I think the problem originally described there is still valid: on s390 the CFA is *not* equal to the value at function entry

Re: var-tracking and s390's LM(G)

SP to the CFA is wrong ... Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: var-tracking and s390's LM(G)

Jakub Jelinek wrote: > On Wed, Feb 05, 2014 at 10:26:16PM +0100, Ulrich Weigand wrote: > > Actually, now I think the problem originally described there is still > > valid: on s390 the CFA is *not* equal to the value at function entry, > > but biased by 96/160 bytes. So sett

[PATCH, rs6000] Remove most -mcall- options from consideration in ENDIAN_SELECT

uot;, CC1_ENDIAN_BIG_SPEC }, \ - { "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \ - { "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \ { "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \ { "cpp_os_ads", CPP_OS_ADS_SPEC }, \ { "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \ -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [RFA][middle-end/52306] Fix reload from creating invalid RTL

orward. Thanks for looking into this! > PR middle-end/52306 > * reload1.c (emit_input_reload_insns): Do not create invalid RTL > when changing the SET_DEST of a prior insn to avoid an input > reload. This is OK. Thanks, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [RS6000] power8 internal compiler errors

t might be easier and cheaper overall to just do a find_replacement within the PRE_MODIFY clause ... If you really prefer a check, I guess you can always do something like: #ifdef ENABLE_CHECKING gcc_assert (find_replacement (&XEXP (...)) == XEXP (...)); #endif Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [RS6000, patch] pr57936, ICE in rs6000_secondary_reload_inner

ch reloads when both the input and output need secondary reload registers. */ Note the condition "if OLDEQUIV and OLD are different" should be true if the input value was inherited. Can you check whether this case is hit with your test case? Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [RS6000, patch] pr57936, ICE in rs6000_secondary_reload_inner

ng along. OK to apply, assuming no regressions? > > PR target/57935 > * reload1.c (emit_input_reload_insns): When reload_override_in, > set old to rl->in_reg when rl->in_reg is a subreg. This is OK, assuming no regressions. Thanks, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [PATCH, rs6000] Restrict reload use of FLOAT_REGS

_p (GENERAL_REGS, rclass)) return GENERAL_REGS; else if (reg_class_subset_p (BASE_REGS, rclass)) return BASE_REGS; else return NO_REGS; } (which is similar to how we did it for s390). Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

[PATCH, rs6000] Fix ELFv2 homogeneous float aggregate ABI bug

(TARGET_32BIT ? 4 : 8); + + if (align_words + fpr_words < GP_ARG_NUM_REG) + passed_in_gprs = true; + else + ret = fpr; + } } if (passed_in_gprs -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

[PATCH, rs6000] Fix aggregate alignment ABI issue

milar for the Darwin64 ABI. Note that for historical reasons we + implement the "aggregate type" check as a BLKmode check here; this + means certain aggregate types are in fact not aligned. */ + else if (TARGET_MACHO && rs6000_darwin64_abi &&a

[PATCH, rs6000] Fix alignment of non-Altivec vector struct fields

field FIELD if the - alignment computed in the usual way is COMPUTED. */ -#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ - ((TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ -? 128 : COMPUTED) - #undef BIGGEST_FIELD_ALIGNMENT /* Use ELF style section commands. */ -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [PATCH, rs6000] Fix alignment of non-Altivec vector struct fields

David Edelsohn wrote: > On Wed, Jul 9, 2014 at 12:06 PM, Ulrich Weigand wrote: > > Hello, > > > > running the ABI compatibility test suite against another compiler showed > > strange effects caused by code in ADJUST_FIELD_ALIGN on rs6000: > > > > #de

Re: [PATCH, rs6000] Fix ELFv2 homogeneous float aggregate ABI bug

ior to the 4.8 and 4.9 branches. This should match existing precent of how to handle ABI changes. Doing a world-rebuild with the warnings enabled would certainly be extremely useful feedback ... Thanks, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

[PATCH, rs6000, v2] Fix ELFv2 homogeneous float aggregate ABI bug

target/powerpc/ppc64-abi-warn-1.c (revision 0) @@ -0,0 +1,12 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-options "-mabi=elfv2" } */ + +struct f8 + { +float x[8]; + }; + +void test (struct f8 a, struct f8 b) /* { dg-message "note: t

[PATCH, rs6000, v2] Fix aggregate alignment ABI issue

n 0) @@ -0,0 +1,11 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ + +struct test + { + long a __attribute__((aligned (16))); + }; + +void test (struct test a) /* { dg-message "note: the ABI of passing aggregates with 16-byte alignment has changed" } */ +{ +} + -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

[RFC, rs6000, v2] Fix alignment of non-Altivec vector struct fields

quot; } */ + +struct test + { +int a __attribute__((vector_size (8))); + }; /* { dg-message "note: the layout of aggregates containing vectors with 8-byte alignment has changed" } */ + -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [RFC, rs6000, v2] Fix alignment of non-Altivec vector struct fields

powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +struct test + { +int a __attribute__((vector_size (8))); + }; /* { dg-message "note: the layout of aggregates containing vectors with 8-byte alignment has changed" } */ + -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [RFC, rs6000, v2] Fix alignment of non-Altivec vector struct fields

Richard Biener wrote: > On Mon, Jul 14, 2014 at 8:55 PM, Ulrich Weigand wrote: > > Hello, > > > > this is an attempt to update the prior patch: > > https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00635.html > > to add a -Wpsabi note as discussed. > >

[PATCH, rs6000, 4.8/4.9] Fix ELFv2 homogeneous float aggregate ABI bug

@ -0,0 +1,12 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-options "-mabi=elfv2" } */ + +struct f8 + { +float x[8]; + }; + +void test (struct f8 a, struct f8 b) /* { dg-message "note: the ABI of passing homogeneous float aggregates will change" } */ +{ +} + -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

[PATCH, rs6000, 4.8/4.9] Fix aggregate alignment ABI issue

++ gcc-4_9-branch/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ + +struct test + { +long a __attribute__((aligned (16))); + }; + +void test (struct test a) /* { dg-message "note: the ABI of passing aggregates with 16-byte alignment will change" } */ +{ +} + -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

[PATCH, rs6000, 4.8/4.9] Fix alignment of non-Altivec vector struct fields

struct test + { + int a __attribute__((vector_size (8))); + }; /* { dg-message "note: the layout of aggregates containing vectors with 8-byte alignment will change" } */ + -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

[PATCH, testsuite] Reliably prune GCC notes in C++ compat suite

after the compat-use-*-compiler definitions. load_lib compat.exp +# Provide the g++-dg-prune routine (gcc-dp.exp is loaded by compat.exp) +load_lib g++-dg.exp + g++_init # Save variables for the C++ compiler under test, which each test will -- Dr. Ulrich Weigand GNU/Linux compilers and

[PING, PATCH, testsuite] Reliably prune GCC notes in C++ compat suite

s. > load_lib compat.exp > > +# Provide the g++-dg-prune routine (gcc-dp.exp is loaded by compat.exp) > +load_lib g++-dg.exp > + > g++_init > > # Save variables for the C++ compiler under test, which each test will > > -- > Dr. Ulrich Weigand > GNU/Linux compilers and toolchain > ulrich.weig...@de.ibm.com > -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno

*/ \ > + &rs6000_reg_names[118][0], /* SPE rh1 */ \ > + &rs6000_reg_names[119][0], /* SPE rh2 */ \ You need to actually initialize those rs6000_reg_names field in rs6000.c if you refer to them here. Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [PATCH, rs6000, v2] Fix ELFv2 homogeneous float aggregate ABI bug

David Edelsohn wrote: > On Mon, Jul 14, 2014 at 2:52 PM, Ulrich Weigand wrote: > > gcc/testsuite/ChangLog: > > > > * config/rs6000/rs6000.c (rs6000_function_arg): If a float argument > > does not fit fully into floating-point registers, and there is sti

Re: [PATCH, rs6000, 4.8/4.9] Fix alignment of non-Altivec vector struct fields

ain.m execution test This is strange; I'm not seeing these test FAIL. (I do see the warning in the log, just as with the C and C++ tests, but the warning is filtered out by the dejagnu scripts and doesn't cause failures). However, I've been testing with the above version of the

[commit, 4.8/4.9, libobjc] Match branch ABI (Re: [PATCH, rs6000, 4.8/4.9] Fix alignment of non-Altivec vector struct fields)

AX (COMPUTED, SPECIFIED));}) -#define rs6000_special_adjust_field_align_p(FIELD, COMPUTED) 0 +#define rs6000_special_adjust_field_align_p(FIELD, COMPUTED) \ + (TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) /* Skip a variable name, enclosed in quotes (").

[commit, s390] Fix TPF unwinder

Hello, I've checked in a fix provided by Jim Johnston on the TPF team to fix a case where the special TPF unwinder didn't work correctly. Tested on TPF by Jim, committed to mainline. Bye, Ulrich ChangeLog: gcc/ 2014-07-30 Ulrich Weigand * config/s

Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno

looks good to me. (Of course, I cannot approve the patch myself.) Thanks, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno

(REG_ALLOC_ORDER) : Likewise. > > (enum reg_class) : Likewise. > > (REG_CLASS_NAMES) : Likewise. > > (REG_CLASS_CONTENTS) : Likewise. > > (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. > > > > * gcc.target/pow

[patch, libgfortran] Fix SPU link failures (Re: Set close-on-exec flag when opening files)

1 "configure" #include "confdefs.h" #if HAVE_DLFCN_H --- 12449,12455 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF ! #line 12452 "configure" #include "confdefs.h&q

Re: [4.8, PATCH 0/26] Backport Power8 and LE support

on the stack, when only the stack will be used by a callee correctly > implementing either ELFv2 or ELFv1 ABIs. Another thing that we didn't > change is that sibcalls can be allowed in more cases than the current > code allows. I concur with Jeff and Alan that 9/26 should be safe. Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

[PATCH] Support spu-elf in libstdc++ crossconfig.m4

Hello, currently, there is no support for spu-elf in crossconfig.m4. In the past, we've usually worked around this by configuring GCC with --with-newlib. But that has other drawbacks since it performs no link tests at all, and thus assumes only a very minimal set of features available via newlib

Re: [PATCH] Support spu-elf in libstdc++ crossconfig.m4

Jonathan Wakely wrote: > On 20 March 2014 18:04, Ulrich Weigand wrote: > > Hello, > > > > currently, there is no support for spu-elf in crossconfig.m4. In the past, > > we've usually worked around this by configuring GCC with --with-newlib. > > > > Bu

[PATCH, rs6000] Avoid clobbering stack pointer via P8 fusion peephole

being loaded is the stack pointer, we must + avoid loading any other value into it, even temporarily. */ + if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM) + return false; } base_reg = XEXP (addr, 0); -- Dr. Ulrich Weigand GNU/Linux compilers

[commit, spu] Fix regression (ICE) in g++.dg/torture/pr57499.C

2064,2070 } hbr_insn = insn; } ! if (INSN_CODE (insn) == CODE_FOR_blockage && next_insn) { if (GET_MODE (insn) == TImode) PUT_MODE (next_insn, TImode); -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain ulrich.weig...@de.ibm.com

[commit, spu] Fix regression (ICE) in gcc.dg/pr48335-2.c

ot;const_int_operand" "")) (match_operand 3 "nonmemory_operand" ""))] "" ! { ! if (INTVAL (operands[1]) + INTVAL (operands[2]) ! > GET_MODE_BITSIZE (GET_MODE (operands[0]))) ! FAIL; ! spu_expand_insv(operands); ! DONE; ! })

[PING^2, PATCH, ARM] Improved core -> NEON extend

> http://gcc.gnu.org/ml/gcc-patches/2012-11/msg00984.html > Ping. -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [Patch] Ignore Invalid Memory operands in constraint 'X'

for "X" are those that imply side-effects like pre-increment. ] > Fixes the ICE gcc.dg/torture/asm-subreg-1.c on aarch64. Clearly the compiler shouldn't crash either, but I guess it really ought to be possible to fix this problem elsewhere. Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [Patch] Fix PR54814

e > code at all. > > Thus, ok from a RM perspective if a reload-affine person approves it. The patch was originally by Bernd, but FWIW it looks good to me as well. Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [RFA] Fix DEBUG_RELOAD support

Matthew Gretton-Dann wrote: > 2013-02-02 Matthew Gretton-Dann > > * gcc/reload.c (subst_reloads): Fix DEBUG_RELOAD build issue. This is OK. Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[commit, spu] Fix -fPIC wrong-code regression

insn = emit_insn (gen_load_pic_offset (pic_reg, scratch_reg_0)); insn = emit_insn (gen_subsi3 (pic_reg, pic_reg, scratch_reg_0)); } --- 2053,2061 } } ! if (flag_pic && cfun->machine->pic_reg) { ! rtx pic_reg = cfun->machine->

[commit, spu] Fix PR target/50310 (unordered vector compares)

turn mask; + } + break; default: gcc_unreachable (); } -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [PATCH 2/6] Generate virtual locations for tokens

eyword. With your changes to cpp_get_token (which is the sole caller of the macro_to_expand callback), are there any changes in the interface to the callback? Any suggestions what could be going on here? Note that the implementation of the callback is in config/spu/spu-c.c:spu_macro_to_expand Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [PATCH, libcpp] Fix thinko in _cpp_remaining_tokens_num_in_context (PR bootstrap/50801)

am proposing the > patch even if I don't know if it bootstraps on SPU or PPC in general. Well, SPU doesn't bootstrap as such (it's a target-only architecture), but I can confirm that the patch does fix the newlib build failure I was seeing on SPU. Thanks for the quick fix! By

Re: [PATCH, libcpp] Fix thinko in _cpp_remaining_tokens_num_in_context (PR bootstrap/50801)

se if (context->tokens_kind == TOKENS_KIND_INDIRECT || context->tokens_kind == TOKENS_KIND_EXTENDED) return ((LAST (context).ptoken - FIRST (context).ptoken) / sizeof (cpp_token *)); "ptoken" seems to be of type "const cpp_token **", so the pointer subtra

[commit, spu] Fix vec_perm pattern (Re: [rs6000, spu] Add vec_perm named pattern)

nd:V16QI 0 "spu_reg_operand" "") (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "") (match_operand:V16QI 2 "spu_reg_operand" "") ! (match_dup 5)] UNSPEC_SHUFB))] "" { ! operands[4] = gen_reg_rtx (V16QImode); ! operands[5] = gen_lowpart (TImode, operands[4]); ! operands[6] = spu_const (V16QImode, 31); }) (define_insn "nop" -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [PATCHv2, RFA] Pass address space to REGNO_MODE_CODE_OK_FOR_BASE_P

up as requirement. If you'd like to add such optimizations for AVR, it would be straightforward to pass the address space argument to LEGITIMIZE_RELOAD_ADDRESS. But that can certainly be done as an independent patch. Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System

Re: [PATCH 0/6] More vector permutation work

sel, 0, OPTAB_DIRECT); gcc_assert (sel != NULL); This fails since for u == 4 and mode == V4SFmode it attempts to expand a V4SFmode shift, which is unsupported. Shouldn't this be using the mode of the selector rather than the mode of the result in any case? Bye, U

Re: [PATCH 0/6] More vector permutation work

Richard Henderson wrote: > On 10/26/2011 07:30 AM, Ulrich Weigand wrote: > > This fails since for u == 4 and mode == V4SFmode it attempts to expand > > a V4SFmode shift, which is unsupported. > > > > Shouldn't this be using the mode of the selector rather than t

Re: [PATCH 0/6] More vector permutation work

> Richard Henderson wrote: > > On 10/26/2011 07:30 AM, Ulrich Weigand wrote: > > > This fails since for u == 4 and mode == V4SFmode it attempts to expand > > > a V4SFmode shift, which is unsupported. > > > > > > Shouldn't this be using the mode

[PING] Pass address space to REGNO_MODE_CODE_OK_FOR_BASE_P

The following patch still needs maintainer review: http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01874.html Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

SPU build broken (Re: CFT: [build] Move libgcc2 to toplevel libgcc)

es in LIB2ADD or LIB2ADD_ST.. Stop. Shouldn't the variable still be called LIB2FUNCS_EXCLUDE after the move to libgcc? LIB2ADD seems to expect full file names ... Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [PING] Pass address space to REGNO_MODE_CODE_OK_FOR_BASE_P

Bernd Schmidt wrote: > On 10/28/11 18:06, Ulrich Weigand wrote: > > > > The following patch still needs maintainer review: > > http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01874.html > > Looks straightforward to me. OK. Thanks! I've checked the patch in now. Ge

Re: Mark objects death@end of scope

utines. But for the SjLj unwinder, it's a bit counter-productive ... Any thoughts how to fix this? Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: SPU build broken (Re: CFT: [build] Move libgcc2 to toplevel libgcc)

Rainer Orth wrote: > "Ulrich Weigand" writes: > > Shouldn't the variable still be called LIB2FUNCS_EXCLUDE after the > > move to libgcc? LIB2ADD seems to expect full file names ... > > Of course, the change is bogus. I can only (half) explain this by the

Re: Mark objects death@end of scope

Michael Matz wrote: > On Fri, 11 Nov 2011, Ulrich Weigand wrote: > > > One reason why this happens is that the unwind*.c files are specifically > > built with -fexception. I think this is for the benefit of the DWARF > > unwinder, to ensure CFI records are avai

[RFA 4.7/4.6] Re: [PATCH v2] Target-specific limits on vector alignment

Richard Guenther wrote: > On Fri, Jul 27, 2012 at 5:24 PM, Ulrich Weigand wrote: > > ChangeLog: > > > > * target.def (vector_alignment): New target hook. > > * doc/tm.texi.in (TARGET_VECTOR_ALIGNMENT): Document new hook. > >

Re: [PATCH v3] s390: Convert from sync to atomic optabs

pand_insv to aid that. Try RISBG last, after other > mechanisms have failed; don't require operands in registers for > it but force them there instead. Try a limited form of ICM. This looks good to me. Retested with no regressions. Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchai

Re: s390: Avoid CAS boolean output inefficiency

Richard Henderson wrote: > On 08/06/2012 11:34 AM, Ulrich Weigand wrote: > > There is one particular inefficiency I have noticed. This code: > > > > if (!__atomic_compare_exchange_n (&v, &expected, max, 0 , 0, 0)) > > abort (); > > > > from

Re: s390: Avoid CAS boolean output inefficiency

Richard Henderson wrote: > On 08/07/2012 10:02 AM, Ulrich Weigand wrote: > > The following patch changes the builtin expander to pass a MEM oldval > > as-is to the back-end expander, so that the back-end can move the > > store to before the CC operation. With that patch I&

Re: s390: rearrange temp moves in s390_expand_cs_hqi

nse. > Can you please test with --with-arch=z10? Tested with no regressions. > * config/s390/s390.c (s390_expand_cs_hqi): Copy val to a temp before > performing the compare for the restart loop. OK. Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[commit 4.7] Re: [PATCH v2] Target-specific limits on vector alignment

Richard Guenther wrote: > On Tue, Aug 7, 2012 at 4:56 PM, Ulrich Weigand wrote: > > Would it be OK to backport this to 4.7 and possibly 4.6? > I'll defer the decision to the target maintainers. But please double-check > for any changes in the vectorizer parts when backpor

[commit 4.6] Re: [PATCH v2] Target-specific limits on vector alignment

Richard Guenther wrote: > On Tue, Aug 7, 2012 at 4:56 PM, Ulrich Weigand wrote: > > Would it be OK to backport this to 4.7 and possibly 4.6? > I'll defer the decision to the target maintainers. But please double-check > for any changes in the vectorizer parts when backporti

[RFA wwwdocs] Re: [PATCH v2] Target-specific limits on vector alignment

es larger than 8 bytes in size), to comply with the AAPCS. +This is an ABI change that affects e.g. layout of structures having a member +of vector type. Code using such types may be incompatible with binary objects +built with older versions of GCC. + General Optimizer Improvements -- Dr

Re: [RFA wwwdocs] Re: [PATCH v2] Target-specific limits on vector alignment

Richard Earnshaw wrote: > On 10/08/12 14:44, Ulrich Weigand wrote: > > Would the following htdocs patch be OK with you? Feel free to suggest > > a more appropriate wording ... > > I think we need to make it clear that this also fixes a bug in the > compiler that could

Re: [RFA wwwdocs] Re: [PATCH v2] Target-specific limits on vector alignment

akes + explicit use of vector types may be incompatible with binary objects + built with older versions of GCC. Auto-vectorized code is not affected + by this change. + General Optimizer Improvements -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [PATCH 0/7] s390 improvements with r[ioxn]sbg

rl" > + [(set (zero_extract:DI > + (match_operand:DI 0 "nonimmediate_operand" "+d") > + (match_operand 1 "const_int_operand" "") > + (match_operand 2 "const_int_operand" "")) > + (and:DI > + (lshiftrt:DI > + (match_dup 0) > + (match_operand 3 "const_int_operand" "")) > + (match_operand:DI 4 "nonimmediate_operand" "d"))) > + (clobber (reg:CC CC_REGNUM))] > + "TARGET_Z10 > + && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL > (operands[2])" > + "rnsbg\t%0,%4,%2,%2+%1-1,64-%2,%1" I guess the last "," is supposed to be a "-". (Then we might as well use %3 instead of 64-%2-%1.) Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [PATCH] Remove basic_block->loop_depth

single_pred_p (bb) && prev->loop_depth == bb->loop_depth) prop = prev; Any suggestions? Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[rfc] Fix SPU build (Re: [PATCH] Remove basic_block->loop_depth)

Richard Guenther wrote: > On Tue, 14 Aug 2012, Ulrich Weigand wrote: > > Looks like this broke SPU build, since spu_machine_dependent_reorg > > accesses ->loop_depth. According to comments in the code, this > > was done because of concerns that loop_father may no longer be

Re: [rfc] Fix SPU build (Re: [PATCH] Remove basic_block->loop_depth)

Richard Guenther wrote: > On Wed, 15 Aug 2012, Ulrich Weigand wrote: > > It seems flow_loops_find by itself is not quite enough, but everything > > necessary to use the loop structures seems to be encapsulated in > > loop_optimizer_init / loop_optimizer_finalize, which are al

Re: [PATCH] proposed fix for PRs target/54516 & rtl-optimization/54540

that earlier passes > have deemed to be safe, and using them as a temporary is not one of those. This sounds reasonable, agreed. > * reload.c (find_dummy_reload): Don't use OUT as a reload reg > for IN if it overlaps a fixed register. OK. Thanks, Ulrich -- Dr. Ulri

Re: [Patch ARM] Update the test case to differ movs and lsrs for ARM mode and non-ARM mode

can-assembler "lsrs\tr\[0-9\]" { target arm_thumb2_ok } }} */ /* { dg-final { scan-assembler "movs\tr\[0-9\]" { target { ! arm_thumb2_ok} } } } */ --- 9,13 r[i] = 0; } ! /* { dg-final { scan-assembler "lsrs\tr\[0-9\]" { target arm_thumb2_ok } } } */ /* { dg-final { scan-assembler "movs\tr\[0-9\]" { target { ! arm_thumb2_ok} } } } */ -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[PATCH, ARM] Prefer vld1.64/vst1.64 over vldm/vstm

Ulrich Weigand * config/arm/arm.c (output_move_neon): Update comment. Use vld1.64/vst1.64 instead of vldm/vstm where possible. (neon_vector_mem_operand): Support double-word modes. * config/arm/neon.md (*neon_mov VD): Call output_move_neon instead

[PATCH, ARM] Use vld1/vst1 to implement vec_set/vec_extract

n arm-linux-gnueabi. OK for mainline? Bye, Ulrich 2012-09-14 Ulrich Weigand * config/arm/arm.c (arm_rtx_costs_1): Handle vec_extract and vec_set patterns. * config/arm/arm.md ("vec_set_internal"): Support memory source operands, implemented via v

Re: [PATCH, ARM] Prefer vld1.64/vst1.64 over vldm/vstm

Richard Earnshaw wrote: > On 14/09/12 19:02, Ulrich Weigand wrote: > > * config/arm/arm.c (output_move_neon): Update comment. > > Use vld1.64/vst1.64 instead of vldm/vstm where possible. > > (neon_vector_mem_operand): Support double-word modes. > > * co

Re: [PATCH, ARM] Use vld1/vst1 to implement vec_set/vec_extract

is used ... All other code in neon.md *either* transforms the NEON lane numbers into RTL subpart numbers and put those in vec_select etc. *or* uses a NEON lane number unchanged as argument of an UNSPEC. It was only this one pattern that broke this rule. > This is OK. Checked in. Thanks, Ulr

Re: [patch] Fix PR rtl-optimization/54290

ubreg" routine on rld[r].in, check whether the result is a hard register and use its REGNO_REG_CLASS. Bernd, given that you worked on this recently, any other thoughts? Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[PATCH, ARM] 64-bit shifts in NEON

g: 2012-09-17 Andrew Stubbs Ulrich Weigand * config/arm/arm.c (arm_print_operand): Add new 'E' format code. (arm_emit_coreregs_64bit_shift): Fix comment. * config/arm/arm.h (enum reg_class): Add VFP_LO_REGS_EVEN. (REG_CLASS_NAMES, REG_CLASS_CONTENTS, IS

Re: [patch] Fix PR rtl-optimization/54290

good to me. OK if testing passes. Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [PATCH, ARM] 64-bit shifts in NEON

ing > other overheads. What instruction are you refering to here? Loads from memory? Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[PATCH] Do not mark pseudo-copies decomposable during first lower-subreg pass

** static unsigned int rest_of_handle_lower_subreg2 (void) { ! decompose_multiword_subregs (); return 0; } --- 1656,1662 ---- static unsigned int rest_of_handle_lower_subreg2 (void) { ! decompose_multiword_subregs (true); return 0; } -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

[PATCH] Fix PR tree-optimization/53636 (SLP generates invalid misaligned access)

tf (vect_dump, "SLP: step doesn't divide the vector-size."); + misalign = NULL_TREE; + } + } + base = build_fold_indirect_ref (base_addr); alignment = ssize_int (TYPE_ALIGN (vectype)/BITS_PER_UNIT); -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com

Re: [PATCH] Fix PR tree-optimization/53636 (SLP generates invalid misaligned access)

Richard Guenther wrote: > On Fri, Jun 15, 2012 at 3:13 PM, Ulrich Weigand wrote: > > However, there is a second case where we need to check every pass: if > > we're not actually vectorizing any loop, but are performing basic-block > > SLP. In this case, it would ap

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