On 9/29/23 12:05, Jeff Law wrote:
On 9/12/23 12:54, Patrick O'Neill wrote:
This testcase causes lots of false-positives for machine description
files.
contrib/ChangeLog:
* check_GNU_style_lib.py: Skip machine description file bracket
linting.
OK. We probably need a compl
/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Specify -mabi=lp64d.
Signed-off-by: Patrick O'Neill
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wre
On 9/29/23 14:59, Jeff Law wrote:
On 9/29/23 15:37, Patrick O'Neill wrote:
Resolves this error on rv32gcv:
cc1: error: ABI requires '-march=rv32'
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c -O0 (test for
excess errors)
Tested for re
Hi Jakub,
A follow-up commit of yours (9d249b7e31e) is causing bootstrap failures
for riscv*-*-* targets.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111649
Patrick
On 9/29/23 03:42, Jakub Jelinek wrote:
Hi!
As reported by Jonathan on IRC, my vec.h patch broke build with GCC 4.8.x
or 4.9.x
Resolves a riscv*-*-* bootstrap failure due to a newly-turned-on assert.
2023-09-30 Jakub Jelinek
PR target/111649
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::vector_infos_manager):
Replace safe_grow with safe_grow_cleared.
---
https://gcc.gnu.org/bu
Committed. Thanks Juzhe!
I had to adjust the changelog's PR formatting to get the pre-commit
hooks to accept it.
Here's the committed patch:
From f446cf5d58568e406cc81f434a63b3045942e9a9 Mon Sep 17 00:00:00 2001
From: Patrick O'Neill
Date: Sat, 30 Sep 2023 15:50:11 -0700
.
Signed-off-by: Patrick O'Neill
---
gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
index 265e91
On 10/2/23 06:57, Kito Cheng wrote:
On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill wrote:
stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.
Tested using glibc rv32gcv and rv64gcv on r14-4258-gc9837443075.
gcc/Chan
On 10/3/23 14:55, Jeff Law wrote:
On 10/3/23 14:19, Patrick O'Neill wrote:
Some characters are escaped which causes the testcase to fail. This
patch restores the original characters.
Tested for regressions using multilib rv32gcv-ilp32d, rv64gcv-lp64d.
gcc/testsuite/Chan
][committed] Remove spurious newline in ztso sequence
Patrick O'Neill (2):
RISC-V: Add Ztso atomic mappings
RISC-V: Specify -mabi for ztso testcases
gcc/common/config/riscv/riscv-common.cc | 6 +
gcc/config/riscv/riscv-opts.h | 4 +
gcc/config/riscv/ris
could have easily missed it.
Regardless, fixing the extraneous newline is easy :-)
gcc/
* config/riscv/sync-ztso.md (atomic_load_ztso): Avoid extraenous
newline.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/sync-ztso.md | 4 ++--
1 file changed, 2 insertions(+), 2 del
On rv32 targets, this patch fixes ztso testcases errors like this:
cc1: error: ABI requires '-march=rv32'
2023-08-11 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add -mabi=lp64d
to dg-options.
* gcc.target/riscv
-psabi-doc/pull/391
2023-08-08 Patrick O'Neill
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as
dependent on 'a' extension.
* config/riscv/riscv-opts.h (MASK_ZTSO): New mask.
(TARGET_ZTSO): New target.
* config
Hi Joern,
I'm seeing new failures introduced by this patch
(9464e72bcc9123b619215af8cfef491772a3ebd9).
On rv64gcv:
FAIL: gcc.dg/pr90263.c scan-assembler memcpy
FAIL: gfortran.fortran-torture/execute/intrinsic_count.f90 execution,
-O2 -fomit-frame-pointer -finline-functions -funroll-loops
D
On 10/4/23 12:19, Joern Rennecke wrote:
On Wed, 4 Oct 2023 at 18:38, Patrick O'Neill wrote:
Hi Joern,
I'm seeing new failures introduced by this patch
(9464e72bcc9123b619215af8cfef491772a3ebd9).
On rv64gcv:
FAIL: gcc.dg/pr90263.c scan-assembler memcpy
My testing didn't flag
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: xfail riscv_v targets.
Signed-off-by: Patrick O'Neill
Co-authored-by: Joern Rennecke
---
gcc/test
On 10/4/23 15:14, Jeff Law wrote:
On 10/4/23 15:57, Patrick O'Neill wrote:
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: xfail riscv_v target
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: Skip riscv_v targets.
* gcc.target/riscv/rvv/base/pr90263.c: New test.
Signed-off-by: Patrick
On 10/4/23 15:29, Jeff Law wrote:
On 10/4/23 16:21, Patrick O'Neill wrote:
On 10/4/23 15:14, Jeff Law wrote:
On 10/4/23 15:57, Patrick O'Neill wrote:
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv
On 10/5/23 15:14, Jeff Law wrote:
On 10/4/23 16:55, Patrick O'Neill wrote:
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: Skip riscv_v ta
.
* gcc.target/riscv/rvv/vsetvl/pr111255.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Ditto.
Signed-off-by: Patrick O'Neill
---
Changes from v1:
- Avoid changing riscv_vector.h
Failures looked like this:
In file included from
/riscv-gnu-toolchain/build/sysroot/usr/in
Committed, thanks!
Patrick
On 10/5/23 17:51, Kito Cheng wrote:
LGTM
Patrick O'Neill 於 2023年10月6日 週五 07:46 寫道：
stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.
Tested using glibc rv32gcv and rv64gcv on r14
On 10/4/23 08:53, Jeff Law wrote:
On 10/3/23 16:26, Patrick O'Neill wrote:
I vaugely recall some discussion about backporting the Ztso mappings
along with the RVWMO mappings. Now that the RVWMO mappings have been
backported for 13.3, is there interest in also backporting the Ztso
map
Hi Lehua!
I ran the gcc testsuite on qemu before/after applying your patches to
305034e3 rv32/64gcv [1].
Baseline
= Summary of gcc testsuite =
| # of unexpected case / # of unique
unexpected case
|
_run-1.exe
PASS: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
(test for excess errors)
spawn riscv64-unknown-elf-run ./cond_convert_float2int_run-1.exe
bbl loader
On 2023/10/18 4:25, Patrick O'Neill wrote:
Hi Lehua!
I ran the gcc testsuite on qemu before/after applying your
mappings.rst
[2] https://inbox.sourceware.org/gcc-patches/ZFV8pNAstwrF2qBb@andrea/T/#t
[3] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/391
gcc/ChangeLog:
2023-07-17 Patrick O'Neill
* common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as
depend
riscv: fix error: control reaches end of non-void function
Patrick O'Neill (11):
RISC-V: Eliminate SYNC memory models
RISC-V: Enforce Libatomic LR/SC SEQ_CST
RISC-V: Enforce subword atomic LR/SC SEQ_CST
RISC-V: Enforce atomic compare_exchange SEQ_CST
RISC-V: Add AMO releas
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
sanitize memmodel input with memmodel_base.
Signed-off-by: Patrick O'Neill
---
gcc/co
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md: Change LR.aq/SC.rl pairs into
sequentially consistent LR.aqrl/SC.rl pairs.
Signed-off-by: Pa
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (atomic_cas_value_strong): Change
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
libgcc/ChangeLog:
* config/riscv/atomic.c: Change LR.aq/SC.rl pairs into
sequentially consistent LR.aqrl/SC.rl pairs.
Signed-off-by: Pa
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'Neill
PR target/89835
gcc/ChangeLog:
* config/riscv/sync.md (atomic_store): Use simple
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (mem_thread_fence_1): Change fence
depending on the given memory model.
S
ordering of both given models.
This change brings LR/SC ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_union_memmodels): Expose
riscv_union_memmodels function to sync.md.
* config/riscv/ris
This patch sets the relevant .rl bits on amo operations.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Change behavior
of %A to include release bits.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 7 +
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/ris
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-27 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test.
* gcc.target/riscv/amo-ta
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (atomic_load): Implement atomic
load mapping.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/sy
From: Martin Liska
Fixes:
gcc/config/riscv/sync.md:66:1: error: control reaches end of non-void function
[-Werror=return-type]
66 | [(set (attr "length") (const_int 4))])
| ^
PR target/109713
gcc/ChangeLog:
* config/riscv/sync.md: Add gcc_unreachable to a switch.
---
gcc
This final patch fixes an error introduced by patch 9/12 in this series.
I'll backport alongside the other patches once the 13 branch is unfrozen :)
On 7/25/23 18:22, Kito Cheng wrote:
OK for backport :)
On Wed, Jul 26, 2023 at 2:11 AM Patrick O'Neill wrote:
From: Martin Liska
The newly added testcase fails on rv32 targets with this message:
FAIL: gcc.target/riscv/rvv/autovec/madd-split2-1.c -O3 -ftree-vectorize (test
for excess errors)
verbose log:
compiler exited with status 1
output is:
cc1: error: ABI requires '-march=rv32'
Something like this appears to fix the
dg-options.
Signed-off-by: Patrick O'Neill
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
in
Thanks!
Here's the comitted patch:
https://inbox.sourceware.org/gcc-patches/20230728163758.377962-1-patr...@rivosinc.com/T/#u
On 7/27/23 15:11, juzhe.zhong wrote:
LGTM.Thanks. You can go ahead commit it.
Replied Message
FromPatrick O'Neill <mailto:patr...@rivosinc.co
No worries! I'm glad it was an easy fix ;)
On 7/27/23 19:55, Demin Han wrote:
Sorry for not consider rv32 config.
The fix is OK. If convenient, please commit it.
On 2023/7/28 4:46, Patrick O'Neill wrote:
The newly added testcase fails on rv32 targets with this message:
FAIL: gcc.ta
GCC 13.2 released[2] so I merged the series now that the branch is unfrozen.
Thanks,
Patrick
[2] https://inbox.sourceware.org/gcc/ZMJeq%2FY5SN+7i8a+@tucnak/T/#u
On 7/25/23 11:01, Patrick O'Neill wrote:
Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
Jeff Law.
If
-psabi-doc/pull/391
2023-08-08 Patrick O'Neill
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as
dependent on 'a' extension.
* config/riscv/riscv-opts.h (MASK_ZTSO): New mask.
(TARGET_ZTSO): New target.
* config
On 7/31/23 22:04, Jeff Law wrote:
On 7/17/23 15:28, Patrick O'Neill wrote:
The RISC-V Ztso extension currently has no effect on generated code.
With the additional ordering constraints guarenteed by Ztso, we can emit
more optimized atomic mappings than the RVWMO mappings.
This PR defi
Committed - thanks!
On 8/8/23 14:54, Palmer Dabbelt wrote:
On Tue, 08 Aug 2023 14:52:14 PDT (-0700), Patrick O'Neill wrote:
The RISC-V Ztso extension currently has no effect on generated code.
With the additional ordering constraints guarenteed by Ztso, we can emit
more optimized a
On rv32 targets, this patch fixes ztso testcases errors like this:
cc1: error: ABI requires '-march=rv32'
2023-08-11 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add -mabi=lp64d
to dg-options.
* gcc.target/riscv
On 8/11/23 13:44, Jeff Law wrote:
On 8/11/23 13:15, Patrick O'Neill wrote:
On rv32 targets, this patch fixes ztso testcases errors like this:
cc1: error: ABI requires '-march=rv32'
2023-08-11 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-z
case.
Co-authored-by: Charlie Jenkins
Signed-off-by: Patrick O'Neill
---
Trunk optimized these added testcases correctly.
GCC 13.2 and earlier do not optimize these cases correctly.
Expands on testcases added in:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;f=gcc/testsuite/gcc.t
: Patrick O'Neill
---
Trunk optimized these added testcases correctly.
GCC 13.2 and earlier do not optimize these cases correctly.
Expands on testcases added in:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;f=gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c;h=0ccf520d349a82dafca0deb3d307a1080e8
On 8/16/23 21:36, Jeff Law wrote:
On 8/16/23 19:17, Patrick O'Neill wrote:
This adds new regression tests to ensure half-register rotations are
correctly optimized into rori instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-rol-ror-08.c: New test.
* gcc.target/risc
FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions execution test
FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -g execution test
Thanks for the quick revision Lehua!
Tested-by: Patrick O'Neill
Patrick
On 10/19/2
execution test
FAIL: gfortran.dg/host_assoc_function_7.f90 -O3
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
-finline-functions execution test
FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -g execution test
Thanks for the quick revision Lehua!
Tested-by: Patrick O'Neill
.zh...@rivai.ai
*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2023-10-24 02:30
*To:* Lehua Ding <mailto:lehua.d...@rivai.ai>
*CC:* kito.cheng <mailto:kito.ch...@gmail.com>; rdapp.gcc
<mailto:rdapp@gmail.com>; palmer <mailto:pal.
del=medlow' 'CXXFLAGS_FOR_TARGET=-O2
-mcmodel=medlow'
On 10/23/23 15:50, 钟居哲 wrote:
I didn't reproduce it. How to enable RTL checking ?
juzhe.zh...@rivai.ai
*From:* Patrick O'Neill <mailto:patr...@rivo
_TARGET=-Os -mcmodel=medany'
'CXXFLAGS_FOR_TARGET=-Os -mcmodel=medany'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20231023 (experimental) (g70b66ac9bcb-dirty)
--------
juzh
The CI just picked it up:
https://github.com/ewlu/gcc-precommit-ci/issues/449#issue-1958483272
Since it doesn't apply to the CI's baseline hash it's only performing a
build.
I'll re-run it in the morning once the baseline has been updated.
In the meantime I started a full build+test run on my l
g++.target/riscv/rvv/rvv.exp: Add -mabi argument to CFLAGS.
Signed-off-by: Patrick O'Neill
---
Resolved failures:
FAIL: g++.target/riscv/rvv/base/bug-18.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-19.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-20.C (
On 10/26/23 06:30, Jeff Law wrote:
On 10/25/23 18:13, Patrick O'Neill wrote:
On rv32gcv testcases like g++.target/riscv/rvv/base/bug-22.C fail with:
FAIL: g++.target/riscv/rvv/base/bug-22.C (test for excess errors)
Excess errors:
cc1plus: error: ABI requires '-march=rv32'
inter -finline-functions
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,
-O3 -g
rv64gcv:
FAIL: gfortran.dg/matmul_6.f90 -O2 execution test
Tested-by: Patrick O'Neill
Patrick
On 10/26/23 01:13, Juzhe-Zhong wrote:
This patch addresses the redundant AVL/VL toggl
On 10/26/23 11:15, Robin Dapp wrote:
rv32gcv:
FAIL: gfortran.dg/intrinsic_pack_6.f90 -O2 execution test
FAIL: gfortran.dg/intrinsic_pack_6.f90 -O3 -g execution test
FAIL: gfortran.dg/matmul_3.f90 -O2 execution test
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,
On 8/25/23 15:36, Jeff Law wrote:
Spurred by Jivan's patch and a desire for cleaner testresults, I went
ahead and make the stack_save_restore tests independent of the precise
stack size by using a regexp.
Pushed to the trunk.
Jeff
Hi Jeff, A recent change that I'm still bisecting [1] cause
number
after __riscv_save_ and __riscv_restore_.
Signed-off-by: Patrick O'Neill
---
Tested using glibc rv64gc on r14-4980-g2672c60917d.
---
gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.t
On 10/27/23 11:02, Jeff Law wrote:
On 10/27/23 11:56, Patrick O'Neill wrote:
GCC recently changed to emit __riscv_restore_5 which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any number after __riscv_save_ and __riscv_restore_.
register in the
range of 1-9 for cm.push and cm.popret insns.
Signed-off-by: Patrick O'Neill
---
Tested using glibc rv64gc on r14-4980-g2672c60917d.
---
gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
/issues/499#issuecomment-1784446631
The patch was applied to this baseline:
https://github.com/gcc-mirror/gcc/commit/c6929b085580cf00cbc52b0f5b0afe2b9caa2a22
and no new failures or resolved failures were found when running the
testsuite.
Tested-by: Patrick O'Neill
Thanks!
Patrick
gcc/Ch
On 10/30/23 09:55, Jeff Law wrote:
On 10/30/23 10:37, Patrick O'Neill wrote:
GCC recently changed its register allocator which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any s register in the range of 1-9 for cm.push and cm.p
the
Ztso extension or add it to an existing -march.
Signed-off-by: Patrick O'Neill
---
.../riscv/amo-table-ztso-amo-add-1.c | 3 ++-
.../riscv/amo-table-ztso-amo-add-2.c | 3 ++-
.../riscv/amo-table-ztso-amo-add-3.c | 3 ++-
.../riscv/amo-table-ztso-amo-ad
.
* config/riscv/sync-ztso.md (atomic_load_ztso): Ditto.
(atomic_store_ztso): Ditto.
* config/riscv/sync.md (atomic_load): Ditto.
(atomic_store): Ditto.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/sync-rvwmo.md | 4 ++--
gcc/config/riscv/sync-ztso.md
/target-supports.exp: Add testing infrastructure to require the A
extension or add it to an existing -march.
Signed-off-by: Patrick O'Neill
---
This patch relies on the previous one in the series. If applied seperately,
amo-table-a-6-store-compat-3.c and amo-table-a-6-load-3.c mu
On 10/31/23 06:05, Jeff Law wrote:
On 10/30/23 18:49, Patrick O'Neill wrote:
Non-atomic targets are currently prevented from using the optimized
fencing for
seq_cst load/seq_cst store. This patch removes that constraint.
gcc/ChangeLog:
* config/riscv/sync-rvwmo.md (atomic_load_
On 10/31/23 06:07, Jeff Law wrote:
On 10/30/23 18:49, Patrick O'Neill wrote:
Add testsuite infrastructure for the A extension and use it to
require the A
extension for dg-do run and add the add extension for non-A dg-do
compile.
gcc/testsuite/ChangeLog:
* gcc.target/risc
the
Ztso extension or add it to an existing -march.
Signed-off-by: Patrick O'Neill
---
Before committing v1, I ran the full testsuite as a sanity check and found
failures that don't happen when running the testcases individually. v2 fixes
those failures using common-sense fixes.
:
* config/riscv/sync.md: Use riscv_subword_address function to
calculate the address and shift in atomic_test_and_set.
Signed-off-by: Patrick O'Neill
---
Tested using r14-5040-g5dc2ba333f8.
This patch causes this codegen to regress (adds a mv) but *only* on -O0.
extern void abort();
sh
Hi Juzhe,
The pre-commit CI is seeing these new failures after applying this patch
[1]:
|FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/mask_strided_load-1.c
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_LOAD" 132 FAIL:
gcc.target/riscv/rvv/autovec/gather-scatter/mask_strided_store-1
:
* config/riscv/sync.md: Use riscv_subword_address function to
calculate the address and shift in atomic_test_and_set.
Signed-off-by: Patrick O'Neill
---
Changelog:
v2: Comment out the diff in the foreword so git doesn't get confused
when applying the patch
---
Tested using r14-5040-g5
ior.
Oh, its a regression. I can add a Fixes: tag
OK once CI finishes without regressions.
Thx,
-Vineet
It passes precommit CI without any new failures:
https://github.com/ewlu/gcc-precommit-ci/issues/526#issuecomment-1787891174
Tested-by: Patrick O'Neill
Thanks,
Patrick
On 11/1/23 12:03, Jeff Law wrote:
On 10/31/23 17:25, Patrick O'Neill wrote:
This patch transitions the ztso testcases to use the testsuite
infrastructure,
enabling the tests on both rv64 and rv32 targets.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-ztso-amo-ad
On 11/1/23 12:00, Jeff Law wrote:
On 11/1/23 10:14, Patrick O'Neill wrote:
Other subword atomic patterns use riscv_subword_address to calculate
the aligned address, shift amount, mask and !mask. atomic_test_and_set
was implemented before the common function was added. After this patc
: Ditto.
Signed-off-by: Patrick O'Neill
---
Tested using rv64gc & rv64gcv to make sure the testcases compile/run
as expected.
These files haven't been changed in a long time so I'm not sure why (or
if) this hasn't been run into by other people before.
---
gcc/testsuite/gfort
Hi Pan,
This patch is causing new failures (ICEs) on trunk:
https://github.com/patrick-rivos/gcc-postcommit-ci/issues/110
Pre-commit CI run:
https://github.com/ewlu/gcc-precommit-ci/issues/553#issuecomment-1790688172
New rv32gcv failures:
|FAIL: gcc.dg/vect/fast-math-bb-slp-call-2.c (internal
(while still running the tests on vector targets).
gcc/testsuite/ChangeLog:
* g++.dg/vect/pr102788.cc: Remove dg-do run directive.
Signed-off-by: Patrick O'Neill
---
Tested using rv64gc & rv64gcv to make sure the testcases compile/run
as expected.
Similar to
https://inbox.sourc
d the case
where the testcase is invoked with dg-do compile.
gcc/testsuite/ChangeLog:
* g++.dg/vect/pr95401.cc: Add require-effective-target vect_int.
Signed-off-by: Patrick O'Neill
---
Tested using rv64gc & rv64gcv to make sure the testcase runs/doesn't
compile as expected
On 5/15/23 21:32, Jeff Law wrote:
On 5/9/23 10:01, Patrick O'Neill wrote:
Ping.
OK for backporting. Sorry for the delay.
jeff
Committed.
Thanks,
Patrick
On 5/16/23 19:47, Palmer Dabbelt wrote:
On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote:
On 5/16/23 19:21, Kito Cheng wrote:
Palmer:
For short-term, this should help your internal test:
https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233
That only helps if using blee
patch enforces SEQ_CST by setting the .aqrl bits on the LR and SC
ops.
2022-03-07 Patrick O'Neill
PR target/104831
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.aqrl pair.
Signed-off-by: Patrick O'Neill
---
RISCV LRSC-BUGFIX
{
0:
ts (1:x7=1 /\ 1:x5=0 /\ b=1)
This patch enforces SEQ_CST by setting the .aqrl bits on the LR and .rl
bits on SC ops.
2022-03-07 Patrick O'Neill
PR target/104831
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.rl pair.
Signed-off-by: Patri
concerned that this addition may
restrict subsequent RTL pass optimizations.
2. Are there other concerns with implementing source-dest constraints
within the combine pass?
3. Any other thoughts/input you have is welcome!
2022-03-10 Patrick O'Neill
* combine.cc: Add register equalit
concerned that this addition may
restrict subsequent RTL pass optimizations.
2. Are there other concerns with implementing source-dest constraints
within the combine pass?
3. Any other thoughts/input you have is welcome!
2022-03-10 Patrick O'Neill
* combine.cc: Add register equalit
-atomics command line flags.
gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
This will need to stay for backwards compatibility and the
-mno-inline-atomics flag.
2022-02-15 Patrick O'Neill
PR target/104338
* riscv.opt: Add command-line
ing.
Note: LLVM implements fence rw,w + sw
https://godbolt.org/z/n68P7ne1W
That means that LLVM isn't compatible with libatomic's LR.aq/SC.rl.
* PR target/89835: The RISC-V target uses amoswap.w for relaxed stores
Patrick O'Neill (7):
RISCV: Enforce Libatomic LR/SC SEQ_CST
RISC
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2022-03-31 Patrick O'Neill
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.rl pair.
Signed-off-by: Patrick O'Neill
---
libgcc/co
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with strong SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2022-03-31 Patrick O'Neill
* sync.md: Change LR.aq/SC.rl pairs into sequentially
consistent LR
This patch sets the relevant .rl bits on amo operations.
2022-03-31 Patrick O'Neill
* riscv.cc (riscv_print_operand): change behavior of %A to
include release bits.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 7 ++-
1 file changed, 6 insert
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings amo ops in line with table A.6 of the ISA manual.
2022-03-31 Patrick O'Neill
* riscv.cc (riscv_memmodel_needs_amo_acquire): C
of
both given models.
This change brings LR/SC ops in line with table A.6 of the ISA manual.
2022-03-31 Patrick O'Neill
* riscv.cc: Add functions to get the parent of two
memmodels in sync.md.
* riscv-protos.h: Likewise.
* sync.md (atomic_cas_value_s
This change brings atomic stores in line with table A.6 of the ISA
manual.
2022-03-31 Patrick O'Neill
PR target/89835
* riscv.cc (atomic_cas_value_strong): Add %I flag for
atomic store fences.
* sync.md (atomic_store): Use simple store instructi
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2022-03-31 Patrick O'Neill
* riscv.cc: Expose helper functions to sync.md.
* riscv-protos.h: Likewise.
* sync.md (mem_thread_fe
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