in JuZhe’s patch set into this patch set?
Michael Collison 於 2023年5月5日 週五，23:47寫道：
This series of patches adds foundational support for RISC-V
auto-vectorization support. These patches are based on the current
upstream rvv vector intrinsic support and is not a new
implementation
Richard,
Can you submit this patch for me while I sort out git write access?
On 11/18/22 07:57, Richard Biener wrote:
On Fri, Nov 11, 2022 at 3:28 AM Michael Collison wrote:
This patches transforms ((x & 0x1) == 0) ? y : z y -into
(-(typeof(y))(x & 0x1) & z) y, where op i
2023-03-02 Michael Collison
Juzhe Zhong
* config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
Remove static declaration to to make externally visible.
(get_mask_policy_for_pred): Ditto.
* config/riscv/riscv-vector-builtins.h
he code
Kevin Lee (2):
This patch adds a guard for VNx1 vectors that are present in ports
like riscv.
This patch supports 8 bit auto-vectorization in riscv.
Michael Collison (8):
RISC-V: Add new predicates and function prototypes
RISC-V: autovec: Export policy functions to global scope
2023-03-02 Michael Collison
Juzhe Zhong
* config/riscv/riscv-protos.h (riscv_classify_vlmul_field):
New external declaration.
(riscv_vector_preferred_simd_mode): Ditto.
(riscv_tuple_mode_p): Ditto.
(riscv_vector_mask_mode_p): Ditto
2023-03-02 Michael Collison
Juzhe Zhong
* config/riscv/riscv.cc (riscv_option_override):
Set riscv_vectorization_factor.
(riscv_estimated_poly_value): Implement
TARGET_ESTIMATED_POLY_VALUE.
(riscv_preferred_simd_mode): Implement
2023-03-02 Michael Collison
Juzhe Zhong
* config/riscv/riscv-v.cc (riscv_classify_vlmul_field):
New function.
(riscv_vector_preferred_simd_mode): Ditto.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto
2023-03-02 Michael Collison
Juzhe Zhong
* config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include
vector-iterators.md.
* config/riscv/vector-auto.md: New file containing
autovectorization patterns.
* config/riscv/vector
2023-03-02 Michael Collison
Vineet Gupta
* gcc.target/riscv/rvv/autovec: New directory
for autovectorization tests.
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New
test to verify code generation of vector add on rv32.
* gcc.target/riscv
From: Kevin Lee
Kevin Lee
gcc/ChangeLog:
* tree-vect-data-refs.cc (vect_grouped_store_supported): Add new
condition
---
gcc/tree-vect-data-refs.cc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc
index 8daf7bd7dd3..df393ba723
-gnu. Okay?
2023-03-09 Michael Collison
* tree-vect-slp.cc (can_duplicate_and_interleave_p):
Check that GET_MODE_NUNITS is a multiple of 2.
---
gcc/tree-vect-slp.cc | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect
2023-04-05 Michael Collison
* gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New
test to verify code generation of vector "and" on rv32.
* gcc.target/riscv/rvv/autovec/loop-and.c: New
test to verify code generation of vector "and" on rv64.
From: Kevin Lee
2023-04-14 Kevin Lee
gcc/testsuite/ChangeLog:
* config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add
new vector mode
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit
type
* gcc.target/riscv/rvv/autovec/loop-add.c: Ditto
* gcc.
Ping. Original patch posted here:
https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00091.html
Ping ^2. Updated patch posted here:
https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01615.html
Michael Collison
PR target/70119
* config/aarch64/aarch64.md (*aarch64__reg_3_mask1):
New pattern.
(*aarch64_reg_3_neg_mask2): New pattern.
(*aarch64_reg_3_minus_mask): New pattern.
(*aarch64__reg_di3_mask2): New pattern.
* config/aarch64
w generate:
foo:
moviv1.4h, 0x8
moviv0.4s, 0
ins v0.d[1], v1.d[0]
ret
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk.
2017-06-15 Michael Collison
* config/aarch64/aarch64-simd.md(aarch64_combine_internal):
Co
Updated the patch per Richard's suggestions to allow scheduling of instructions
before reload.
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2017-05-22 Kyrylo Tkachov
Michael Collison
PR target/70119
* config/aarch64/aarch
Richard,
I reworked the patch and retested on big endian as well as little. The original
code was performing two swaps in the big endian case which works out to no
swaps at all.
I also updated the ChangeLog per your comments. Okay for trunk?
2017-06-19 Michael Collison
* config
Fixed the "nitpick" issues pointed out by James. Okay for trunk?
2017-05-22 Kyrylo Tkachov
Michael Collison
PR target/70119
* config/aarch64/aarch64.md (*aarch64__reg_3_mask1):
New pattern.
(*aarch64_reg_3_neg_mask2): N
This patch cleans up warning messages due to unused variables and overly
complicated loop structures.
Okay for trunk?
2017-03-30 Michael Collison
PR target/68535
* config/arm/arm.c (gen_ldm_seq): Remove last unnecessary
set of base_reg
(arm_gen_movmemqi
Hi Eric,
The warnings are listed in the PR here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68535
Regards,
Michael Collison
-Original Message-
From: Eric Gallager [mailto:eg...@gwmail.gwu.edu]
Sent: Friday, June 23, 2017 2:37 PM
To: Michael Collison
Cc: GCC Patches ; nd
Subject
Richard,
I reworked the patch using an assert as you suggested. Bootstrapped and
retested. Okay for trunk?
-Original Message-
From: Richard Earnshaw (lists) [mailto:richard.earns...@arm.com]
Sent: Friday, June 23, 2017 2:09 AM
To: Michael Collison ; GCC Patches
Cc: nd
Subject: Re
Ping ^3. Updated patch posted here:
https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01615.html
Ping^2. Original patch posted here:
https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00091.html
Okay I will take a look at this.
Michael Collison
> On Jun 30, 2017, at 11:04 AM, Andreas Schwab wrote:
>
>> On Jun 23 2017, Michael Collison wrote:
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c
>> b/gcc/testsuite/gcc.target/aarch64/
, CC_Vmode is introduced.
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2017-10-26 Michael Collison
Richard Henderson
* config/aarch64/aarch64-modes.def (CC_V): New.
* config/aarch64/aarch64-protos.h
(aarch64_add_128bit_scratch_regs): Declare
for patch here:
https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01512.html
This patch contains new patterns for addv overflow patterns.
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2017-10-26 Michael Collison
Richard Henderson
* config/aarch64/aarch64.md
for patch here:
This patch contains new patterns for subv overflow patterns.
https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01512.html
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2017-10-26 Michael Collison
Richard Henderson
* config/aarch64/aarch64.md
for patch here:
https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01512.html
This patch contains new test cases to verify that the new overflow patterns are
being utilized.
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2017-10-26 Michael Collison
Richard Henderson
Hi Jeff,
No longer needed. Jakub's patch does the job.
Michael Collison
> On Nov 19, 2017, at 3:50 PM, Jeff Law wrote:
>
>> On 10/25/2017 11:54 PM, Michael Collison wrote:
>> Ping. Original patch posted here:
>>
>> https://gcc.gnu.org/ml/gcc-patches/20
Hello,
The ARMv8.4-A architecture builds on ARMv8.3-A and includes optional
cryptographic extensions supporting SHA512, SHA3, SM3 and SM4. New FP16
multiply add/subtract instructions have been added that are mandatory in
ARMv8.4-A and optional from ARMv8.2-A onward.
Although the new cryptogr
verified all
instructions assembly correctly.
2017-11-10 Michael Collison
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
(__ARM_FEATURE_AES): Define if TARGET_AES is true.
(__ARM_FEATURE_SHA2): Define if TARGET_SHA2 is true.
* config/aarch64
Hi all,
This patch adds support for the Arm architecture v8.4. A new command line
option, -march=armv8.4-a, is added as well as documentation.
Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all
instructions assembly correctly.
2017-11-10 Michael Collison
Intrinsics generate the
appropriate SM3/SM4 assembly instructions.
Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all
instructions assembly correctly.
Okay for trunk?
2017-11-10 Michael Collison
* config/aarch64/aarch64-builtins.c
Intrinsics generate the
appropriate SHA-512/SHA-3 assembly instructions.
Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all
instructions assembly correctly.
Okay for trunk?
2017-11-10 Michael Collison
* config/aarch64/aarch64-builtins.c
.
Test cases were added to verify that the ACLE Intrinsics generate the
appropriate FP16 multiply add/subtract assembly instructions.
Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all
instructions assembly correctly.
Okay for trunk?
2017-11-10 Michael Collison
CC_Vmode is introduced.
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2018-05-31 Michael Collison
Richard Henderson
* config/aarch64/aarch64-modes.def (CC_V): New.
* config/aarch64/aarch64-protos.h
(aarch64_add_128bit_scratch_regs): Declare
(aarch64_subv_128bit_scratch_regs
for patch here:
https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01512.html
This patch contains new patterns for addv overflow patterns.
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2018-05-31 Michael Collison
Richard Henderson
* config/aarch64/aarch64.md
for patch here:
https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01512.html
This patch contains new patterns for subv overflow patterns.
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2018-05-31 Michael Collison
Richard Henderson
* config/aarch64/aarch64.md
for patch here:
https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01512.html
This patch contains new test cases to verify that the new overflow patterns are
being utilized.
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2018-05-31 Michael Collison
Richard Henderson
x27; aarch64_gen_unlikely_cbranch'.
Okay for trunk?
-Original Message-
From: James Greenhalgh
Sent: Thursday, June 7, 2018 5:19 PM
To: Michael Collison
Cc: GCC Patches ; nd
Subject: Re: [PATCH][Aarch64] v2: Arithmetic overflow common functions [Patch
1/4]
On Wed, Jun 06, 2018 at 1
All requested changes made:
- label_ref added as operand 3
- more meaningful names given to variables
Okay for trunk?
-Original Message-
From: James Greenhalgh
Sent: Thursday, June 7, 2018 5:29 PM
To: Michael Collison
Cc: GCC Patches ; nd
Subject: Re: [PATCH][Aarch64] v2: Arithmetic
All requested changes made:
- label_ref added as operand 3
- more descriptive variable names used
Okay for trunk?
-Original Message-
From: James Greenhalgh
Sent: Thursday, June 7, 2018 5:30 PM
To: Michael Collison
Cc: GCC Patches ; nd
Subject: Re: [PATCH][Aarch64] v2: Arithmetic
Updated with Richard's style and mismatched mode comments.
Okay for trunk?
-Original Message-
From: Richard Sandiford
Sent: Monday, June 11, 2018 11:47 AM
To: Michael Collison
Cc: James Greenhalgh ; GCC Patches
; nd
Subject: Re: [PATCH][Aarch64] v2: Arithmetic overflow addv pat
-31 Michael Collison
Richard Henderson
* config/aarch64/aarch64.md (subv4, usubv4): New patterns.
(subti): Handle op1 zero.
(subvti4, usub4ti4): New.
(*sub3_compare1_imm): New.
(sub3_carryinCV): New.
(*sub3_carryinCV_z1_z2
conditional
statement changed from TARGET_CRYPTO to TARGET_AES.
-Original Message-
From: James Greenhalgh [mailto:james.greenha...@arm.com]
Sent: Tuesday, January 9, 2018 10:44 AM
To: Michael Collison
Cc: GCC Patches ; nd
Subject: Re: [PATCH 1/5][AArch64] Crypto command line split
On Wed
Patch updated per Richard's comments. Ok for trunk?
-Original Message-
From: Richard Sandiford [mailto:richard.sandif...@linaro.org]
Sent: Thursday, January 4, 2018 8:02 AM
To: Michael Collison
Cc: GCC Patches ; nd
Subject: Re: [PATCH 5/5][AArch64] fp16fml support
Hi Michael,
Okay will put on my to-do list for post GCC 8.
-Original Message-
From: James Greenhalgh [mailto:james.greenha...@arm.com]
Sent: Wednesday, January 10, 2018 12:21 PM
To: Michael Collison
Cc: Richard Sandiford ; GCC Patches
; nd
Subject: Re: [PATCH 5/5][AArch64] fp16fml support
On Tue
ict_it". This was causing illegal rtl
to be generated for IT blocks which in turn caused an internal error.
Bootstrapped and regression tested on arm-linux-gnueabihf. Okay for trunk?
2018-01-28 Michael Collison
* config/arm/thumb2.md:
(*thumb2_mov_negscc
one
instruction at -O2
f7:
fcvtzu x0, d0
ret
Bootstrapped and regression tested on aarch64-linux-gnu. Okay for trunk?
2018-05-15 Michael Collison
* config/aarch64/aarch64.md:
(*fix_to_zero_extenddfdi2): New pattern.
* gcc.target/aarch64
, s0
ret
We can merge the float_truncate into the fix at the rtl level
With -ffast-math enabled and -O2 we can now generate:
f6:
fcvtzs w0, d0
ret
Bootstrapped and regression tested on aarch64-linux-gnu. Okay for trunk?
2018-05-15 Michael Collison
The CLZ_DEFINED_VALUE_AT_ZERO macro is harded to return 32. For the
vector intrinsic vclz this is incorrect and should return the value
eight. The CTZ_DEFINED_VALUE_AT_ZERO has the same issue.
Tested on arm-linux-gnueabihf, arm-linux-gnueabi.
2014-10-08 Michael Collison
* config/arm
Yes this problem was found with Christophe's neon intrinsic tests which
are awaiting approval. The problem was found by passing a value of zero
to the vclz vector intrinsic.
On 10/09/2014 12:11 AM, Andrew Pinski wrote:
On Thu, Oct 9, 2014 at 12:05 AM, Michael Collison
wrote:
Tejas,
You are correct. I will update the comment.
On 10/9/2014 12:55 AM, Tejas Belagod wrote:
On 09/10/14 08:05, Michael Collison wrote:
The CLZ_DEFINED_VALUE_AT_ZERO macro is harded to return 32. For the
vector intrinsic vclz this is incorrect and should return the value
eight. The
.
2014-10-08 Michael Collison
* config/arm/arm.h (CLZ_DEFINED_VALUE_AT_ZERO) : Update
to support vector modes
(CTZ_DEFINED_VALUE_AT_ZERO): Ditto
On 10/09/2014 12:55 AM, Tejas Belagod wrote:
On 09/10/14 08:05, Michael Collison wrote:
The CLZ_DEFINED_VALUE_AT_ZERO macro is
the flattening I had to add new include files to gengtype.c.
I performed a full bootstrap with all languages on x86-linux. I also
bootstrapped on all targets listed in contrib/config-list.mk with c and
c++ enabled.
Is this okay for trunk?
2014-11-19 Michael Collison
* gengtype.c
a full bootstrap with all languages on x86-linux. I also
bootstrapped on all targets listed in contrib/config-list.mk with c and
c++ enabled.
Is this okay for trunk?
2014-11-19 Michael Collison
* builtins.c: Remove include of lto-streamer.h.
Include plugin-api.h and gcov-io.h
arm-linux-gnueabi, arm-linux-gnueabihf,
armeb-linux-gnueabihf. Okay for trunk?
2015-06-24 Michael Collison
* gcc/config/arm/arm.md (*arm_smin_cmp): New pattern.
(*arm_umin_cmp): Likewise.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 1ac8af0..994c95f 100644
--- a/g
, r0
ble .L2
.L3:
mov r3, #1
b .L2
With the patch this now generates:
addsr0, r0, r1
movvs r3, #1
movvc r3, #0
str r3, [r2]
bx lr
Ok for trunk?
2016-07-27 Michael Collison
Michael Coll
Patch updated with all comments from James.
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2017-10-15 Michael Collison
* config/aarch64/aarch64.md(_trunc>2):
New pattern.
(_trunchf2: New pattern.
(_trunc2: New pattern.
* config/aarc
; GCC Patches ; Michael
Collison ; Segher Boessenkool
; Kyrill Tkachov ; nd
Subject: Re: [PATCH][compare-elim] Merge zero-comparisons with normal ops
On Sat, Oct 14, 2017 at 10:39 AM, Eric Botcazou wrote:
>> This looks good. OK for the trunk.
>
> FWIW I disagree. The patch complete
Are we in agreement that I should revert the patch?
-Original Message-
From: Richard Biener [mailto:richard.guent...@gmail.com]
Sent: Tuesday, October 17, 2017 1:10 PM
To: Michael Collison ; Eric Botcazou
Cc: Jeff Law ; GCC Patches ; Segher
Boessenkool ; Kyrill Tkachov
; nd
Subject
This patch fixes an ICE on x86 because we were not constraining the operands
of a recognized insn. Bootstrapped and tested on aarch64-none-linux-gnu and
x86_64.
Also successfully compiled the failing test cases in 82597 and duplicate 82592.
Ok for trunk?
2017-10-18 Michael Collison
to be an integer
register. With my patch the destination can be an integer or fp register.
I fixed the failures and bootstrapped and tested on aarch64-linux-gnu. Okay for
trunk?
2017-09-02 Michael Collison
* config/aarch64/aarch64.md(_trunc>2):
New pattern.
(_trunc
Ping. Original patch posted here:
https://gcc.gnu.org/ml/gcc-patches/2017-10/msg01317.html
NetBSD/Arm requires that DEFAULT_STRUCTURE_SIZE_BOUNDARY (see
config/arm/netbsd-elf.h for details). This patch disallows
-mstructure-size-boundary on netbsd if the value is not equal to the
DEFAULT_STRUCTURE_SIZE_BOUNDARY.
Okay for trunk?
2017-07-05 Michael Collison
* config/arm
when I added the overflow
operations there as well. Additionally other targets seem to use the comparison
operators this way (i386 for the umulv).
Regards,
Michael Collison
-Original Message-
From: Richard Earnshaw (lists) [mailto:richard.earns...@arm.com]
Sent: Wednesday, July 5, 2017 2:3
Ping^3. Original patch posted here:
https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00091.html
James,
The subtract instruction only reliably sets the N and Z flags. We convey this
information in aarch64_seelct_cc_mode.
Regards,
Michael Collison
-Original Message-
From: James Greenhalgh [mailto:james.greenha...@arm.com]
Sent: Monday, July 10, 2017 10:12 AM
To: Michael Collison
Updated per Richard's comments and suggestions.
Okay for trunk?
2017-07-10 Michael Collison
* config/arm/arm.c (arm_option_override): Deprecate
use of -mstructure-size-boundary.
* config/arm/arm.opt: Deprecate -mstructure-size-boundary.
* doc/invoke
37 mt(1729);
std::uniform_int_distribution dist(0,1008);
for (int i = 0; i < 16; ++i)
{
std::cout << dist(mt) << " ";
}
}
Okay for trunk?
2017-07-16 Michael Collison <mailto:michael.colli...@arm.com>
Add optimized implementation of mers
No particular reason; I can merge it into one preprocessor line.
-Original Message-
From: drep...@gmail.com [mailto:drep...@gmail.com] On Behalf Of Ulrich Drepper
Sent: Tuesday, July 18, 2017 12:24 AM
To: Michael Collison
Cc: GCC Patches ; nd
Subject: Re: PATCH v2][Aarch64] Add
Ping. Updated patch posted here:
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00723.html
I took his "okay" as an approval since he is listed as a maintainer.
-Original Message-
From: Jonathan Wakely [mailto:jwak...@redhat.com]
Sent: Tuesday, July 25, 2017 10:37 AM
To: Michael Collison
Cc: gcc-patches@gcc.gnu.org; libstd...@gcc.gnu.org; nd
Subject: Re: [PATCH v
comparison. The mode of the
compare then indicates what might or might not be valid in the way the
comparison is finally constructed."
Okay for trunk?
2017-08-01 Michael Collison
Richard Henderson
* config/aarch64/aarch64-modes.def (CC_V): New.
* config/
e-size-boundary'
Okay for trunk?
2017-08-04 Michael Collison
* testsuite/g++.dg/ext/packed8.C: Skip test for arm_eabi.
* testsuite/g++.dg/init/array16.C: Skip test for arm_eabi.
* testsuite/g++.dg/other/crash-4.C: Skip test for arm_eabi.
* testsuite/gcc.dg/bu
.size f1, .-f1
.align 2
.p2align 3,,7
.global f2
.type f2, %function
f2:
neg w2, w1
lsl w0, w0, w2
ret
Okay for trunk?
2017-08-07 Michael Collison
* config/aarch64/aarch64.md (*aarch64_reg__minus3):
New patte
, 2017 2:02 PM
To: pins...@gmail.com
Cc: gcc-patches@gcc.gnu.org; Michael Collison ; nd
Subject: Re: [PATCH] [Aarch64] Optimize subtract in shift counts
> That is simplify:
> (SHIFT A (32 - B)) -> (SHIFT A (AND (NEG B) 31)) etc.
I think you need SHIFT_COUNT_TRUNCATED to be true for t
Richard,
The pattern will only be matched if the value is positive. More specifically if
the constant value is 32 (SImode) or 64 (DImode).
-Original Message-
From: Richard Kenner [mailto:ken...@vlsi1.ultra.nyu.edu]
Sent: Monday, August 7, 2017 6:56 PM
To: Michael Collison
Cc: gcc
This case is covered by Wilco's previous reply:
https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00575.html
-Original Message-
From: Richard Kenner [mailto:ken...@vlsi1.ultra.nyu.edu]
Sent: Tuesday, August 8, 2017 5:13 AM
To: Michael Collison
Cc: gcc-patches@gcc.gnu.org; nd ;
.ultra.nyu.edu]
Sent: Tuesday, August 8, 2017 12:52 PM
To: Michael Collison
Cc: gcc-patches@gcc.gnu.org; nd ; pins...@gmail.com
Subject: RE: [PATCH] [Aarch64] Optimize subtract in shift counts
> This case is covered by Wilco's previous reply:
>
> https://gcc.gnu.org/ml/gcc-patches/2017-08
: Michael Collison
Cc: gcc-patches@gcc.gnu.org; nd ; pins...@gmail.com
Subject: RE: [PATCH] [Aarch64] Optimize subtract in shift counts
> Because for integer shift instructions the shift count is truncated.
> We ensure that we only use integer shift instructions by emitting a
> shift with a m
Correct.
-Original Message-
From: Richard Kenner [mailto:ken...@vlsi1.ultra.nyu.edu]
Sent: Tuesday, August 8, 2017 1:20 PM
To: Michael Collison
Cc: gcc-patches@gcc.gnu.org; nd ; pins...@gmail.com
Subject: RE: [PATCH] [Aarch64] Optimize subtract in shift counts
> Correct. It
ary=8 option why was it added
in the first place?
-Original Message-
From: Richard Earnshaw (lists) [mailto:richard.earns...@arm.com]
Sent: Monday, August 7, 2017 5:32 AM
To: Michael Collison ; gcc-patches@gcc.gnu.org
Cc: nd
Subject: Re: [PATCH][Arm] Test suite failures resulting from deprec
Patch updated to remove -mstructure-size-boundary from tests based on comments
from Richard. Outdated comments also removed.
Okay for trunk?
2017-08-01 Michael Collison
* testsuite/g++.dg/ext/packed8.C: Remove -mstructure-size boundary
option and fix comment
This simple technique allows us to catch cases such as this example.
Bootstrapped and tested on arm-none-linux-gnueabihf, aarch64-none-linux-gnu and
x86_64.
Ok for trunk?
2017-08-05 Kyrylo Tkachov
Michael Collison
* compare-elim.c: Include emit-rtl.h.
(can
, August 14, 2017 1:27 AM
To: Richard Kenner
Cc: Michael Collison ; GCC Patches
; nd ; Andrew Pinski
Subject: Re: [PATCH] [Aarch64] Optimize subtract in shift counts
On Tue, Aug 8, 2017 at 10:20 PM, Richard Kenner
wrote:
>> Correct. It is truncated for integer shift, but not simd
Ping. Original patch:
https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00544.html
Ping. Original patch here:
https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00766.html
chard Biener
Cc: Richard Kenner ; Michael Collison
; GCC Patches ; nd
; Andrew Pinski
Subject: Re: [PATCH] [Aarch64] Optimize subtract in shift counts
Richard Biener writes:
> On Tue, Aug 22, 2017 at 9:29 AM, Richard Sandiford
> wrote:
>> Richard Biener writes:
>>> On Augu
, September 6, 2017 11:32 AM
To: Michael Collison
Cc: Richard Biener ; Richard Kenner
; GCC Patches ; nd
; Andrew Pinski
Subject: Re: [PATCH] [Aarch64] Optimize subtract in shift counts
Michael Collison writes:
> Richard Sandiford do you have any objections to the patch as it stands?
> It d
Patch updated with all relevant comments and suggestions.
Bootstrapped and tested on arm-none-linux-gnueabihf, and aarch64-none-linux-gnu
and x86_64.
Ok for trunk?
2017-08-05 Kyrylo Tkachov
Michael Collison
* compare-elim.c: Include emit-rtl.h
scalar instructions and eliminate the two FP
<-> integer register transfes.
f1:
fcvtzs s0, s0
scvtf s0, s0
ret
Bootstrapped and tested on aarch64-linux-gnu. Okay for trunk?
2017-09-02 Michael Collison
* config/aarch64/aarch64.md(_trunc>2):
lsl x0, x1, x0
ret
Okay for trunk?
2017-05-17 Kyrylo Tkachov
Michael Collison
PR target/70119
* config/aarch64/aarch64.md (*aarch64__reg_3_mask1):
New pattern.
(*aarch64_reg_3_neg_mask2): New pattern.
(*aarch64_reg_3_minu
5-17 Michael Collison
Richard Henderson
* config/aarch64/aarch64-modes.def (CC_V): New.
* config/aarch64/aarch64-protos.h
(aarch64_add_128bit_scratch_regs): Declare
(aarch64_add_128bit_scratch_regs): Declare.
(aarch64_expand_subvti): Dec
o.org]
Sent: Friday, May 19, 2017 3:59 AM
To: Michael Collison
Cc: gcc-patches@gcc.gnu.org; nd
Subject: Re: [PATCH][Aarch64] Add support for overflow add and sub operations
Hi Michael,
On 19 May 2017 at 07:12, Michael Collison wrote:
> Hi,
>
> This patch improves code generations fo
ig/aarch64/aarch64.c (aarch64_rtx_costs): Account for cost
of shift when the shift amount is masked with constant equal to
the size of the mode.
* config/aarch64/predicates.md (subreg_lowpart_operator): New
predicate.
2016-05-22 Kyrylo Tkachov
Michael C
Ping. Testsuite issue resolved. Okay for trunk?
-Original Message-
From: Christophe Lyon [mailto:christophe.l...@linaro.org]
Sent: Friday, May 19, 2017 3:59 AM
To: Michael Collison
Cc: gcc-patches@gcc.gnu.org; nd
Subject: Re: [PATCH][Aarch64] Add support for overflow add and sub
#include
#include
int
main()
{
__gnu_cxx::sfmt19937 mt(1729);
std::uniform_int_distribution dist(0,1008);
for (int i = 0; i < 16; ++i)
{
std::cout << dist(mt) << " ";
}
}
2017-06-01 Michael Collison
Add optimized implementat
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