The old stack stack was performed before the stack was dropped,
which would cause the detection tool to report a memory leak.
The current stack check scheme is as follows:
'-fstack-clash-protection':
1. When the frame->total_size is smaller than the guard page size,
the stack is dropped accord
After several considerations, I decided to set VTV_PAGE_SIZE to 16KB under
loongarch64.
v1 - > v2:
1. When the macro __loongarch_lp64 is defined, the VTV_PAGE_SIZE is set to 64K.
2. In the vtv_malloc.cc file __vtv_malloc_init function, it does not check
whether VTV_PAGE_SIZE is equal to the
v1 - > v2:
1. When the macro __loongarch_lp64 is defined, the VTV_PAGE_SIZE is set to 64K.
2. In the vtv_malloc.cc file __vtv_malloc_init function, it does not check
whether VTV_PAGE_SIZE is equal to the system page size, if the macro
__loongarch_lp64 is defined.
v2 -> v3:
Set VTV_PAGE_SIZ
.html)
2. Add prefetch insns.
*** BLURB HERE ***
Lulu Cheng (2):
LoongArch: Optimize immediate load.
LoongArch: Add prefetch insns.
gcc/config/loongarch/constraints.md | 7 +-
gcc/config/loongarch/loongarch-def.c | 2 +
gcc/config/loongarch/loongarch-protos.h | 1
Co-Authored-By: xujiahao
gcc/ChangeLog:
* config/loongarch/loongarch-def.c: Initial number of parallel prefetch.
* config/loongarch/loongarch-protos.h (loongarch_prefetch_cookie):
Function declaration.
* config/loongarch/loongarch-tune.h (struct loongarch_cache):
Fixed an issue where the compiler would not take four 64-bit immediate
load instructions out of the loop.
gcc/ChangeLog:
* config/loongarch/constraints.md (x): New constraint.
* config/loongarch/loongarch.cc (struct loongarch_integer_op):
Define a new member curr_value, th
Sorry for the problem in this patch. I will send it again after
modification.
在 2022/10/29 下午3:05, Lulu Cheng 写道:
Co-Authored-By: xujiahao
gcc/ChangeLog:
* config/loongarch/loongarch-def.c: Initial number of parallel prefetch.
* config/loongarch/loongarch-protos.h
Pushed to r13-3571.
在 2022/10/29 下午2:53, Lulu Cheng 写道:
v1 - > v2:
1. When the macro __loongarch_lp64 is defined, the VTV_PAGE_SIZE is set to 64K.
2. In the vtv_malloc.cc file __vtv_malloc_init function, it does not check
whether VTV_PAGE_SIZE is equal to the system page size, if the ma
v1 -> v2:
1. Change the code format.
2. Fix bugs in the code.
Both regression tests and spec2006 passed.
The problem mentioned in the link does not move the four immediate load
instructions out of the loop. It has been optimized. Now, as in the test case,
four immediate load instructions are gene
在 2022/11/1 下午4:02, Xi Ruoyao 写道:
On Tue, 2022-11-01 at 14:19 +0800, Lulu Cheng wrote:
+;; Load immediate to the 32-63 bits of the source register.
+(define_insn_and_split "load_hi32"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (ior:DI
+
v1 -> v2:
1. Change the code format.
2. Fix bugs in the code.
v2 -> v3:
Modifying a code implementation of an undefined behavior.
Both regression tests and spec2006 passed.
The problem mentioned in the link does not move the four immediate load
instructions out of the loop. It has been optimized
Looks good to me.
在 2022/8/16 下午4:08, Xi Ruoyao 写道:
A simple optimization. Ok for trunk?
-- >8 --
We already had smin/smax RTL pattern using fmin/fmax instruction. But
for smin/smax, it's unspecified what will happen if either operand is
NaN. So we would generate calls to libc fmin/fmax fu
2022/8/11 下午7:35, Lulu Cheng 写道:
thread.c:
__attribute__ ((tls_model ("global-dynamic"))) __thread int a;
void
test (void)
{
a = 10;
}
Compile the tests with -fno-plt, error message is as follows:
thread.c: In function 'test':
thread.c:7:1: error: unrecog
在 2022/8/18 上午10:56, Hans-Peter Nilsson 写道:
On Mon, 15 Aug 2022, Xi Ruoyao via Gcc-patches wrote:
Can we make a final solution to this soon? Now the merge window of
Linux 6.0 is closed and we have two Linux kernel releases not possible
to be built with Binutils or GCC with new relocation typ
Use five instructions to calculate a signed 64-bit offset relative to the pc.
gcc/ChangeLog:
* config/loongarch/loongarch-opts.cc: Allow cmodel to be extreme.
* config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
Add extreme support for TLS GD and LD types.
在 2022/8/18 下午7:37, Xi Ruoyao 写道:
+ if (opts->x_flag_plt)
+ error ("code model %qs and %qs not support %s mode",
+"tiny-static", "extreme", "plt");
I think we can ignore the effect of -fplt if code model is extreme,
instead of forcing everyone to explicitly add -f
在 2022/8/18 下午8:52, Xi Ruoyao 写道:
On Thu, 2022-08-18 at 19:49 +0800, Lulu Cheng wrote:
I think we can ignore the effect of -fplt if code model is extreme,
instead of forcing everyone to explicitly add -fno-plt. The "large"
code model of x86_64 also does not limit the address ra
v1 -> v2:
- Modify some description information.
- Add options -W[no]extreme-plt, warn about code model extreme not support plt
mode,
and then disable plt.
---
Use five instructions to calculate a signed 64-bit offset relative to the pc.
gcc/ChangeLog:
v1 -> v2:
- Modify some description information.
- Add options -W[no]extreme-plt, warn about code model extreme not support plt
mode,
and then disable plt.
v2 -> v3:
- When -mcmodel=extreme, default set to -fno-plt mode, if the user forces to use
'-mcmodel=extreme -fplt', an error will be reporte
v1 -> v2:
- Modify some description information.
- Add options -W[no]extreme-plt, warn about code model extreme not support plt
mode,
and then disable plt.
v2 -> v3:
- When -mcmodel=extreme, default set to -fno-plt mode, if the user forces to use
'-mcmodel=extreme -fplt', an error will be reporte
Pushd to r13-2128.
在 2022/8/20 下午4:39, Lulu Cheng 写道:
v1 -> v2:
- Modify some description information.
- Add options -W[no]extreme-plt, warn about code model extreme not support plt
mode,
and then disable plt.
v2 -> v3:
- When -mcmodel=extreme, default set to -fno-plt mode, if the user
The function jump instruction in normal mode is 'bl',
so the scope of the function jump is +-128MB.
Now we've added support for 'medium' mode, this mode is
to complete the function jump through two instructions:
pcalau12i + jirl
So in this mode the function jump range is increased to +-2GB
在 2022/8/23 下午10:51, Xi Ruoyao 写道:
diff --git a/gcc/config/loongarch/loongarch-protos.h
b/gcc/config/loongarch/loongarch-protos.h
index cadaad7519c..4e925aa3876 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -30,6 +30,12 @@ along with GCC;
Pushed to r13-2165.
在 2022/8/20 下午5:18, Huacai Chen 写道:
Hi, Lulu,
I think there is a typo in your subject line.
Huacai
On Sat, Aug 20, 2022 at 5:05 PM Lulu Cheng wrote:
The function jump instruction in normal mode is 'bl',
so the scope of the function jump is +-128MB.
Now w
在 2022/8/24 下午10:03, Xi Ruoyao 写道:
SYMBOL_REF_TLS_MODEL invokes SYMBOL_REF_FLAGS, and SYMBOL_REF_FLAGS
invokes RTL_FLAG_CHECK1 and aborts when RTL code is not SYMBOL_REF.
r13-1833 removed "gcc_assert (SYMBOL_REF_P (x))" before invoking
"SYMBOL_REF_TLS_MODEL (x)", indicating that it's now possi
在 2022/8/24 下午10:12, Xi Ruoyao 写道:
On Wed, 2022-08-24 at 22:08 +0800, Xi Ruoyao wrote:
v1 -> v2:
* Avoid introduce of SYMBOL_PCREL32, use SYMBOL_PCREL for 32-bit PC
relative.
* Rebase onto a bug fix ([1/2] in the series) to avoid merge conflict.
* Fix missed ChangeLog entries.
Rese
在 2022/8/25 下午7:41, Xi Ruoyao 写道:
On Thu, 2022-08-25 at 17:12 +0800, Xi Ruoyao via Gcc-patches wrote:
On Thu, 2022-08-25 at 16:53 +0800, Lulu Cheng wrote:
I think this should add a sentence:
"Currently, the identifier name can only be one of small or
extreme."
I'll ad
LGTM!
Thanks.
在 2022/8/24 下午10:09, Xi Ruoyao 写道:
If GCC is not built with a working linker for the target (developers
occansionally build such a "minimal" GCC for testing and debugging),
TLS will be emulated and __tls_get_addr won't be used. Refine those
tests depending on __tls_get_addr with
OK!
Thanks!
在 2022/8/31 下午1:54, Xi Ruoyao 写道:
The LoongArch support for libubsan and libasan has been added in:
- https://reviews.llvm.org/D129371
- https://reviews.llvm.org/D129418
and we've merged them in r13-2269. It's time to enable them.
No unexpected failures in GCC asan.exp and ubsan
I think the following modification should be added:
git diff loongarch/predicates.md
+;; Do not use GOT to access external symbols, when define
+;; TARGET_DIRECT_EXTERN_ACCESS.
+
(define_predicate "is_const_call_local_symbol"
(and (match_operand 0 "const_call_insn_operand")
(ior (mat
在 2022/9/4 上午10:51, Xi Ruoyao 写道:
On Sun, 2022-09-04 at 10:26 +0800, Lulu Cheng wrote:
If the above modifications are not added, the function call is:
bl %plt(test1)
now is :
bl test1
Regarding "%plt(...)", in the binutils code:
/* For compatible old asm code. */
在 2022/9/4 下午2:35, Xi Ruoyao 写道:
On Sun, 2022-09-04 at 11:22 +0800, Lulu Cheng wrote:
在 2022/9/4 上午10:51, Xi Ruoyao 写道:
On Sun, 2022-09-04 at 10:26 +0800, Lulu Cheng wrote:
If the above modifications are not added, the function call is:
bl %plt(test1)
now is :
bl test1
LGTM!
Thanks!
在 2022/9/4 下午9:18, Xi Ruoyao 写道:
v1 -> v2:
Move TARGET_DIRECT_EXTERN_ACCESS check from loongarch_classify_symbol to
loongarch_symbol_binds_local_p, so "%plt" is not output if
-mdirect-extern-access used.
-- >8 --
As a new target, LoongArch does not use copy relocation as it's
gcc/ChangeLog:
PR target/106828
* config/loongarch/loongarch.cc (loongarch_asan_shadow_offset): New.
(TARGET_ASAN_SHADOW_OFFSET): New.
gcc/testsuite/ChangeLog:
PR target/106828
* g++.target/loongarch/pr106828.C: New test.
---
gcc/config/loongarch/loongarc
Sorry, asan shadow offset is wrong in v1.
In the file asan_mapping.h line 207:
#define ASAN_SHADOW_OFFSET_CONST 0x4000
So it's should be 1<<46.
gcc/ChangeLog:
PR target/106828
* config/loongarch/loongarch.cc (loongarch
在 2022/9/7 下午4:02, Xi Ruoyao 写道:
On Wed, 2022-09-07 at 15:39 +0800, Lulu Cheng wrote:
Sorry, asan shadow offset is wrong in v1.
In the file asan_mapping.h line 207:
# define ASAN_SHADOW_OFFSET_CONST 0x4000
So it's should be 1<<46.
LGTM. I forgot to i
Sorry, I will correct this typo.
Thanks!
在 2022/9/7 下午5:58, Martin Liška 写道:
On 9/7/22 09:39, Lulu Cheng wrote:
|+ This value is taken from the file libsanitizer/asan/asan_mappint.h. */|
s/asan_mappint.h/asan_mapping.h
Cheers,
Martin
This modification will cause the ABI to change, we are discussing solutions.
And we will give a conclusion at the latest tommorrow.
Thanks!
在 2022/4/25 下午1:57, Xi Ruoyao 写道:
Ping.
Normally we shouldn't ping a patch after only a few days, but we're
running out of time to catch GCC 12 milestone
hink the modification should be below.
if (!TYPE_P (TREE_TYPE (f)))
return -1;
Thanks!
Lulu Cheng
gcc/ChangeLog:
* config/loongarch/loongarch.md: Add '(clobber (mem:BLK (scratch)))'
to PLV instruction templates.
---
gcc/config/loongarch/loongarch.md | 40 +--
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/gcc/config/loongarch/loonga
gcc/ChangeLog:
* config/loongarch/loongarch.md: Add fdiv define_expand template,
then generate floating-point division and floating-point reciprocal
instructions.
---
gcc/config/loongarch/loongarch.md | 6 ++
1 file changed, 6 insertions(+)
diff --git a/gcc/config/loo
OK!
在 2022/4/27 下午7:45, Xi Ruoyao 写道:
On Wed, 2022-04-27 at 14:57 +0800, Lulu Cheng wrote:
I think the modification should be below.
if (!TYPE_P (TREE_TYPE (f)))
return -1;
I think (!TYPE_P (TREE_TYPE (f)) will never be true (the code handling
calling
I have pushed upstream. Thanks. Lulu Cheng
在 2022/4/27 下午7:45, Xi Ruoyao 写道:
On Wed, 2022-04-27 at 14:57 +0800, Lulu Cheng wrote:
I think the modification should be below.
if (!TYPE_P (TREE_TYPE (f)))
return -1;
I think (!TYPE_P (TREE_TYPE (f)) will never be
If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to be
implemented through "ll.w+sc.w". In the implementation of the instruction
sequence,
it is necessary to determine whether the two registers are equal.
Since LoongArch's comparison instructions do not distinguish between
When the value of the macro DEFAULT_CFLAGS is set to '-ansi -pedantic-errors',
regname-s9-fp.c will test to fail. To solve this problem, add the compilation
option '-Wno-pedantic -std=gnu90' to this test case.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/regname-fp-s9.c: Add compilatio
LTO option streaming and target attributes both require per-function
target configuration, which is achieved via option save/restore.
We implement TARGET_OPTION_{SAVE,RESTORE} to switch the la_target
context in addition to other automatically maintained option states
(via the "Save" option propert
LTO option streaming and target attributes both require per-function
target configuration, which is achieved via option save/restore.
We implement TARGET_OPTION_{SAVE,RESTORE} to switch the la_target
context in addition to other automatically maintained option states
(via the "Save" option propert
Add descriptions for the compilation options '-mfrecipe' '-mdiv32'
'-mlam-bh' '-mlamcas' and '-mld-seq-sa'.
gcc/ChangeLog:
* doc/invoke.texi: Add descriptions for the compilation
options.
---
gcc/doc/invoke.texi | 45 +++--
1 file changed,
Fixes: d28ea8e5a704 ("LoongArch: Split loongarch_option_override_internal
into smaller procedures")
gcc/ChangeLog:
* config/loongarch/loongarch.opt.urls: Regenerate.
---
gcc/config/loongarch/loongarch.opt.urls | 19 +--
1 file changed, 17 insertions(
Xi Ruoyao set the alignment rules under LA464 in commit r14-1839,
but the macro ASM_OUTPUT_ALIGN_WITH_NOP was removed in R14-4674,
which affected the alignment rules.
So I set different aligns on LA464 and LA664 again to test the
performance of spec2006, and modify the alignment based on the test
Pushed to r14-9766.
在 2024/4/2 下午2:33, Jiahao Xu 写道:
For machines that satisfy ISA_HAS_LSX && !TARGET_64BIT, we will not support
them now
and in the future, so this patch removes these unused code.
gcc/ChangeLog:
* config/loongarch/lasx.md: Remove unused code.
* config/loongar
在 2024/4/6 下午5:53, Xi Ruoyao 写道:
On Tue, 2024-04-02 at 15:03 +0800, Lulu Cheng wrote:
+/* Alignment for functions loops and jumps for best performance. For new
+ uarchs the value should be measured via benchmarking. See the documentation
+ for -falign-functions -falign-loops and -falign
gcc/ChangeLog:
* config/loongarch/loongarch.opt.urls: Regenerate.
* config/mn10300/mn10300.opt.urls: Likewise.
* config/msp430/msp430.opt.urls: Likewise.
* config/nds32/nds32-elf.opt.urls: Likewise.
* config/nds32/nds32-linux.opt.urls: Likewise.
* co
Pushed to r14-9866.
在 2024/4/8 下午4:45, Yang Yujie 写道:
This patch fixes the back-end context switching in cases where functions
should be built with their own target contexts instead of the
global one, such as LTO linking and functions with target attributes (TBD).
PR target/113233
gcc/
From: chenguoqi
libsanitizer/ChangeLog:
* configure.tgt: Enable tsan and lsan for loongarch64.
* tsan/Makefile.am (EXTRA_libtsan_la_SOURCES): Add
tsan_rtl_loongarch64.S.
* tsan/Makefile.in: Regenerate.
---
libsanitizer/configure.tgt| 5 +
libsanitizer/tsa
gcc/ChangeLog:
* config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
function return value type to unsigned short.
---
gcc/config/loongarch/larchintrin.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/loongarch/larchintrin.h
b/gcc/config/loong
gcc/ChangeLog:
* config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
symbol type conversions.
(__cacop_d): Likewise.
(__cpucfg): Likewise.
(__asrtle_d): Likewise.
(__asrtgt_d): Likewise.
(__lddir_d): Likewise.
(__ldpte_d):
From: Xi Ruoyao
Now loongarch.md uses HAVE_AS_TLS, we need this to fix the failure
building a cross compiler if the cross assembler is not installed yet.
gcc/ChangeLog:
PR target/112299
* config/loongarch/loongarch-opts.h (HAVE_AS_TLS): Define to 0
if not defined yet.
(
There are two reasons for removing this macro definition:
1. The default in the assembler is to use the nop instruction for filling.
2. For assembly directives: .align [abs-expr[, abs-expr[, abs-expr]]]
The third expression it is the maximum number of bytes that should be
skipped by this alig
ditional branch relaxation. (cherry pick r14-5434)
PR112299 is also fixed here.
Lulu Cheng (2):
LoongArch: Delete macro definition ASM_OUTPUT_ALIGN_WITH_NOP.
LoongArch: Check whether binutils supports the relax function. If
supported, explicit relocs are turned off by default.
Xi Ruoyao (
From: Xi Ruoyao
As the commit message of r14-4674 has indicated, if the assembler does
not support conditional branch relaxation, a relocation overflow may
happen on conditional branches when relaxation is enabled because the
number of NOP instructions inserted by the assembler will be more than
gcc/ChangeLog:
* config.in: Regenerate.
* config/loongarch/genopts/loongarch.opt.in: Add compilation option
mrelax. And set the initial value of explicit-relocs according to the
detection status.
* config/loongarch/gnu-user.h: When compiling with -mno-relax,
ditional branch relaxation. (cherry pick r14-5434)
PR112299 is also fixed here.
Lulu Cheng (2):
LoongArch: Delete macro definition ASM_OUTPUT_ALIGN_WITH_NOP.
LoongArch: Check whether binutils supports the relax function. If
supported, explicit relocs are turned off by default.
Xi Ruoyao (
There are two reasons for removing this macro definition:
1. The default in the assembler is to use the nop instruction for filling.
2. For assembly directives: .align [abs-expr[, abs-expr[, abs-expr]]]
The third expression it is the maximum number of bytes that should be
skipped by this alig
From: Xi Ruoyao
Now loongarch.md uses HAVE_AS_TLS, we need this to fix the failure
building a cross compiler if the cross assembler is not installed yet.
gcc/ChangeLog:
PR target/112299
* config/loongarch/loongarch-opts.h (HAVE_AS_TLS): Define to 0
if not defined yet.
(
gcc/ChangeLog:
* config.in: Regenerate.
* config/loongarch/genopts/loongarch.opt.in: Add compilation option
mrelax. And set the initial value of explicit-relocs according to the
detection status.
* config/loongarch/gnu-user.h: When compiling with -mno-relax,
From: Xi Ruoyao
As the commit message of r14-4674 has indicated, if the assembler does
not support conditional branch relaxation, a relocation overflow may
happen on conditional branches when relaxation is enabled because the
number of NOP instructions inserted by the assembler will be more than
ditional branch relaxation. (cherry pick r14-5434)
PR112299 is also fixed here.
Lulu Cheng (2):
LoongArch: Delete macro definition ASM_OUTPUT_ALIGN_WITH_NOP.
LoongArch: Check whether binutils supports the relax function. If
supported, explicit relocs are turned off by default.
Xi Ruoyao (
There are two reasons for removing this macro definition:
1. The default in the assembler is to use the nop instruction for filling.
2. For assembly directives: .align [abs-expr[, abs-expr[, abs-expr]]]
The third expression it is the maximum number of bytes that should be
skipped by this alig
gcc/ChangeLog:
* config.in: Regenerate.
* config/loongarch/genopts/loongarch.opt.in: Add compilation option
mrelax. And set the initial value of explicit-relocs according to the
detection status.
* config/loongarch/gnu-user.h: When compiling with -mno-relax,
From: Xi Ruoyao
As the commit message of r14-4674 has indicated, if the assembler does
not support conditional branch relaxation, a relocation overflow may
happen on conditional branches when relaxation is enabled because the
number of NOP instructions inserted by the assembler will be more than
From: Xi Ruoyao
Now loongarch.md uses HAVE_AS_TLS, we need this to fix the failure
building a cross compiler if the cross assembler is not installed yet.
gcc/ChangeLog:
PR target/112299
* config/loongarch/loongarch-opts.h (HAVE_AS_TLS): Define to 0
if not defined yet.
(
In binutils 2.40 and earlier versions, only a warning will be reported
when a relocation immediate value is out of bounds. As a result,
the value of the macro HAVE_AS_COND_BRANCH_RELAXATION will also be
defined as 1 when the assembler does not support conditional branch
relaxation. Therefore, add t
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_split_symbol):
Assign the '/u' attribute to the mem.
gcc/testsuite/ChangeLog:
* g++.target/loongarch/got-load.C: New test.
---
gcc/config/loongarch/loongarch.cc | 5 +
gcc/testsuite/g++.target/loo
TLS gd ld and ie type symbols will generate corresponding GOT entries,
so non-zero offsets cannot be generated.
The address of TLS le type symbol+addend is not implemented in binutils,
so non-zero offset is not generated here for the time being.
gcc/ChangeLog:
* config/loongarch/loongarch
s of a test case.
v1 -> v2:
1. Use the temporarily allocated registers as intermediate registers to
implement the extreme macro.
2. Fixed bugs in v1 test cases.
Lulu Cheng (4):
LoongArch: Merge template got_load_tls_{ld/gd/le/ie}.
LoongArch: Add the macro implementation of mcmode
Binutils does not support relaxation using four instructions to obtain
symbol addresses
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
When the code model of the symbol is extreme and -mexplicit-relocs=auto,
the macro instruction loading symb
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
Add support for call36.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c:
New test.
---
gcc/config/loongarch/loongarch.cc | 20 +++
gcc/ChangeLog:
* config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
Add function declaration.
* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
is not allowed
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_load_tls):
Load all types of tls symbols through one function.
(loongarch_got_load_tls_gd): Delete.
(loongarch_got_load_tls_ld): Delete.
(loongarch_got_load_tls_ie): Delete.
(loongarch_got_loa
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
Add support for call36.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c:
New test.
---
gcc/config/loongarch/loongarch.cc | 22 +++
plicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.
v2 -> v3:
1. Modify the detection rules of a test case.
v1 -> v2:
1. Use the temporarily allocated registers as intermediate registers to
implement the extreme macro.
2. Fixed bugs in v1 test cases.
Lulu Cheng (
gcc/ChangeLog:
* config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
Add function declaration.
* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
is not allowed
Binutils does not support relaxation using four instructions to obtain
symbol addresses
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
When the code model of the symbol is extreme and -mexplicit-relocs=auto,
the macro instruction loading symb
From: Xi Ruoyao
The ABI mandates the pcalau12i/addi.d/lu32i.d/lu52i.d instructions for
addressing a symbol to be adjacent. So model them as "one large
instruction", i.e. define_insn, with two output registers. The real
address is the sum of these two registers.
The advantage of this approach i
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_load_tls):
Load all types of tls symbols through one function.
(loongarch_got_load_tls_gd): Delete.
(loongarch_got_load_tls_ld): Delete.
(loongarch_got_load_tls_ie): Delete.
(loongarch_got_loa
From: chenguoqi
libsanitizer/ChangeLog:
* configure.tgt: Enable tsan and lsan for loongarch64.
* tsan/Makefile.am: Add tsan_rtl_loongarch64.S to
EXTRA_libtsan_la_SOURCES.
* tsan/Makefile.in: Regenerate.
---
libsanitizer/configure.tgt| 5 +
libsanitizer/tsan/Make
Modify address calculation logic from (((a x C) + fp) + offset) to ((fp +
offset) + a x C).
Thereby modifying the register dependencies and optimizing the code.
The value of C is 2 4 or 8.
The following is the assembly code before and after a loop modification in
spec2006 401.bzip:
Modify address calculation logic from (((a x C) + fp) + offset) to ((fp +
offset) + a x C).
Thereby modifying the register dependencies and optimizing the code.
The value of C is 2 4 or 8.
The following is the assembly code before and after a loop modification in
spec2006 401.bzip:
Check whether the assembler supports tls le relax. If it supports it, the
assembly
instruction sequence of tls le relax will be generated by default.
The original way to obtain the tls le symbol address:
lu12i.w $rd, %le_hi20(sym)
ori $rd, $rd, %le_lo12(sym)
add.{w/d} $rd, $rd, $tp
I
cmodel=extreme.
https://github.com/loongson/la-abi-specs/blob/release/laelf.adoc#extreme-code-model
Lulu Cheng (2):
LoongArch: Add the macro implementation of mcmodel=extreme.
LoongArch: When the code model is extreme, the symbol address is
obtained through macro instructions regardless of
Instructions pcalau12i, addi.d, lu32i.d and lu52i.d must be adjancent so that
the
linker can infer the PC of pcalau12i to apply relocations to lu32i.d and
lu52i.d.
Otherwise, the results would be incorrect if these four instructions are not in
the same 4KiB page.
See the link for details:
https:
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
Remove the sym+addend form from the SYMBOL_PCREL64 type symbol.
(loongarch_option_override_internal): Supports option combinations
of -cmodel=extreme and -mexplicit-relocs=none.
The [x]vld/[x]vst directive is defined as follows:
[x]vld/[x]vst {x/v}d, rj, si12
When not modified, the immediate field of [x]vld/[x]vst is between 10 and
14 bits depending on the type. However, in loongarch_valid_offset_p, the
immediate field is restricted first, so there is no error. However,
cmodel=extreme.
https://github.com/loongson/la-abi-specs/blob/release/laelf.adoc#extreme-code-model
v1 -> v2:
1. Use the temporarily allocated registers as intermediate registers to
implement the extreme macro.
2. Fixed bugs in v1 test cases.
Lulu Cheng (2):
LoongArch: Add the ma
Instructions pcalau12i, addi.d, lu32i.d and lu52i.d must be adjancent so that
the
linker can infer the PC of pcalau12i to apply relocations to lu32i.d and
lu52i.d.
Otherwise, the results would be incorrect if these four instructions are not in
the same 4KiB page.
See the link for details:
https:
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
Remove the sym+addend form from the SYMBOL_PCREL64 type symbol.
(loongarch_output_mi_thunk): Add code model extreme support.
(loongarch_option_override_internal): Supports option combina
Instructions pcalau12i, addi.d, lu32i.d and lu52i.d must be adjancent so that
the
linker can infer the PC of pcalau12i to apply relocations to lu32i.d and
lu52i.d.
Otherwise, the results would be incorrect if these four instructions are not in
the same 4KiB page.
See the link for details:
https:
a test case.
Lulu Cheng (2):
LoongArch: Add the macro implementation of mcmodel=extreme.
LoongArch: When the code model is extreme, the symbol address is
obtained through macro instructions regardless of the value of
-mexplicit-relocs.
gcc/config/loongarch/loongarch.cc
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
Remove the sym+addend form from the SYMBOL_PCREL64 type symbol.
(loongarch_output_mi_thunk): Add code model extreme support.
(loongarch_option_override_internal): Supports option combina
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