This is a RFC patch for large code model implementation.
gcc/ChangeLog:
* gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF
and LABEL_REF type.
(call_insn_operand): Support for CM_Large.
(pcrel_symbol_operand): New.
* gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_d
UNSPEC_CLMUL is defined to define_c_enum in riscv.md, so
it shouldn't be redefined to define_int_iterator again.
*gcc/ChangeLog:*
* config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to UNSPEC_CLMUL_VC.
0001-RISC-V-Raname-UNSPEC_CLMUL-in-vector-crypto.md.patch
Description: Binary data
Hi Jeff,
Sorry for this missing.
I've removed riscv_asm_output_pool_epilogue because the pool beginning is
always aligned from FUNCTION_BOUNDARY.
Please find attached. Thank you.
Jeff Law 於 2023年12月18日 週一 上午3:15寫道：
>
>
> On 11/10/23 02:10, KuanLin Chen wrote:
> > Sorry. I
According to spec, fmv.h checks if the input operands are correctly
NaN-boxed. If not, the input value is treated as an n-bit canonical NaN.
This patch fixs the issue that operands returned by soft-fp16 libgcc
(i.e., __truncdfhf2) was not correctly NaN-boxed.
*gcc/ChangeLog:*
* config/riscv/ri
According to spec, fmv.h checks if the input operands are correctly
NaN-boxed. If not, the input value is treated as an n-bit canonical NaN.
This patch fixs the issue that operands returned by soft-fp16 libgcc
(i.e., __truncdfhf2) was not correctly NaN-boxed.
*gcc/ChangeLog:*
* config/riscv/ri
According to spec, fmv.h checks if the input operands are correctly
NaN-boxed. If not, the input value is treated as an n-bit canonical NaN.
This patch fixs the issue that operands returned by soft-fp16 libgcc
(i.e., __truncdfhf2) was not correctly NaN-boxed.
*gcc/ChangeLog:*
* config/riscv/r
gcc/ChangeLog:
* gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF
and LABEL_REF type.
(call_insn_operand): Support for CM_Large.
(pcrel_symbol_operand): New.
* gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_define
"__riscv_cmodel_large".
* gcc/config/riscv/riscv-op
Sorry. It missed a semicolon in the previos patch. Please find the new one
in the attachment. Thanks.
0001-RISC-V-Support-mcmodel-large.patch
Description: Binary data
According to spec, fmv.h checks if the input operands are correctly
NaN-boxed. If not, the input value is treated as an n-bit canonical NaN.
This patch fixs the issue that operands returned by soft-fp16 libgcc
(i.e., __truncdfhf2) was not correctly NaN-boxed.
*gcc/ChangeLog:*
* config/riscv/ri
The GTY skip makes GGC clean the registered functions wrongly in lto.
Example:
riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c
-O2 -march=rv64gcv
In file included from bug-3.c:2: internal compiler error: Segmentation fault
gcc/ChangeLog:
*riscv-vector-built
In the origin, cc1 registers rvv builtins with turn on all sub vector
extensions but lto not. It makes lto use the asynchronous DECL_MD_FUNCTION_CODE
from lto-objects.
Example:
riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c
-O2 -march=rv64gcv
bug-3.c: In function '
simulate_builtin_function_decl may return decl that be ggc_freed already
in pushdecl when duplicate_decls is true. Add a argument CREATE_P for
the caller to know if the return decl is usable.
gcc/ChangeLog:
* langhooks.h (simulate_builtin_function_decl):
Add one more argument.
Hi Jeff,
I'm really sorry for the regression failure.
I missed one patch to fix these issues.
Thanks for your review.
The GTY skip makes GGC clean the registered functions wrongly in lto.
Example:
riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c
-O2 -march=rv64gcv
In the origin, cc1 registers rvv builtins with turn on all sub vector
extensions but lto not. It makes lto use the asynchronous DECL_MD_FUNCTION_CODE
from lto-objects.
Example:
riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c
-O2 -march=rv64gcv
bug-10.c: In function
Hi,
This patch adds support for the XAndesperf ISA extension.
The 32-bit AndeStar V5 extension includes branch instructions,
load effective address instructions, and string processing
instructions for performance improvement.
New INSN patterns are added into the new file andes.md
as a seprated ven
Hi,
This extension defines vector instructions to calculae of the
signed/unsigned
dot product of four SEW/4-bit data and accumulate the result into a SEWbit
element for all elements in a vector register.
gcc/ChangeLog:
* config/riscv/andes-vector-builtins-bases.cc (nds_vd4dot): New
class
Hi,
This extension defines instructions to perform scalar floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754
32-bit single-precision floating-point (SP) data in a scalar
floating point register.
gcc/ChangeLog:
* config/riscv/andes.def: Add nds_fcvt_s_bf16
Hi,
This patch add support for XAndesvbfhcvt ISA extension.
This extension defines instructions to perform vector floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit
single-precision floating-point (SP) data in a vector register.
gcc/ChangeLog:
* co
Hi,
This extension defines vector instructions to extract a pair of FP16 data
from
a floating-point register. Multiply the top FP16 data with the FP16 elements
and add the result with the bottom FP16 data.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
Turn on VECTOR_ELEN_
Hi,
This is a patch series for Andes vender extension of RISC-V.
These patches are tested by riscv-gnu-toolchain gcc/g++ testsuite. And the
report is the same as without these patches.
= Summary of gcc testsuite =
| # of unexpected case /
Hi,
This extension defines vector load instructions to move sign-extended or
zero-extended INT4 data into 8-bit vector register elements.
gcc/ChangeLog:
* config/riscv/andes-vector-builtins-bases.cc
(nds_nibbleload): New class.
* config/riscv/andes-vector-builtins-bases.h
Hi,
This extension defines vector instructions to calculae of the
signed/unsigned
dot product of four SEW/4-bit data and accumulate the result into a SEWbit
element for all elements in a vector register.
gcc/ChangeLog:
* config/riscv/andes-vector-builtins-bases.cc (nds_vd4dot): New
class
Hi,
This extension defines vector load instructions to move sign-extended or
zero-extended INT4 data into 8-bit vector register elements.
gcc/ChangeLog:
* config/riscv/andes-vector-builtins-bases.cc
(nds_nibbleload): New class.
* config/riscv/andes-vector-builtins-bases.h
Hi Jeff,
> You've added a new type (nds_vfpmad). You'll need to udpate all the
> existing DFAs to handle insns with that type. Otherwise someone that
> asks for code generation for your design, but a different tuning model
> will get aborts.
> It's generally considered OK to add them to a dummy
Hi Kito,
>>* +(define_predicate "extract_loc_imm_si"*
> Rename it to unsigned_5_bit_integer_operand
>>* + (and (match_code "const_int")
*>>* +(match_test "IN_RANGE (INTVAL (op), 0, 31)")))
*>>* +*
>>* +(define_predicate "extract_loc_imm_di"*
> Rename it to unsigned_6_bit_integer_operand
Hi,
This extension defines instructions to perform scalar floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754
32-bit single-precision floating-point (SP) data in a scalar
floating point register.
gcc/ChangeLog:
* config/riscv/andes.def: Add nds_fcvt_s_bf16
Hi Jeff,
> Just a nit. In several places you need to replace
> "UPPERCAE_NAME" with "UPPERCASE_NAME".
Fixed. Thanks for your review.
This is a patch series for Andes vender extension of RISC-V.
These patches are tested by riscv-gnu-toolchain gcc/g++ testsuite. And the
report is the same as with
Hi,
This patch add support for XAndesvbfhcvt ISA extension.
This extension defines instructions to perform vector floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit
single-precision floating-point (SP) data in a vector register.
gcc/ChangeLog:
* co
Jeff Law 於 2025年7月22日 週二 上午6:34寫道：
Hi Jeff,
Thanks your review.
> > +
> > +(define_insn "*nds_branch_imms7"
> > + [(set (pc)
> > + (if_then_else
> > + (match_operator 1 "equality_operator"
> > + [(match_operand:X 2 "register_operand" "r")
> > + (match_operand:X 3 "ad
Hi Kito,
Kito Cheng 於 2025年7月30日 週三 上午9:01寫道：
>
> > +(define_insn "@nds_vfwcvt_bf16"
> > + [(set (match_operand:NDS_VWEXTBF 0 "register_operand"
> > "=&vr")
> > + (unspec_volatile:NDS_VWEXTBF
> > + [(float_extend:NDS_VWEXTBF
> > +(match_operand: 1 "reg
Please find:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release
These instructions are from "3.1.26. NDS.FFB" to "3.1.29. NDS.FLMISM"
in AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf.
Thanks.
Jeff Law 於 2025年7月30日 週三 下午11:22寫道：
>
>
>
>
Hi Jeff & Kito,
Thanks for all your review.
We'll Fixed these in next patch version.
Kito Cheng 於 2025年7月30日 週三 上午9:48寫道：
>
> On Tue, Jul 22, 2025 at 6:40 AM Jeff Law wrote:
> >
> >
> >
> > On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
> > > This extension defines instructions to perform scalar floa
Hi Juzhe,
I think fault_load_def::get_name should remove "instance.pred ==
PRED_TYPE_mu", right?
於 2023年6月2日 週五 上午7:05寫道：
>
> From: Juzhe-Zhong
>
> Base on these:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/232
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/233
>
> Ad
33 matches
Mail list logo
