[avr,committed] Use monic denominator polynomials to save a multiplication.

This is a small tweak in LibF7 to save one multiplication in computation of denominator polynomials. The polynomials are monic now, and f7_horner needs one multiplication less. Johann -- LibF7: Use monic denominator polynomials to save a multiplication. libgcc/config/avr/libf7/ * libf

[avr,committed] Remove all uses of attribute pure from LibF7.

Applied the following patch. Johann LibF7: Remove uses of attribute pure. libgcc/config/avr/libf7/ * libf7.h (F7_PURE): Remove all occurrences. * libf7.c: Same. diff --git a/libgcc/config/avr/libf7/libf7.c b/libgcc/config/avr/libf7/libf7.c index 373a8a55d90..0d9e4c325b2 1006

[avr,committed] Implement atan2

This implements atan2 which was missing from LibF7. Johann -- LibF7: Implement atan2. libgcc/config/avr/libf7/ * libf7.c (F7MOD_atan2_, f7_atan2): New module and function. * libf7.h: Adjust comments. * libf7-common.mk (CALL_PROLOGUES): Add atan2. diff --git a/libgcc/c

[avr,committed] Implement fma, fmal.

This commit implements fma and fmal which were missing from LibF7. Johann -- LibF7: Implement fma / fmal. libgcc/config/avr/libf7/ * libf7.h (F7_SIZEOF): New macro. * libf7-asm.sx: Use F7_SIZEOF instead of magic number "10". (F7MOD_D_fma_, __fma): New module and functio

[avr,committed] LibF7: Implement a function that was missing for devices without MUL.

This implements the worker function for double multiplication for devices without MUL instruction. Johann -- LibF7: Implement mul_mant for devices without MUL instruction. libgcc/config/avr/libf7/ * libf7-asm.sx (mul_mant): Implement for devices without MUL. * asm-defs.h (wmov)

[patch,libgcc,contrib]: Add some auto-generated files deps to gcc_update.

This patch adds two deps to gcc_update files_and_dependencies for two auto-generated headers from avr libgcc. Ok for master? Johann -- Add dependencies for some auto-generated files from avr-libgcc. / * contrib/gcc_update (files_and_dependencies): Add dependencies for: libgcc/

Ping #1: [patch,avr] Fix PR109650 wrong code

Ping #1 for: https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618976.html https://gcc.gnu.org/pipermail/gcc-patches/attachments/20230519/9536bf8c/attachment-0001.bin Johann Am 19.05.23 um 10:49 schrieb Georg-Johann Lay: Here is a revised version of the patch.  The difference to the

[testsuite,applied] PR52641: Fix more implicit int=32 fallout.

Committed to undo implicit assumptions. Johann testsuite/52641: Fix more of implicit int=32 assumption fallout. gcc/testsuite/ PR testsuite/52641 * gcc.dg/torture/pr107451.c: Require int32plus. * gcc.dg/torture/pr108574-3.c: Use __INT32_TYPE__ instead of int. * g

[patch] Fix PR101188 wrong code from postreload

There is the following bug in postreload that can be traced back to v5 at least: In postreload.cc::reload_cse_move2add() there is a loop over all insns. If it encounters a SET, the next insn is analyzed if it is a single_set. After next has been analyzed, it continues with if (success)

[avr, committed] Improve operations on non-LD_REGS when the operation follows a move from LD_REGS.

Applied the following patch to improve operations on no-LD_REGS when the operation follows a move from LD_REGS. Johann target/110088: Improve operation of l-reg with const after move from d-reg. After reload, there may be sequences like lreg = dreg lreg = lreg const with an LD_REGS dreg,

Re: [patch] Fix PR101188 wrong code from postreload

Am 03.06.23 um 17:53 schrieb Jeff Law: On 6/2/23 02:46, Georg-Johann Lay wrote: There is the following bug in postreload that can be traced back to v5 at least: In postreload.cc::reload_cse_move2add() there is a loop over all insns.  If it encounters a SET, the next insn is analyzed if it

Re: [patch] Fix PR101188 wrong code from postreload

Am 03.06.23 um 17:53 schrieb Jeff Law: On 6/2/23 02:46, Georg-Johann Lay wrote: There is the following bug in postreload that can be traced back to v5 at least: In postreload.cc::reload_cse_move2add() there is a loop over all insns.  If it encounters a SET, the next insn is analyzed if it

Ping #2: [patch,avr] Fix PR109650 wrong code

Ping #2 for: https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618976.html https://gcc.gnu.org/pipermail/gcc-patches/attachments/20230519/9536bf8c/attachment-0001.bin Ping #1: https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620098.html Johann Am 19.05.23 um 10:49 schrieb Georg-Johann Lay

[patch,avr]: Improve bit-extractions as of PR109907.

This patch improves bit-extractions on AVR. Andrew added some patches so that more bit extractions are recognized in the middle-end and rtl optimizers. The patch adds pattern for "extzv" and replaces the deprecated "extzv". There are still situations where expensive shifts are passed down to th

[avr,committed] Tidy code for inverted bit insertions

Applied this no-op change that tidies up the code for inverted bit insertions. Johann -- Use canonical form for reversed single-bit insertions after reload. We now split almost all insns after reload in order to add clobber of REG_CC. If insns are coming from insn combiner and there is no c

[Patch,avr,committed] Fix PR target/110220: Set JUMP_LABEL as required.

Committed as obvious. An insn emitted by avr specific RTL optimization pass missed setting of its JUMP_LABEL. Johann target/110220: Set JUMP_LABEL and LABEL_NUSES of new branch insn generated by target specific RTL optimization pass .avr-casesi. gcc/ PR target/110220

[avr,committed] Fix some typos in avr-mcus.def

This fixes some minor typos in avr-mcus.def. Johan gcc/ * config/avr/avr-mcus.def (avr128d*, avr64d*): Fix their FLASH_SIZE and PM_OFFSET entries. diff --git a/gcc/config/avr/avr-mcus.def b/gcc/config/avr/avr-mcus.def index ca99116adab..d0056c960ee 100644 --- a/gc

[avr,committed] Add some more devices to avr-mcus.def.

This adds some more Xmega like devices to the avr backend. Johann AVR: Add some more devices: AVR16DD*, AVR32DD*, AVR64DD*, AVR64EA*, ATtiny42*, ATtiny82*, ATtiny162*, ATtiny322*, ATtiny10*. gcc/ * config/avr/avr-mcus.def (avr64dd14, avr64dd20, avr64dd28, avr64dd32) (

Re: [AVR PATCH] Improvements to SImode and PSImode shifts by constants.

Am 02.11.23 um 12:54 schrieb Roger Sayle: This patch provides non-looping implementations for more SImode (32-bit) and PSImode (24-bit) shifts on AVR. For most cases, these are shorter and faster than using a loop, but for a few (controlled by optimize_size) Maybe this should also adjust t

[patch,avr] Fix PR109650 wrong code

This patch fixes a wrong-code bug in the wake of PR92729, the transition that turned the AVR backend from cc0 to CCmode. In cc0, the insn that uses cc0 like a conditional branch always follows the cc0 setter, which is no more the case with CCmode where set and use of REG_CC might be in different

[patch,avr] PR105753: Fix ICE in add_clobbers.

This patch removes the superfluous parallel in [u]divmod patterns in the AVR backend. Effect of extra parallel is that add_clobbers reaches gcc_unreachable() because the clobbers for [u]divmod are missing. The parallel around the parts of an insn pattern is implicit if it has multiple parts like

[avr,committed] Fix a trivial typo in gen-avr-mmcu-specs.cc.

Applied as obvious, there was a trailing */ in a 1-line // comment. https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=a726d007f197d13ec80b9d625bf8bab97c96384c Johann gcc/ChangeLog * config/avr/gen-avr-mmcu-specs.cc: Remove stale */ after // comment. -- diff --git a/gcc/config/avr/gen

Re: [patch,avr] Fix PR109650 wrong code

handle fixed-point modes. Apart from that, the patch behaves the same: Am 15.05.23 um 20:05 schrieb Georg-Johann Lay: This patch fixes a wrong-code bug in the wake of PR92729, the transition that turned the AVR backend from cc0 to CCmode.  In cc0, the insn that uses cc0 like a conditional branch

Re: [patch,avr] Fix PR109650 wrong code

slightly more general in that they also handle fixed-point modes. Apart from that, the patch behaves the same: Am 15.05.23 um 20:05 schrieb Georg-Johann Lay: This patch fixes a wrong-code bug in the wake of PR92729, the transition that turned the AVR backend from cc0 to CCmode.  In cc0, the insn

[avr,committed] Fix PR90622

This patch fixes a minor optimization issue for an avr specific builtin. Applied as obvious. https://gcc.gnu.org/r14-1025 Johann -- target/90622: __builtin_avr_insert bits: Use BLD/BST for one bit in place. If just one bit is inserted in the same position like with: __builtin_avr_insert_

[avr,testsuite,committed] Skip test that fail for avr for this or that reason.

This annotates some tests that won't work for AVR like: * asm goto with output reload (AVR is not lra). * Using a program address as a ram address. * Float related stuff: AVR double is 32-bit, and long double is incomplete (some functions missing, no signed zeros, etc.) Applied as obvious.

[testsuite,committed] PR testsuite/52641

: Georg-Johann Lay Date: Mon May 22 16:47:56 2023 +0200 testsuite/52641: Fix tests that fail for 16-bit int / pointer targets. gcc/testsuite/ PR testsuite/52641 * c-c++-common/pr19807-2.c: Use __SIZEOF_INT__ instead of 4. * gcc.c-torture/compile/pr103813

[testsuite,committed]: PR52614: Fix more of the int=32 assumption fallout.

Applied more of the int=32 assumption fallout. Johann -- testsuite/52641: Fix more of implicit int=32 assumption fallout. gcc/testsuite/ PR testsuite/52641 * gcc.c-torture/compile/pr108892.c: Require int32. * gcc.c-torture/compile/pr98199.c: Require int32plus. *

[patch]: Implement PR104327 for avr

PR target/104327 not only affects s390 but also avr: The avr backend pre-sets some options depending on optimization level. The inliner then thinks that always_inline functions are not eligible for inlining and terminates with an error. Proposing the following patch that implements TARGET_CAN_INL

[avr,committed] Fix cost computation for bit insertions.

Applied this patchlet that implements proper cost computation of (set (zero_extract (...) ...)) kind patterns that do single-bit (inverted) bit insertions. Johann -- Improve cost computation for single-bit bit insertions. Some miscomputation of rtx_costs lead to sub-optimal code for single-

Re: [patch]: Implement PR104327 for avr

Am 24.05.23 um 11:38 schrieb Richard Biener: On Tue, May 23, 2023 at 2:56 PM Georg-Johann Lay wrote: PR target/104327 not only affects s390 but also avr: The avr backend pre-sets some options depending on optimization level. The inliner then thinks that always_inline functions are not

Re: [patch]: Implement PR104327 for avr

Am 25.05.23 um 08:35 schrieb Richard Biener: On Wed, May 24, 2023 at 5:44 PM Georg-Johann Lay wrote: Am 24.05.23 um 11:38 schrieb Richard Biener: On Tue, May 23, 2023 at 2:56 PM Georg-Johann Lay wrote: PR target/104327 not only affects s390 but also avr: The avr backend pre-sets some

[avr,committed] PR82931: Improve single-bit transfers between registers.

Applied this patch that makes one insn more generic so it can handle more bit positions than just 0. Johann -- target/82931: Make a pattern more generic to match more bit-transfers. There is already a pattern in avr.md that matches single-bit transfers from one register to another one, but it

[avr,committed]: Implement PR104327 for avr

Am 25.05.23 um 17:07 schrieb Richard Biener: Am 25.05.2023 um 16:22 schrieb Georg-Johann Lay :  Am 25.05.23 um 08:35 schrieb Richard Biener: On Wed, May 24, 2023 at 5:44 PM Georg-Johann Lay wrote: Am 24.05.23 um 11:38 schrieb Richard Biener: On Tue, May 23, 2023 at 2:56 PM Georg

[patch, avr] Fix PR target/99184: Wrong cast from double to 16-bit and 32-bit ints.

Hello, this patch fixed PR target/99184 which incorrectly rounded during 64-bit (long) double to 16-bit and 32-bit integers. The patch just removes the respective roundings from libf7-asm.sx::to_integer and ::to_unsigned. Luckily, LibF7 does nowhere use respective functions internally, the

Re: [patch, avr] Fix PR target/99184: Wrong cast from double to 16-bit and 32-bit ints.

Am 19.09.22 um 09:51 schrieb Richard Biener: On Sun, Sep 18, 2022 at 7:40 PM Georg Johann Lay wrote: Hello, this patch fixed PR target/99184 which incorrectly rounded during 64-bit (long) double to 16-bit and 32-bit integers. The patch just removes the respective roundings from libf7

[PATCH] improved const shifts for AVR targets

Hi, recently I used some arduino uno for a project and realized some areas which do not output optimal asm code. Especially around shifts and function calls. With this as motivation and hacktoberfest I started patching things. Since patch files do not provide a good overview and I hope for a "hack

Re: [PATCH v3] c++: parser - Support for target address spaces in C++

[PATCH v3] c++: parser - Support for target address spaces in C++ First of all, it is great news that GCC is going to implement named address spaces for C++. I have some questions: 1. How is name-mangling going to work? == Clang supports address spaces in

Re: [PATCH] PR85678: Change default to -fno-common

Wilco Dijkstra schrieb: GCC currently defaults to -fcommon. As discussed in the PR, this is an ancient C feature which is not conforming with the latest C standards. On many targets this means global variable accesses have a codesize and performance penalty. This applies to C code only, C++ cod

[patch,avr,committed] Remove an unused function (PR85969)

Applied as obvious Johann PR target/85969 * config/avr/gen-avr-mmcu-specs.c (str_prefix_p): Remove unused static function. --- trunk/gcc/config/avr/gen-avr-mmcu-specs.c 2019/10/25 14:39:06 277454 +++ trunk/gcc/config/avr/gen-avr-mmcu-specs.c 2019/10/25 15:13:23

[patch][avr] PR92055: Add switches to enable 64-bit [long] double.

Hi, this adds the possibility to enable IEEE compatible double and long double support in avr-gcc. It supports 2 configure options --with-double={32|64|32,64|64,32} --with-long-double={32|64|32,64|64,32|double} which select the default layout of these types and also chose which mutlilib variant

Re: [PATCH] Support multiple registers for the frame pointer

Am 04.11.19 um 16:22 schrieb Vladimir Makarov: On 2019-11-02 1:28 p.m., Kwok Cheung Yeung wrote: The AMD GCN architecture uses 64-bit pointers, but the scalar registers are 32-bit wide, so pointers must reside in a pair of registers. The two hard registers holding the frame pointer are curre

Re: [PATCH] Support multiple registers for the frame pointer

Kwok Cheung Yeung schrieb: The AMD GCN architecture uses 64-bit pointers, but the scalar registers are 32-bit wide, so pointers must reside in a pair of registers. The two hard registers holding the frame pointer are currently fixed, but if they are changed to unfixed (so that the FP can be el

Ping^1 [patch][avr] PR92055: Add switches to enable 64-bit [long] double.

Ping #1 Am 31.10.19 um 22:55 schrieb Georg-Johann Lay: Hi, this adds the possibility to enable IEEE compatible double and long double support in avr-gcc. It supports 2 configure options --with-double={32|64|32,64|64,32} --with-long-double={32|64|32,64|64,32|double} which select the default

Re: GCC wwwdocs move to git done

Am 09.10.19 um 02:27 schrieb Joseph Myers: I've done the move of GCC wwwdocs to git (using the previously posted and discussed scripts), including setting up the post-receive hook to do the same things previously covered by the old CVS hooks, and minimal updates to the web pages dealing with the

Re: GCC wwwdocs move to git done

Am 06.11.19 um 15:03 schrieb Georg-Johann Lay: Am 09.10.19 um 02:27 schrieb Joseph Myers: I've done the move of GCC wwwdocs to git (using the previously posted and discussed scripts), including setting up the post-receive hook to do the same things previously covered by the old CVS hooks

Re: Ping^1 [patch][avr] PR92055: Add switches to enable 64-bit [long] double.

Am 06.11.19 um 11:39 schrieb Georg-Johann Lay: Ping #1 Am 31.10.19 um 22:55 schrieb Georg-Johann Lay: Hi, this adds the possibility to enable IEEE compatible double and long double support in avr-gcc. It supports 2 configure options --with-double={32|64|32,64|64,32} --with-long-double={32|64

Re: [patch][avr] PR92055: Add switches to enable 64-bit [long] double.

Am 07.11.19 um 10:41 schrieb Martin Liška: Hello. I've noticed quite some GNU coding style violations with your patch. Please next time, use something like: $ git diff HEAD~ > /tmp/patch && ./contrib/check_GNU_style.py /tmp/patch Thanks, Martin hm, I am actually using GNU style with Emacs..

Re: [patch][avr] PR92055: Add switches to enable 64-bit [long] double.

Am 07.11.19 um 13:49 schrieb Martin Liška: On 11/7/19 1:39 PM, Georg-Johann Lay wrote: Am 07.11.19 um 10:41 schrieb Martin Liška: Hello. I've noticed quite some GNU coding style violations with your patch. Please next time, use something like: $ git diff HEAD~ > /tmp/patch &

[patch,avr] Add suport for devices from the 0-series.

Hi, this patch adds support for a few more AVR devices. Because the offset where flash is seen in RAM deviates from the settings for the family (and hence also from the linker script defaults), a new field in avr_mcu_t is needed to express this so that specs can be generated appropriately.

Ping^1: [patch,avr] Add suport for devices from the 0-series.

Ping ? Am 08.11.19 um 17:19 schrieb Georg-Johann Lay: Hi, this patch adds support for a few more AVR devices.  Because the offset where flash is seen in RAM deviates from the settings for the family (and hence also from the linker script defaults), a new field in avr_mcu_t is needed to

[wwwdocs] Add AVR news.

Added the following change to the v10 changes site. Johann diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index d6108269..7d96bc66 100644 --- a/htdocs/gcc-10/changes.html +++ b/htdocs/gcc-10/changes.html @@ -334,7 +334,54 @@ a work-in-progress. arm-uclinuxfdpiceabi, and

[patch,avr,applied]: Simplify asm macro skip.

Applied the following trivial and obvious patch to the avr back. Johann libgcc/ * config/avr/lib1funcs.S (skip): Simplify. diff --git a/libgcc/config/avr/lib1funcs.S b/libgcc/config/avr/lib1funcs.S index 8ebdc01c88c..2ffa2090b25 100644 --- a/libgcc/config/avr/lib1funcs.S +++ b/libgcc/c

[avr,applied]: Remove a no more existing file from contrib/gcc_update::files_and_dependencies.

Hi, gcc/config/avr/t-multilib does no more exist, hence removed from the files to touch. Applied addendum to PR92055 (which removed that file) as obvious. Johann The mentioned auto-generated file is no more part of the GCC sources, it's auto-generated in $(builddir) during

[avr,committed] Add support for some avrxmega3 devices.

Applied this patchlet to add support for: ATtiny1604, ATtiny1606, ATtiny1607, ATtiny402, ATtiny404, ATtiny406, ATtiny804, ATtiny806, ATtiny807, ATtiny202, ATtiny204. Johann Add support for some more AVR devices from avrxmega3 family. * config/avr/avr-mcus.def (attiny1604, att

[patch,avr, 0/3] Support 64-bit (long) double.

Now that the avr backend can support 64-bit floats by means of configure-options --with-double= and --with-long-double=, this patch series adds some routines to support it. It's an ad-hoc, avr-specific implementation in assembly and GNU-C which is added as a new subfolder in libgcc/config/avr/

[patch,avr, 1/3] Support 64-bit (long) double: The gcc part.

Am 16.12.19 um 17:40 schrieb Georg-Johann Lay: Patch 1/3 is the GCC changes: Documentation and new avr-specific configure options: --with-libf7 selects to which level double support from libf7 is added to libgcc. --with-double-comparison select what FLOAT_LIB_COMPARE_RETURNS_BOOL returns

Re: [patch,avr, 2/3] Support 64-bit (long) double: The libgcc changes.

Am 16.12.19 um 17:40 schrieb Georg-Johann Lay: Patch 2/3 is the libgcc additions: --with-libf7 selects which makefile-snips from libf7 to use. libgcc/ * config.host (tmake_file) [target=avr]: Add t-libf7, t-libf7-math, t-libf7-math-symbols as specified by --with-libf7

[patch][avr] PR92606: Disable -fipa-icf-variables because it generates wrong code.

Hi, this patch turns off -fipa-icf-variables because it generates wrong code like for PR92606. As there is no target hook that could decide whether such optimizations are obsolete, disable such optimizations alltogether until PR92932 (target hook to disable such optimizations depending on obje

[patch][avr] New option -nodevicespecs to omit -specs=... in self specs.

Hi, currently device support in avr-gcc is accomplished by injecting a specs file my means of -specs=... in dirver self specs. This patch adds a new avr driver option to omit the addition of respective -specs option so give the user more freedom. Ok to apply? Johann * config/avr/avr

[PING^1][patch][avr] PR92606: Disable -fipa-icf-variables because it generates wrong code.

Ping #1. Hi, this patch turns off -fipa-icf-variables because it generates wrong code like for PR92606. As there is no target hook that could decide whether such optimizations are obsolete, disable such optimizations alltogether until PR92932 (target hook to disable such optimizations depend

[PING^1][patch][avr] New option -nodevicespecs to omit -specs=... in self specs.

Ping #1 Hi, currently device support in avr-gcc is accomplished by injecting a specs file my means of -specs=... in dirver self specs. This patch adds a new avr driver option to omit the addition of respective -specs option so give the user more freedom. Ok to apply? Johann * config/a

[PING^1][patch,avr, 0/3] Support 64-bit (long) double.

Ping #1 Now that the avr backend can support 64-bit floats by means of configure-options --with-double= and --with-long-double=, this patch series adds some routines to support it. It's an ad-hoc, avr-specific implementation in assembly and GNU-C which is added as a new subfolder in libgcc/c

[PING^1][patch,avr, 0/3] Support 64-bit (long) double.

Ping #1 Now that the avr backend can support 64-bit floats by means of configure-options --with-double= and --with-long-double=, this patch series adds some routines to support it. It's an ad-hoc, avr-specific implementation in assembly and GNU-C which is added as a new subfolder in libgcc/c

[PING^1][patch,avr, 2/3] Support 64-bit (long) double: The libgcc changes.

Ping #1 Am 16.12.19 um 17:40 schrieb Georg-Johann Lay: Patch 2/3 is the libgcc additions: --with-libf7 selects which makefile-snips from libf7 to use. libgcc/ * config.host (tmake_file) [target=avr]: Add t-libf7, t-libf7-math, t-libf7-math-symbols as specified by --with-libf7

[PING^1][patch,avr, 3/3] Support 64-bit (long) double: libf7.

Ping #1 Am 16.12.19 um 17:40 schrieb Georg-Johann Lay: Patch 3/3 is the actual libf7 implementation. A great deal of which is assembly, together with C + inline assembly for higher routines. Johann libgcc/config/avr/libf7/ * t-libf7: New file. * t-libf7-math: New file. * t-libf7

[PING^1][patch,avr, 1/3] Support 64-bit (long) double: The gcc part.

Ping #1 Am 16.12.19 um 17:40 schrieb Georg-Johann Lay: Patch 1/3 is the GCC changes: Documentation and new avr-specific configure options: --with-libf7 selects to which level double support from libf7 is added to libgcc. --with-double-comparison select what FLOAT_LIB_COMPARE_RETURNS_BOOL

[PING^2][patch][avr] PR92606: Disable -fipa-icf-variables because it generates wrong code.

Ping #2. Hi, this patch turns off -fipa-icf-variables because it generates wrong code like for PR92606. As there is no target hook that could decide whether such optimizations are obsolete, disable such optimizations alltogether until PR92932 (target hook to disable such optimizations depend

[PING^2][patch][avr] New option -nodevicespecs to omit -specs=... in self specs.

Ping #2 Hi, currently device support in avr-gcc is accomplished by injecting a specs file my means of -specs=... in dirver self specs. This patch adds a new avr driver option to omit the addition of respective -specs option so give the user more freedom. Ok to apply? Johann * config/a

[Ping^2][patch,avr, 2/3] Support 64-bit (long) double: The libgcc changes.

Ping #2 Georg-Johann Lay schrieb: Am 16.12.19 um 17:40 schrieb Georg-Johann Lay: Patch 2/3 is the libgcc additions: --with-libf7 selects which makefile-snips from libf7 to use. libgcc/ * config.host (tmake_file) [target=avr]: Add t-libf7, t-libf7-math, t-libf7-math-symbols as

[Ping^2][patch,avr, 0/3] Support 64-bit (long) double.

Ping #2 Georg-Johann Lay schrieb: Now that the avr backend can support 64-bit floats by means of configure-options --with-double= and --with-long-double=, this patch series adds some routines to support it. It's an ad-hoc, avr-specific implementation in assembly and GNU-C which is add

[Ping^2][patch,avr, 1/3] Support 64-bit (long) double: The gcc part.

Ping #2 Georg-Johann Lay schrieb: Am 16.12.19 um 17:40 schrieb Georg-Johann Lay: Patch 1/3 is the GCC changes: Documentation and new avr-specific configure options: --with-libf7 selects to which level double support from libf7 is added to libgcc. --with-double-comparison select what

Re: [patch,avr, 1/3] Support 64-bit (long) double: The gcc part.

Jeff Law schrieb: On Mon, 2019-12-16 at 17:43 +0100, Georg-Johann Lay wrote: Am 16.12.19 um 17:40 schrieb Georg-Johann Lay: Patch 1/3 is the GCC changes: Documentation and new avr-specific configure options: --with-libf7 selects to which level double support from libf7 is added to libgcc

Re: [patch][avr] PR92606: Disable -fipa-icf-variables because it generates wrong code.

Jeff Law schrieb: On Wed, 2019-12-18 at 16:30 +0100, Georg-Johann Lay wrote: Hi, this patch turns off -fipa-icf-variables because it generates wrong code like for PR92606. As there is no target hook that could decide whether such optimizations are obsolete, disable such optimizations

[patch,avr,applied]: Set -fsplit-wide-types-early.

This patch sets -fsplit-wide-types-early for avr as it appears that the old placement of that pass gives better code for that target. Applied as r380033. Johann * common/config/avr/avr-common.c (avr_option_optimization_table) [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.

[patch,avr,applied] Adjust help messages.

This patch unifies help screen messages. Johann -- AVR: Overhaul help screen gcc/ * config/avr/avr.opt: Overhaul help screen.diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt index ea35b7d5b4e..c3ca8379ee3 100644 --- a/gcc/config/avr/avr.opt +++ b/gcc/config/avr/avr.opt @@ -

[patch,avr,applied] Take into account -mtiny-stack in frame pointer adjustments

Applied this addendum to avr PR114100: When the frame pointer is adjusted and -mtiny-stack is set, then it is enough to adjust the low part of the frame pointer. Johann -- AVR: target/114100 - Factor in -mtiny-stack in frame pointer adjustments gcc/ PR target/114100 * config/a

[patch,avr,applied] Avoid magic numbers for register numbers.

There are some places where avr.cc uses magic numbers like 17 that are actually register numbers. This patch defines constants like REG_17 and uses them instead of the magic numbers when a register number is meant. Johann -- AVR: Use REG_ constants instead of magic numbers . There are some pl

[patch,avr,applied] ad target/92729: Remove last cc0 remains.

Removed the last cc0 remains. Johann -- AVR: ad target/92792 - Remove insn attribute "cc" and its (dead) uses. The backend has remains of cc0 condition code. Unfortunately, all that information is useless with CCmode, and their use was removed with the removal of NOTICE_UPDATE_CC in PR92729 w

[avr,patch,applied] ad target/114100 - Don't print unused frame pointer adjustments.

This addendum ports a corner case optimization from -mno-fuse-add to -mfuse-add: When a base register needs temporal adjustment, and the base is the frame pointer, then there are cases where the post-adjustment is not needed. Passes without new regressions on ATtiny40. Johann -- AVR: ad targe

[patch,avr,applied] Use more C++ ish coding style.

This is a no-op patch that uses some more C++ / C99 features if possible. Johann -- AVR: Use more C++ ish coding style. gcc/ * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED. Use bool in place of int for boolean logic (if possible). Move declarations to definitions (if pos

[patch,avr,applied] Improve output of insn "*insv.any_shift.".

Applied Roger's proposed improvements with some changes: Lengthy code is more convenient in avr.cc than in an insn output function, and it makes it easy to work out the exact instruction length. Moreover, the code can handle shifts with offset zero (cases of *and3 insns). Passed with no new reg

[patch,avr,applied] Add two RTL peepholes.

Register alloc may expand a 3-operand arithmetic X = Y o CST as X = CST X o= Y where it may be better to instead: X = Y X o= CST Johann -- AVR: Add two RTL peepholes. Register alloc may expand a 3-operand arithmetic X = Y o CST as X = CST X o= Y where it may be better to inst

[patch,avr.applied] Adjusted rtx costs of plus + zero_extend

Adjusted rtx costs of (plus (zero_extend (...)) reg). Johann -- AVR: Adjust rtx cost of plus + zero_extend. gcc/ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust rtx cost. diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 36995e05cbe..b87ae6a256d

[patch,avr,applied] Add an insn combine pattern for offset computation.

Computing uint16_t += 2 * uint8_t can occur when an offset into a 16-bit array is computed. Without this pattern is costs six instructions: A move (1), a zero-extend (1), a shift (2) and an addition (2). With this pattern it costs 4. Johann -- AVR: Add an insn combine pattern for offset com

[patch,avr,applied] Add some more cost computation

This adds cost computation for some insn combiner patterns and improves a few other nits. Johann -- AVR: Add cost computation for some insn combine patterns. gcc/ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for usum_widenqihi and add_zero_extend1. [MINU

[patch,avr,applied] Tweak xor insn constraints

xor insn allows some more values without the requirement of a scratch register. This patch adds new constraint alternative for such values. The output function avr_out_bitop already handles these cases, so no change is needed there. Johann -- avr.md - Tweak xor insn constraints. xor insn can

[patch,avr,applied] Adjust message for SIGNAL and INTERRUPT usage

Applied this patchlet for a more precise diagnostic. Johann -- AVR: Adjust message for SIGNAL and INTERRUPT usage gcc/ * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic for deprecated SIGNAL and INTERRUPT usage without respective header. diff --git a/gcc/config

[patch,avr,applied]: Rename %_misc specs.

This renames pecs like cc1_misc to cc1_rodata_in_ram to point out their purpose. Johann -- AVR: Rename device-specs %_misc to %_rodata_in_ram. gcc/ * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.

[patch, avr, applied] Specs always define __AVR_PM_BASE_ADDRESS__ when the core has it

This defines the spec always when the core has it, not only override it when it differs from the core's value. Johann -- AVR: Always define __AVR_PM_BASE_ADDRESS__ in specs provided the core has it. gcc/ * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always

[patch,avr,applied] PR113824: Fix multilib set for ATA5795

This device was in the wrong multilib set. Johann -- AVR: target/113824 - Fix multilib set for ATA5795. gcc/ PR target/113824 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4. * doc/avr-mmcu.texi: Rebuild.diff --git a/gcc/config/avr/avr-mcus.def b/gcc/config/

[patch,avr,applied] Tidy up gen-avr-mmcu-specs.cc

This patchlet tidies up gen-avr-mmcu-specs.cc. Some information was computed more than once, in different functions. The patch uses a new struct to pass around information. Johann AVR: Tidy up gen-avr-mmcu-specs.cc gcc/ * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New. (

[patch,avr,applied] Addendum to target/112944: Initialize FLMAP as needed

This code will link against parts of the startup code from AVR-LibC when it is needed to init bit-field FLMAP. Johann -- AVR: target/112944 - Addendum: Link code to initialize NVMCTRL_CTRLB.FLMAP For devices that see a part for the flash memory in the RAM address space, bit-field NVMCTRL_CTRLB

Re: [pushed] wwwdocs: gcc-14: Fix typo in AVR section

Am 14.02.24 um 01:40 schrieb Gerald Pfeifer: Note that is not part of current HTML standards; can we simply remove it? Hi Gerald, thanks for looking into this. The is not strictly needed, I just has the case that "-Wl,--defsym,__RODATA_FLASH_START__=32k" had a line-break in it. In addition

[patch,avr,applied] Fix PR target/113927: Simple code triggers a stack frame

Applied this patch Johann -- AVR: target 113927 - Simple code triggers stack frame for Reduced Tiny. The -mmcu=avrtiny cores have no ADIW and SBIW instructions. This was implemented by clearing all regs out of regclass ADDW_REGS so that constraint "w" never matched. This corrupted the subset

[patch,avr,applied] Minor improvements to option and attribute documentation.

Applied this patch. Johann -- AVR: Improve documentation for -mmcu=. gcc/ * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel". Note on complete device support. AVR: Add examples for ISR macro to interrupt attribute doc. gcc/ * doc/extend.texi (AVR Function Attri

[patch,avr,applied] Use @defbuiltin to document built-ins.

This patch uses @defbuiltin to document built-in functions so that the functions are listed in the index. Previously, @table @code was used. Johann -- AVR: extend.texi - Use @defbuiltin to document built-ins. gcc/ * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin inst

[patch,avr,applied] Use int types of exact width and signedness in built-ins prototypes

AVR: Use types of exact size and signedness in built-ins. The AVR built-ins used types like "int" or "char" that don't have exact signedness or type size which depend on -mint8 and -f[no-][un-]signed-char etc. As the built-ins are modelling machine instructions of given type sizes and signedness

[patch,avr] PR114100 : Better indirect addressing on reduced cores

A description of what the patch does follows in the commit message below. On ATmega128, there are no changes in test results. On ATtiny40 (reduced core) there are no new execution fails, but apart from that there is quite some noise in the delta: unsupported (memory full) -> pass unsupported

[avr,patch,applied] Remove some dead code

This code was dead in the block where it lived, because avr_adiw_reg_p() is only true when ADIW and SBIW are available -- which is not the case for AVR_TINY. Johann -- AVR: Dead code removal. gcc/ * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in an "if avr_adiw_

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