> -Original Message-
> From: Joern Rennecke [mailto:joern.renne...@embecosm.com]
> Sent: Monday, March 25, 2013 8:53 PM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH GCC]Relax the probability condition in CE pass when
> optimizing for code
/Os, ok for
trunk?
Thanks.
2013-03-26 Bin Cheng
PR target/56102
* config/arm/arm.c (thumb1_rtx_costs, thumb1_size_rtx_costs): Fix
rtx costs for SET/ASHIFT/ASHIFTRT/LSHIFTRT/ROTATERT patterns with
mult-word mode.Index: gcc/config/arm/arm.c
> -Original Message-
> From: Richard Earnshaw
> Sent: Tuesday, March 26, 2013 6:57 PM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH GCC/ARM]Fix rtx cost for Thumb1
>
> On 26/03/13 08:34, Bin Cheng wrote:
> > Hi,
> > As repor
.
Thanks.
2013-04-03 Bin Cheng
* rtl.h (AUTO_INC_DEC): Fix typo of HAVE_POST_MODIFY_DISP.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On
> Behalf Of Bin Cheng
> Sent: Wednesday, April 03, 2013 9:38 AM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH GCC]Fix typo in definition of macro AUTO_INC_DEC in rtl.h
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Wednesday, April 03, 2013 5:36 PM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH GCC]Fix typo in definition of macro AUTO_INC_DEC in
rtl.h
>
> On Wed, Apr
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On
> Behalf Of Bin Cheng
> Sent: Tuesday, March 26, 2013 4:33 PM
> To: 'Joern Rennecke'
> Cc: gcc-patches@gcc.gnu.org; 'Jeff Law'
> Subject: RE: [PAT
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On
> Behalf Of Bin Cheng
> Sent: Monday, March 25, 2013 3:15 PM
> To: gcc-patches@gcc.gnu.org
> Subject: FW: [PATCH GCC/pr56124] Don't prefer memory if the source
> -Original Message-
> From: Vladimir Makarov [mailto:vmaka...@redhat.com]
> Sent: Thursday, April 11, 2013 7:20 AM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH GCC/pr56124] Don't prefer memory if the source of load
> operation has side
only the exact one before branch.
For example:
mov r0, r1
//other insns does not kill r0
branch if (r0 == 0)
//other insns
Tested on thumb1, is it OK?
2013-04-18 Bin Cheng
* config/arm/arm.c (thumb1_reorg): Search for flag setting insn
before branch in same basic block
> -Original Message-
> From: Richard Earnshaw
> Sent: Thursday, April 18, 2013 5:25 PM
> To: Steven Bosscher
> Cc: Bin Cheng; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH ARM]Extend thumb1_reorg to save more comparison
> instructions
>
> On 18/04/13 09:20, St
iterations in iv_elimination_lt. Though I think this change isn’t necessary
for current code, it’s needed if we further relax iv elimination for cases
in which sign/unsigned conversion is involved.
Thanks,
bin
2014-07-17 Bin Cheng
* tree-ssa-loop-ivopts.c (iv_elimination_compare_lt
equality.
As a result, functions strip_wrap_conserving_type_conversions and
expr_equal_p can be removed now. A test case is also added to illustrate iv
elimination opportunity captured by this patch.
Thanks,
bin
2014-07-17 Bin Cheng
* tree-ssa-loop-ivopts.c (ivopts_data): New field
case, because for many loops iterating from "0"
(i.e., we have "a == 0"), the expression will be folded.
I also refactored period check from may_eliminate_iv into a single function
so that it can be reused.
Thanks,
bin
2014-07-17 Bin Cheng
Hi,
I reverted my patches about inlining memset on arm, it can't build glibc
properly. I will try to resolve the issue.
Sorry for the inconvenience.
Revert r212893:
PR target/55701
* config/arm/arm.md (setmem): New pattern.
* config/arm/arm-protos.h (struct tune_pa
introduced.
Is it OK?
Thanks
2011-11-07 Bin Cheng
PR rtl-optimization/50663
* cprop.c (bb_implicit): New global variable.
(insert_set_in_table): Add additional parameter, record implicit set
info.
(hash_scan_set): Add additional parameter
ithout any regression.
I also tested the patch on
arm-none-eabi+cortex-m0/arm-none-eabi+cortex-m3/i686-pc-linux and no
regressions introduced.
So is it OK?
Thanks
2012-08-13 Bin Cheng
* regcprop.c (copyprop_hardreg_forward_1) Notice copies in the form
of
subtract of ZERO.
Ping.
> -Original Message-
> From: Richard Earnshaw
> Sent: Thursday, July 26, 2012 9:19 PM
> To: Andrew Pinski
> Cc: Bin Cheng; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH]Remove duplicate check on BRANCH_COST in fold-const.c
>
> On 26/07/12 11:27, Andrew Pinsk
() / UNITS_PER_WORD;
I ran regression test with/without Os for cortex-m0 and everything is ok.
Ok for trunk and 4.7/4.6 release branches?
Thanks.
2012-09-04 Bin Cheng
PR target/45070
* config/arm/arm.c (thumb1_extra_regs_pushed): Handle return value
of size
less than 4 bytes
> > -Original Message-
> > From: Richard Earnshaw
> > Sent: Thursday, July 26, 2012 9:19 PM
> > To: Andrew Pinski
> > Cc: Bin Cheng; gcc-patches@gcc.gnu.org
> > Subject: Re: [PATCH]Remove duplicate check on BRANCH_COST in
> > fold-const.c
>
I measured the patch on CSiBE, about 600 bytes are saved for both O2 and
Os on
> cortex-m0 without any regression.
>
> I also tested the patch on
> arm-none-eabi+cortex-m0/arm-none-eabi+cortex-m3/i686-pc-linux and no
> regressions introduced.
>
> So is it OK?
>
> Thanks
&
> -Original Message-
> From: Ramana Radhakrishnan
> Sent: Tuesday, September 04, 2012 4:03 PM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] PR45070: Fix wrong epilogue code for cortex-m0/Os
>
> >
> > I ran regression test
Hi Richard,
Thanks very much for comments.
> > Ping?
> >
> > Hi Ramana, could you help me review this patch?
> > Hi Eric, Richard, could you help me review the change in regcprop.c?
>
> Subtraction of zero isn't canonical rtl though. Passes after peephole2
would
> be well within their rights to
> >
> > Yes, it may be feasible to rewrite the instruction in machine reorg
> > pass, rather than peephole2. But that need bigger change in ARM back
end.
> > Hi Ramana, Richard, what's your opinion on this?
> >
> > Thanks very much.
> >
> >
>
> I side with Richard on this one. The mid-end should
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On
> Behalf Of Bin Cheng
> Sent: Wednesday, September 05, 2012 7:01 PM
> To: Ramana Radhakrishnan
> Cc: gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] PR45070: Fix wr
Ping.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On
> Behalf Of Bin.Cheng
> Sent: Tuesday, September 04, 2012 11:20 PM
> To: Richard Guenther; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: Re: Ping^2: [PATCH]Remove duplicat
> -Original Message-
> From: Richard Guenther [mailto:richard.guent...@gmail.com]
> Sent: Tuesday, September 18, 2012 5:50 PM
> To: Bin Cheng
> Cc: Bin.Cheng; gcc-patches@gcc.gnu.org; Richard Earnshaw
> Subject: Re: Ping^2: [PATCH]Remove duplicate check on BRANCH_COST
> -Original Message-
> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
> Sent: Wednesday, September 05, 2012 6:09 AM
> To: Bin Cheng
> Cc: Ramana Radhakrishnan; 'Eric Botcazou'; gcc-patches@gcc.gnu.org
> Subject: Re: Ping: [PATCH GCC/ARM] Fi
section has been improved by only 0.05% on x86_64, not as obvious as
ARM/MIPS(0.1-0.2%).
I ran regression test on cortex-m3/cortex-m0/X86 with Os and everything was
fine.
Is it ok for upstream?
Thanks
2012-09-28 Bin Cheng
* common.opt (flag_ira_hoist_pressure): New.
* doc
to 0, so this patch is therefore just a
code cleanup and does not change behaviour in the compiler.
I built mipsel-elf cross compiler and compared newlib/libstdc++ compiled by
the patched/original compilers.
Is it OK?
Thanks
2012-07-26 Bin Cheng
* fold-const.c (fold_truth_andor
rt circuit when optimizing
for size on armv6-m processors. This brings us ~0.2% code size improvement
for CSiBE benchmark on cortex-m0.
Also tunes on other ARM processes could be followed.
No regression introduced, is it OK?
Thanks
2012-07-26 Bin Cheng
* config/arm/arm-cores.def (corte
> -Original Message-
> From: Ramana Radhakrishnan [mailto:ramana.radhakrish...@linaro.org]
> Sent: Thursday, July 26, 2012 6:45 PM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH arm]Define LOGICAL_OP_NON_SHORT_CIRCUIT in ARM back
end
>
> &g
Ping.
Hi, could anyone help me with this bug please, if you have time?
Any comments will be appreciated.
Thanks very much.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On
> Behalf Of Bin Cheng
> Sent: Friday, April 20,
> -Original Message-
> From: Ulrich Weigand [mailto:uweig...@de.ibm.com]
> Sent: Thursday, May 03, 2012 12:05 AM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, reload] Fix bug pr52804, RELOAD pass reloads wrong
> register on ARM for cortex-m0
> -Original Message-
> From: Ulrich Weigand [mailto:uweig...@de.ibm.com]
> Sent: Thursday, May 03, 2012 6:11 PM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, reload] Fix bug pr52804, RELOAD pass reloads wrong
> register on ARM for cortex-m0
.
gcc/ChangeLog:
2012-05-11 Bin Cheng
* tree-ssa-sink.c (pred_blocks, pred_visited): New static vars.
(init_sink_load): New function initializes pred_blocks and
pred_visited.
(free_sink_load): New function frees pred_blocks and pred_visited.
(sink_load_p): New
Hi,
I back-ported following changes to ARM/embedded-4_6-branch.
Thanks.
r188418 | amker | 2012-06-12 11:10:55 +0800 (二, 12 6月 2012) | 25 lines
Backport r180986 from mainline
2011-11-04 Eric Botcazou
PR c++/50608
* c-common.c (c_fully_fold_internal) : Call
f
Hi,
Bug PR46934 exists on all thumb1 targets, for example cortex-m0.
This patch removes "-march=armv5te" option for testcase pr46934.c,
allowing the test to be run on all thumb1 targets, not just armv5te.
Is it ok? Thanks.
gcc/testsuite/ChangeLog:
2011-09-15 Cheng Bin
* gcc.targe
Hi,
The linker should do endian swizzling at link-time according to "--be8"
option.
This patch modifies BE8_LINK_SPEC by adding cortex-m processors in the specs
string.
Since R-profile supports configurable big-endian instruction fetch, I didn't
include it here.
Is it ok? Thanks.
2011-09-15 Che
Thursday, September 15, 2011 6:46 PM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [ARM] pass "--be8" to linker when linking for M profile
>
> On 15/09/11 03:41, Bin Cheng wrote:
> > Hi,
> > The linker should do endian swizzling at link-time according
Thursday, September 15, 2011 6:46 PM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [ARM] pass "--be8" to linker when linking for M profile
>
> On 15/09/11 03:41, Bin Cheng wrote:
> > Hi,
> > The linker should do endian swizzling at link-time according
. Is it OK?
I think it is a bug of reload, and I understand reload pass should be rarely
touched,
so any comments are highly appreciated on this topic.
Thanks very much.
2012-04-20 Bin Cheng
PR target/52804
* reload1.c (reload_reg_reaches_end_p): Check whether successor
r
Hi,
Thanks for your review.
Here comes the 2nd version patch modified according to your comments. Is it
ok?
Also could you please commit it if ok because I have no write access?
The new patch is tested against x86-linux-gnu.
Thanks.
2011-11-15 Bin Cheng
PR rtl-optimization/50663
So no redundant insertions will be
generated in PRE pass.
Some discussion can be found at:
http://gcc.gnu.org/ml/gcc/2011-12/msg0.html
The patch is tested on x86 and arm-none-eabi, no failure introduced.
Is it OK?
Thanks
gcc/ChangeLog:
2011-12-21 Bin Cheng
Richard Gue
I tested the test case with "r13" which is another callee saved register,
I think it's ok to replace.
Thanks
> -Original Message-
> From: Ye Joey [mailto:joey.ye...@gmail.com]
> Sent: Friday, December 23, 2011 11:25 AM
> To: Bin Cheng
> Cc: gcc-patc
Also the test case does not write rbp, so I guess it's ok to use rbp too.
Thanks
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On
> Behalf Of Bin Cheng
> Sent: Friday, December 23, 2011 11:57 AM
> To: 'Y
manually.
Is it OK?
Thanks
gcc/ChangeLog:
2012-01-17 Bin Cheng
PR target/51835
* config/arm/arm.c (arm_libcall_uses_aapcs_base): Use correct ABI
for
__aeabi_d2iz/__aeabi_d2uiz in hard-float abi if only
single-precision
arithmetic is supported in hardware.
gcc
rm-eabi and x86, Is it OK?
Thanks.
gcc/ChangeLog:
2012-02-04 Bin Cheng
PR target/51867
* builtins.c (expand_builtin): Don't check
DECL_ASSEMBLER_NAME_SET_P.
gcc/testsuite/ChangeLog:
2012-02-04 Bin Cheng
PR target/51867
* testsuite/c-c++-common/dfp/sig
gcc/ChangeLog:
2012-02-08 Bin Cheng
Backport from mainline
2011-06-08 Julian Brown
* config/arm/arm.c (arm_libcall_uses_aapcs_base): Use correct ABI
for double-precision helper functions in hard-float mode if only
single-precision arithmetic is supported
Hi,
Backport mainline r183733 to ARM/embedded-4_6-branch.
The patch is already in gcc-4_6-branch, now commit to
ARM/embedded-4_6-branch.
gcc/ChangeLog.arm
2012-02-10 Bin Cheng
Backport from mainline.
2012-01-30 Bin Cheng
PR target/51835
* config/arm/arm.c
Ping...
Thanks
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On
> Behalf Of Bin Cheng
> Sent: Wednesday, February 08, 2012 4:29 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH ARM] backport r174803 from trunk to
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, February 13, 2012 7:37 PM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH ARM] backport r174803 from trunk to 4.6 branch
>
> On 08/02/12 08:29, Bin Cheng wrote:
> > Hi,
> &
401 - 452 of 452 matches
Mail list logo
