We could also check
TREE_THIS_NOTRAP here, but in that case we also could move stores,
whose value is not available readily, which we want to avoid. */
I think the comment above the change needs to be changed or extended slightly.
Thanks,
Andrew Pinski
>
> Thanks a lot!
> -Jiangnin
)
,On Sun, Mar 3, 2019 at 6:32 AM H.J. Lu wrote:
>
> For vector init constructor:
>
> ---
> typedef float __v4sf __attribute__ ((__vector_size__ (16)));
>
> __v4sf
> foo (__v4sf x, float f)
> {
> __v4sf y = { f, x[1], x[2], x[3] };
> return y;
> }
> ---
>
> we can optimize vector init construc
zero latency in some cases so being able to find them is
important.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.md (zero_extendsidi2_aarch64): Fix type
attrribute for uxtw.
diff --git a/gcc/config/aarch64/aar
with-empty-struct.H: New file.
> * g++.target/riscv/riscv.exp: New file.
This testcase seems generic, that is it has no ABI dependent values
attached to it.
Can it be moved to a more generic location instead? Maybe there are
other targets which get this incorrect also.
Thanks,
Andrew
On Tue, Apr 2, 2019 at 2:46 AM Ulrich Weigand wrote:
>
> Hello,
>
> the spu-elf target in GCC supports generating code for the SPU processors
> of the Cell Broadband Engine; it has been part of upstream GCC since 2008.
>
> However, at this point I believe this target is no longer in use:
> - There
xcept caller to a normal function.
>
> Of course I know to little about this.
>
> Btw, doesn't your check also prevent tail/sibling calls when
> the caller wraps it into a try { } catch (...) {}? Or does unwind
> not work in that case either?
>
> Btw, I'd
On Mon, Apr 1, 2019 at 5:12 PM wrote:
>
> From: Andrew Pinski
>
> Hi,
> The problem here is the token->val.node is not saved over
> a precompiled header for C++ operator. This can cause an
> internal compiler error as we tried to print out the spelling
> of the
On Thu, Mar 14, 2019 at 6:19 PM wrote:
>
> From: Andrew Pinski
>
> Hi,
> On OcteonTX2, ld1r and ld1 (with a single lane) are split
> into two different micro-ops unlike most other targets.
> This adds three extra costs to the cost table:
> ld1_dup: used for "ld
On Fri, Aug 18, 2017 at 12:17 PM Andrew Pinski wrote:
>
> Like https://gcc.gnu.org/ml/gcc-patches/2010-09/msg00060.html for
> PowerPC, we should do something similar for aarch64. This pattern
> does show up in SPEC CPU 2006 in astar but I did not look into
> performance improveme
le with no regressions, and testcases were
> saved. Is this ok for trunk?
forwprop was created orginally to something similar but this case is a
specific case of backwards prop (almost).
I wonder if it could be combined with that or as Richard mentioned,
jump threading.
Thanks,
Andre
s. So it is not
really doing a manual bisect per-say but rather it is doing a manual
bisect using prebuilt binaries and knowing which one comes before
which one.
One way is store the binaries based on the date that commit happened
instead. This is a bit more complex but still doable.
Thanks,
Andrew Pinski
>
>
> Segher
r GCC 9? I'd
> like to see us start acting like it is stage 4 soon!
I am in the process of getting OcteonTX2 patches in shape to submit.
I hope to have them in a good shape by end of next week.
Thanks,
Andrew Pinski
>
> James
>
> > 2019-01-15 Kyrylo Tkachov
> >
> > * config/aarch64/aarch64.c (ares_tunings): Define.
> > * config/aarch64/aarch64-cores.def (ares): Use the above.
On Tue, Jan 29, 2019 at 2:36 PM Steve Ellcey wrote:
>
> So the various tests that started failing with r265398 seem to need
> different fixes. This particular fix is for the
> gcc.target/aarch64/lsl_asr_sbfiz.c failure. The problem is that the
> instructions we are trying to match to *ashiftsi_e
On Mon, Jul 27, 2015 at 3:36 AM, James Greenhalgh
wrote:
> On Mon, Jul 27, 2015 at 10:52:58AM +0100, pins...@gmail.com wrote:
>> > On Jul 27, 2015, at 2:26 AM, Jiong Wang wrote:
>> >
>> > Andrew Pinski writes:
>> >
>> >>> On Fri, Jul 24, 2
Hi,
I committed a testcase that ICEs after applying "Gimple loop
splitting v2" patch to a GCC 6. The IV and the bounds were two
different types which was causing the ICE to happen.
Thanks,
Andrew Pinski
ChangeLog:
* gcc.c-torture/compile/20160802-1.c: New testcase.
Index: tests
regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.c (thunderx_vector_cost): New variable.
(thunderx_tunings): Use thunderx_vector_cost instead of generic_vector_cost.
Index: config/aarch64/aarch64.c
===
--- config
ThunderX. I used the tuning flags route so it can
be overridden if needed later on or if someone else wants to use the
same method for their core.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64-tuning-flags.def
On Fri, Aug 5, 2016 at 12:32 AM, Martin Liška wrote:
> On 08/05/2016 09:30 AM, Martin Liška wrote:
>> Hi.
>>
>> Sorry for the mistake with the enum, that was silly ;)
>> New patch version also handles the unnecessary braces.
>>
>> Martin
>
> I attached a wrong patch, sending the new one.
This br
On Mon, Jun 6, 2016 at 3:19 AM, Jan Hubicka wrote:
> Hi,
> while looking into profile mismatches introduced by the backward threading
> pass
> I noticed that the heuristics seems quite simplistics. First it should be
> profile sensitive and disallow duplication when optimizing cold paths. Second
On Fri, Aug 5, 2016 at 12:18 AM, Andrew Pinski wrote:
> Hi,
> On ThunderX, load (and store) pair that does a pair of two word
> (32bits) load/stores is slower in some cases than doing two
> load/stores. For some internal benchmarks, it provides a 2-5%
> improvement.
>
> Th
On Tue, Aug 9, 2016 at 2:42 PM, kugan wrote:
>
>
> On 09/08/16 23:43, kugan wrote:
>>
>> Hi,
>>
>> The test-case in PR72835 is failing with -O2 and passing with
>> -fno-tree-reassoc. It also passes with -O2 -fno-tree-vrp.
>>
>> diff of .115t.dse2 and .116t.reassoc1 for the c++ testcase is as
>> fo
On Thu, Aug 11, 2016 at 5:19 PM, Denys Vlasenko wrote:
>
>
> On 08/11/2016 10:59 PM, Andrew Pinski wrote:
>>
>> On Thu, Aug 11, 2016 at 1:49 PM, Denys Vlasenko
>> wrote:
>>>
>>> falign-functions=N is too simplistic.
>>>
>>> Ingo
On Fri, Aug 19, 2016 at 12:16 PM, Andy Ross wrote:
> We ran into this issue in the Zephyr project with our toolchain (gcc
> built with --enable-newlib). Basically GCC appears to be honoring a
> legacy requirement to give newlib a "long" instead of "int" for
> __INT32_TYPE__, which then leaks out
On Thu, Aug 18, 2016 at 1:14 AM, Richard Biener wrote:
>
> The following patch makes it possible to add statistic counters to
> update-ssa. Clone materialization ends up updating SSA form from
> a context with current_pass being NULL - wrapping materialize_all_clones
> into a pass fixes this.
>
>
On Mon, Aug 22, 2016 at 9:09 AM, Andy Ross wrote:
> The reproduction is straightforward. Just build any cross gcc with
> --enable-newlib (e.g. the one in the Zephyr SDK) and compile this
> (on any 32 or 64 bit 2's complement architecture) with newlib's
> headers.
>
> #include
>
> extern
On Mon, Aug 22, 2016 at 9:42 AM, Andy Ross wrote:
> Andrew Pinski wrote:
>> Why do you think the above code does not have a bug in it? int32_t
>> is long and changing it now is changing the ABI (especially for
>> C++).
>
> I don't follow. There's no cha
__always_inline__, __gnu_inline__, __artificial__))
The main reason is because in C++98 (and I can't remember if C++11),
template are not supposed to consider a static function being a
candidate (though GCC does not get it right is no reason why not to
change it).
Thanks,
Andrew Pinski
>
>
On Fri, Jun 3, 2016 at 3:51 AM, Wilco Dijkstra wrote:
> Increase loop alignment on Cortex cores to 8 and set function alignment to
> 16. This makes things consistent across big.LITTLE cores, improves
> performance of benchmarks with tight loops and reduces performance variations
> due to small
I don't understand why you need to have a direct
relationship to preprocessed macros to these values here.
Have your own lookup table inside your own JIT rather than a generic
way of doing it.
Having a generic way seems more incorrect way of doing it and even
says that the JIT is supposed t
On Tue, Jun 7, 2016 at 12:19 PM, Andrew Pinski wrote:
> On Mon, May 23, 2016 at 5:26 AM, Basile Starynkevitch
> wrote:
>> Hello All,
>>
>> As I explained in https://gcc.gnu.org/ml/jit/2016-q2/msg00042.html it is
>> difficult (or tricky without using dirty t
On Tue, Jun 7, 2016 at 12:22 PM, Andrew Pinski wrote:
> On Tue, Jun 7, 2016 at 12:19 PM, Andrew Pinski wrote:
>> On Mon, May 23, 2016 at 5:26 AM, Basile Starynkevitch
>> wrote:
>>> Hello All,
>>>
>>> As I explained in https://gcc.gnu.org/ml/jit/201
On Fri, Jun 17, 2016 at 7:29 AM, Martin Liška wrote:
> Hello.
>
> After we've recently applied various changes (fixes) to predict.c, SPEC2006
> shows that PRED_LOOP_EXIT value should be amended.
This caused a 1% decrease of performance on coremarks on
aarch64-linux-gnu on ThunderX.
Thanks,
Andr
On Fri, Oct 13, 2017 at 6:38 AM, Jan Hubicka wrote:
> Hi,
> this patch enables check that no edge probabilities are missing.
This caused a bootstrap failure on aarch64-linux-gnu with go enabled.
But I see you have disabled the code for now.
Just for reference the failure:
../../../gcc/libgo/go/u
On Mon, Sep 18, 2017 at 2:06 PM, Uros Bizjak wrote:
> On Tue, Sep 5, 2017 at 3:50 PM, Uros Bizjak wrote:
>> Revised patch, incorporates fixes from Alexander's review comments.
>>
>> I removed some implementation details from Alexander's description of
>> memory_blockage named pattern.
>>
>>
>> 20
On Thu, Oct 19, 2017 at 7:03 PM, Sandra Loosemore
wrote:
> This is the set of nios2 optimization patches that I've previously
> mentioned in these threads:
>
> https://gcc.gnu.org/ml/gcc/2017-10/msg00016.html
> https://gcc.gnu.org/ml/gcc-patches/2017-10/msg00957.html
>
> To give an overview of wha
On Tue, Oct 24, 2017 at 11:27 AM, Charles Baylis
wrote:
> In ILP32, GCC fails to merge pointer arithmetic into the addressing
> mode of a load instruction, as
> add w0, w0, w1, lsl 2
> ldr w0, [x0]
> is not equivalent to:
> ldr w0, [x0, w1, lsl 2]
>
> Shows the
ther optimization option, consider using
-Og (see Optimize Options) with -g. With no -O option at all, some
compiler passes that collect information useful for debugging do not
run at all, so that -Og may result in a better debugging experience.
Thanks,
Andrew Pinski
>
> 201
On Fri, Nov 3, 2017 at 12:11 AM, Wilco Dijkstra wrote:
> The Arm backend sets the default sched-pressure algorithm to
> SCHED_PRESSURE_MODEL. Benchmarking on AArch64 shows this
> speeds up floating point performance on SPEC - eg. CactusBSSN improves
> by ~16%. The gains are mostly due to less sp
On Tue, Jun 27, 2017 at 6:39 AM, Wilco Dijkstra wrote:
> This patch fixes a failure in gcc.target/aarch64/reload-valid-spoff.c
> triggered by https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01367.html -
> it supersedes https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01907.html
> as this fixes the root
1, slot_, (vec_->num++ - ix_) * sizeof (T));\
> ^
>
> There is nothing wrong with the code being warned here.
> While "struct btrace_insn" is trivial (has a user-provided default
> ctor), it is still tr
Hi,
After https://gcc.gnu.org/ml/gcc-cvs/2017-06/msg01066.html, there
was many crashes with -mcpu=thunderx2t99. This patch fixes the
crashes.
Committed after bootstrap and test.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Check prev_set
and
On Mon, Jun 12, 2017 at 12:56 AM, Tamar Christina
wrote:
> Hi All,
>
> this patch implements a optimization rewriting
>
> x * copysign (1.0, y) and
> x * copysign (-1.0, y)
>
> to:
>
> x ^ (y & (1 << sign_bit_position))
>
> This is done by creating a special builtin during matching and generate th
NSERT_EXPR).
Thanks,
Andrew Pinski
ChangeLog:
* tree-ssa-sccvn.c (vn_nary_op_eq): Check BIT_INSERT_EXPR's operand 1
to see if the types precision matches.
Index: tree-ssa-sccvn.c
===
--- tree-ssa-sccvn.c(revision 25015
On Wed, Jul 12, 2017 at 9:10 PM, Marc Glisse wrote:
> On Wed, 12 Jul 2017, Andrew Pinski wrote:
>
>> Hi,
>> Unlike most other expressions, BIT_INSERT_EXPR has an implicit
>> operand of the precision/size of the second operand. This means if we
>> have an integer c
double. In that they are passed via the floating
registers (sN, dN, qN).
Is this ok an ABI?
Is the patch ok? Bootstrapped and tested on aarch64-linux-gnu with
--enable-decimal-float with no regressions and all of the dfp
testcases pass.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/aarch64
On Thu, Jul 13, 2017 at 5:12 PM, Andrew Pinski wrote:
> Hi,
> This patch adds Decimal floating point support to aarch64. It is
> the base support in that since there is no hardware support for DFP,
> it just defines the ABI. The ABI I chose is that _Decimal32 is
> tre
On Mon, Jul 17, 2017 at 3:02 AM, Richard Biener
wrote:
> On Thu, Jul 13, 2017 at 6:18 AM, Andrew Pinski wrote:
>> On Wed, Jul 12, 2017 at 9:10 PM, Marc Glisse wrote:
>>> On Wed, 12 Jul 2017, Andrew Pinski wrote:
>>>
>>>> Hi,
>>>> Unlike most
On Thu, Jul 20, 2017 at 5:49 AM, Wilco Dijkstra wrote:
> In https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01125.html Jiong
> pointed out some addressing inefficiencies due to a recent change in
> regcprop (https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00775.html).
>
> This patch improves aarch64_l
On Wed, Jul 19, 2017 at 11:13 AM, Richard Biener
wrote:
> On July 19, 2017 6:10:28 PM GMT+02:00, Andrew Pinski
> wrote:
>>On Mon, Jul 17, 2017 at 3:02 AM, Richard Biener
>> wrote:
>>> On Thu, Jul 13, 2017 at 6:18 AM, Andrew Pinski
>>wrote:
>>>>
regressions.
Thanks,
Andrew Pinski
* tree-ssa-uninit.c (warn_uninitialized_vars): Don't warn about memory
accesses where the use is for the first operand of a BIT_INSERT.
Index: tree-ssa-uninit.c
===
--- tree-ssa-uninit.c (revision 2
On Fri, Jul 21, 2017 at 2:45 PM, Peter Bergner wrote:
> On 7/13/17 7:12 PM, Andrew Pinski wrote:
>> This patch adds Decimal floating point support to aarch64. It is
>> the base support in that since there is no hardware support for DFP,
>> it just defines the ABI. Th
were with GCC 6.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.c (thunderx_vector_cost): Fix vec_fp_stmt_cost.
Index: config/aarch64/aarch64.c
===
--- config/aarch64/aarch64.c(revision 250529)
+++ config/aarch64/aarch64
there.
Committed as obvious after a bootstrap/test on aarch64-linux-gnu with
no regressions.
Thanks,
Andrew Pinski
* config/aarch64/aarch64.c (thunderx_vector_cost): Decrease cost of
vec_unalign_load_cost and vec_unalign_store_cost.
Index: config/aarch64/aarc
>
> the pattern optimizes a BIT_FIELD_REF on a BIT_INSERT_EXPR by
> either extracting from the destination or the inserted value.
Note this optimization pattern was on my list to implement for
bit-field optimizations after lowering.
Thanks,
Andrew Pinski
>
> Bootstrap and regtest runnin
BIT_FIELD_REF ;
_9 = BIT_INSERT_EXPR <_8, _2, 2 (4 bits)>;
For the vector case, can't we write it as:
_1 = BIT_FIELD_REF ;
_2 = BIT_FIELD_REF ;
res_8 = {_1, _2};
And then have some match.pd patterns (which might get complex), to
rewrite that into VEC_PERM_EXPR?
The reason why I ask
same way as I had fixed PRE, by special casing
BIT_INSERT_EXPR due to the implicit operand.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* tree-ssa-scopedtables.c (hashable_expr_equal_p): Check
BIT_INSERT_EXPR's operand 1
to see i
"--target_board=unix/\{,-mcpu=thunderx,-mcpu=thunderx2t99,-march=armv8-a,-march=armv8.1-a,-march=armv8.2-a\}".
Thanks,
Andrew Pinski
ChangeLog:
* gcc.target/aarch64/_Float16_1.c: Skip if supplied a -mcpu= option.
* gcc.target/aarch64/_Float16_2.c: Likewise
* gcc.target/aarch64/_Float16_3.c
=unix/\{,-mcpu=thunderx,-mcpu=thunderx2t99,-march=armv8-a,-march=armv8.1-a,-march=armv8.2-a\}.
Thanks,
Andrew Pinski
ChangeLog:
* gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: Pass
-march=armv8-a+nolse, skip if -mcpu= is passed.
* gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c
/\{,-mcpu=thunderx,-mcpu=thunderx2t99,-march=armv8-a,-march=armv8.1-a,-march=armv8.2-a\}
and saw no failures.
Thanks,
Andrew Pinski
ChangeLog:
* gcc.target/aarch64/target_attr_10.c: Add -mcpu=generic.
* gcc.target/aarch64/target_attr_13.c: LIkewise.
* gcc.target/aarch64/target_attr_15.c: LIkewise
On Mon, Aug 7, 2017 at 1:36 PM, Michael Collison
wrote:
> This patch improves code generation for shifts with subtract instructions
> where the first operand to the subtract is equal to the bit-size of the
> operation.
>
>
> long f1(long x, int i)
> {
> return x >> (64 - i);
> }
>
> int f2(int
ou describe this a little bit more? What is going wrong here?
Is it because there is no red zone between the variables?
Also I noticed you are using .cc as the testcase file name, why don't
you use .C instead and then you won't need the other patch which you
just posted.
Thanks,
Andrew Pins
Hi,
This testcase checks the assembly and does an execute of it so it
needs --save-temps like the other testcases.
Committed as obvious after test on aarch64-linux-gnu with no regressions.
Thanks,
Andrew
ChangeLog:
* gcc.target/aarch64/vect-xorsign_exec.c: Add --save-temps to the
options passe
CPU implementer : 0x42
CPU architecture: 8
CPU variant : 0x0
CPU part: 0x516
CPU revision: 1
Thanks,
Andrew Pinski
ChangeLog:
* aarch64-option-extensions.def (rdma): Fix feature string to what
Linux prints out in /proc/cpuinfo.
Index: aarch64-option-extensions.def
regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.md (*frintz): New pattern.
testsuite/ChangeLog:
* testsuite/gcc.target/aarch64/floattointtofloat-1.c: New testcase.
commit 9cef5e196729df5a197b81b72192d687683a057a
Author: Andrew Pinski
Date: Thu Aug 17 22:31:15 2017 -0700
On Fri, Aug 25, 2017 at 10:43 AM, Charles Baylis
wrote:
> On 9 June 2017 at 15:13, Richard Earnshaw (lists)
> wrote:
>> On 21/02/17 16:54, charles.bay...@linaro.org wrote:
>>> From: Charles Baylis
>>>
>>> This patch adds support for modelling the varying costs of
>>> different addressing modes.
ew this looks good.
Thanks,
Andrew
>
> Regards,
> Renlin
>
>
> gcc/ChangeLog:
>
> 2017-08-31 Renlin Li
>
> PR target/63359
> * doc/extend.texi (AArch64Operandmodifers): New section.
>
>
> On 27/06/17 18:19, Renlin Li wrote:
>>
>
On Mon, Sep 4, 2017 at 7:28 AM, Tamar Christina wrote:
>> > vect__5.25_58 = VIEW_CONVERT_EXPR> intD.11>(vect__4.21_65);
>> > vect__5.25_57 = VIEW_CONVERT_EXPR> intD.11>(vect__4.22_63);
>> > vect__5.25_56 = VIEW_CONVERT_EXPR> intD.11>(vect__4.23_61);
>> > vect__5.25_55 = VIEW_CONVERT_EXPR>
On Fri, Aug 11, 2017 at 2:58 AM, Tamar Christina
wrote:
> Hi All,
>
> The inlining of lrint isn't valid in all cases on ILP32 when
> -fno-math-errno is used because an inexact exception is raised in
> certain circumstances.
>
> For ILP32 I now restrict the inlining only when -fno-trapping-math
> i
On Wed, Jul 26, 2017 at 6:46 AM, Wilco Dijkstra wrote:
> Remove the remaining uses of '*' from the movsi/di/ti patterns.
> Using '*' in alternatives is typically incorrect at it tells the register
> allocator to ignore those alternatives. So remove these from all the
> integer move patterns. Thi
On Sun, Sep 10, 2017 at 9:50 PM, Michael Collison
wrote:
> This patch improves the latency of code by eliminating two FP <-> integer
> register transfers.
>
> An example:
>
> float f1(float x)
> {
> int y = x;
> return (float)y;
> }
>
> Trunk generates:
>
> f1:
> fcvtzs w0, s0
>
On Tue, Jul 18, 2017 at 5:50 AM, Christophe Lyon
wrote:
> Hello,
>
> I've received a complaint that GCC for AArch64 would generate
> vectorized code relying on unaligned memory accesses even when using
> -mstrict-align. This is a problem for code where such accesses lead to
> memory faults.
>
> A
piling the cross compiler with
the new native compiler? Since this patch only touches the C++
front-end and only C++11 even that makes less sense. Are you sure
this was not a bug in qemu which is just happening showing up now?
Even then this makes little sense as the code generation between the
two revisions should not touch anything related to fortran.
Thanks,
Andrew Pinski
>
> Christophe
On Sat, May 6, 2017 at 8:03 AM, Jeff Law wrote:
> This is the 2nd of 3-5 patches to address pr78496.
>
> Jump threading will examine ASSERT_EXPRs as it walks the IL and record
> information from those ASSERT_EXPRs into the available expression and
> const/copies tables where they're later used to
On Sat, May 6, 2017 at 4:55 PM, Andrew Pinski wrote:
> On Sat, May 6, 2017 at 8:03 AM, Jeff Law wrote:
>> This is the 2nd of 3-5 patches to address pr78496.
>>
>> Jump threading will examine ASSERT_EXPRs as it walks the IL and record
>> information from those ASSE
On Fri, Dec 30, 2016 at 10:05 PM, Andrew Pinski wrote:
> Hi,
> Currently for the following function:
> int f(int a, int b)
> {
> return a + (b <<7);
> }
>
> GCC produces:
> add w0, w0, w1, lsl 7
> But for ThunderX 1, it is better if the instruction wa
On Sun, May 7, 2017 at 8:06 AM, Jeff Law wrote:
> On 05/06/2017 05:56 PM, Andrew Pinski wrote:
>>
>> On Sat, May 6, 2017 at 4:55 PM, Andrew Pinski wrote:
>>>
>>> On Sat, May 6, 2017 at 8:03 AM, Jeff Law wrote:
>>>>
>>>> This is the 2nd of
On Sun, May 7, 2017 at 10:26 PM, Andrew Pinski wrote:
> On Sun, May 7, 2017 at 9:30 PM, Jim Wilson wrote:
>> On 05/05/2017 12:23 AM, Richard Sandiford wrote:
>>>
>>> 2017-05-05 Richard Sandiford
>>>
>>> gcc/
>>>
ue with the aarch64 backend there.
See https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01800.html
I can't remember if the following patch was ever submitted or committed.
Here are my notes about this patch from the internal bug report we got
here at Cavium (back in 2013):
Switch tables are impleme
On Wed, May 10, 2017 at 10:26 AM, Ian Lance Taylor wrote:
> I have committed a large patch to update the Go frontend and libgo to
> the recent changes in the gofrontend repository. I had postponed
> merging changes during the GCC 7 release process. I am now merging
> all the changes that were pe
On Wed, May 10, 2017 at 5:37 PM, Andrew Pinski wrote:
> On Wed, May 10, 2017 at 10:26 AM, Ian Lance Taylor wrote:
>> I have committed a large patch to update the Go frontend and libgo to
>> the recent changes in the gofrontend repository. I had postponed
>> merging cha
On Tue, May 16, 2017 at 7:16 PM, Andi Kleen wrote:
> From: Andi Kleen
>
> When running creduce on an ICE substantial amounts of the total
> CPU time go to backtrace_qsort() (sorting dwarf of the compiler) for
> printing the backtrace of the ICE. When running a reduction we don't need the
> backtr
cktrace)
state = backtrace_create_state (NULL, 0, bt_err_callback, NULL);
int count = 0;
if (state != NULL)
backtrace_full (state, 2, bt_callback, bt_err_callback,
(void *) &count);
Changing onl
On Wed, May 24, 2017 at 12:29 PM, Jonathan Wakely wrote:
> On 24/05/17 14:50 -0400, Jason Merrill wrote:
>>
>> On Wed, May 24, 2017 at 10:20 AM, Jonathan Wakely
>> wrote:
>>>
>>> On 23/05/17 16:26 -0400, Jason Merrill wrote:
On Tue, May 23, 2017 at 2:00 PM, Jonathan Wakely
wr
On Wed, May 24, 2017 at 8:07 PM, Andrew Pinski wrote:
> On Wed, May 24, 2017 at 12:29 PM, Jonathan Wakely wrote:
>> On 24/05/17 14:50 -0400, Jason Merrill wrote:
>>>
>>> On Wed, May 24, 2017 at 10:20 AM, Jonathan Wakely
>>> wrote:
>>>>
&
On Thu, May 25, 2017 at 6:43 PM, Jerry DeLisle wrote:
> On 05/25/2017 02:57 PM, Thomas Koenig wrote:
>>
>> Hi everybody,
>>
>> I have committed the patch (with the corrections for the name)
>> as rev 248472.
>>
>> The infrastructure is in place, so we will be able to make
>> any fine-tuning easily
On Tue, Feb 28, 2017 at 1:53 AM, Maxim Kuvyrkov
wrote:
>> On Feb 20, 2017, at 5:38 PM, Kyrill Tkachov
>> wrote:
>>
>> Hi Maxim,
>>
>> On 30/01/17 11:24, Maxim Kuvyrkov wrote:
>>> This patch series improves -fprefetch-loop-arrays pass through small fixes
>>> and tweaks, and then enables it for s
On Mon, Jun 5, 2017 at 8:37 AM, Jan Hubicka wrote:
> Hi,
> I have committed the following fix.
I seeing the following error while building aarch64-elf:
/home/jenkins/workspace/BuildToolchainAARCH64_thunder_elf_upstream/toolchain/scripts/../src/gcc/shrink-wrap.c:
In function ‘void handle_simple_
Hi,
This patch adds -mcpu=thunderx2t99. Cavium has acquired the Vulcan
IP from Broadcom. I am keeping the old -mcpu=vulcan as backwards
compatible but renaming all of the structures to be based on the new
name of the chip. In the next few weeks, I am auditing the current
tuning and will be pos
X 2 CN99xx).
Thanks,
Andrew Pinski
ChangeLog:
* gcc.dg/atomic/c11-atomic-exec-5.c: Lower ITER_COUNT to 100
for AARCH64.
Index: testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
===
--- testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
Hi,
Currently for the following function:
int f(int a, int b)
{
return a + (b <<7);
}
GCC produces:
add w0, w0, w1, lsl 7
But for ThunderX 1, it is better if the instruction was split allowing
better scheduling to happen in most cases, the latency is the same. I
get a small improvement in
Ping?
On Sat, Dec 10, 2016 at 1:24 PM, Andrew Pinski wrote:
> On Thu, Nov 10, 2016 at 6:58 PM, Andrew Pinski wrote:
>> On Tue, Oct 25, 2016 at 3:25 PM, Matthias Klose wrote:
>>> On 07.10.2016 23:08, Andrew Pinski wrote:
>>>> Hi,
>>>> This patch adds
Just adding the changes that were done to add Cavium ThunderX to changes.html.
Committed as obvious.
Thanks,
Andrew
Index: changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-7/changes.html,v
retrieving revision 1.34
diff -u -p -r
On Wed, Jan 11, 2017 at 8:29 AM, Richard Earnshaw (lists)
wrote:
> On 06/01/17 12:11, Siddhesh Poyarekar wrote:
>> Hi,
>>
>> This patch documents the newly added flag in gcc 7 for the upcoming
>> Qualcomm Falkor processor core.
>>
>> Siddhesh
>>
>> Index: htdocs/gcc-7/changes.html
>> =
On Fri, Jan 13, 2017 at 10:24 PM, Jeff Law wrote:
>
>
> Given a block with more than one dead store, one of which is the last
> statement in the block, the existence debugging statements can change the
> generated code which is of course bad.
>
> The problem is when I moved the code to delete the
On Fri, Jan 6, 2017 at 3:47 AM, Jiong Wang wrote:
> On 11/11/16 18:22, Jiong Wang wrote:
>>
>> As described in the cover letter, this patch implements return address
>> signing
>> for AArch64, it's controlled by the new option:
>>
>>-msign-return-address=[none | non-leaf | all]
>>
>> "none" me
On Fri, Jan 20, 2017 at 1:58 PM, Martin Jambor wrote:
> Hi,
>
> when I fixed PR 78365 by streaming types of parameters that might not
> have been anywhere else, I forgot that I was holding them in non-GC
> memory and so I caused PR 79108. The following patch fixes it by
> putting ipa_param_descri
ks in SPEC CPU 2006 were neutral.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.c (thunderx2t99_addrcost_table): Improve cost table.
Index: gcc/config/aarch64/aarc
? Bootstrapped and tested on both ThunderX2 CN99xx and ThunderX
CN88xx with no regressions. I got a 2x improvement for 462.libquantum
on CN88xx, overall a 10% improvement on SPEC INT on CN88xx at -Ofast.
CN99xx's SPEC did not change.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64-pro
On Thu, Jan 26, 2017 at 4:38 PM, Segher Boessenkool
wrote:
> Scheduling should never move very expensive instructions to places they
> are executed more frequently. This patch fixes that, reducing the
> execution time of c-ray by over 40% (I tested on a BE Power7 system).
>
> Is there some existi
On Thu, Jan 26, 2017 at 3:17 PM, Martin Sebor wrote:
>> Hi,
>>
>> With this patch all my builds for aarch64/arm failed:
>> /gcc/gimple-ssa-sprintf.c: In function
>> ‘::fmtresult::format_floating(const::direc
>> tive&, tree_node*)’:
>> /gcc/gimple-ssa-sprintf.c:1643: error: ‘XFmode’ was not declare
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