Hi,
The comment in v2 is addressed. Tested again on both trunk and gcc-15.
Ok for trunk and gcc-15?
Changes in v3:
- Extract the constant VF check out.
Changes in v2:
- Remove the condition of dr_safe_speculative_read_required.
- Add a constant VF check.
Thanks,
Pengfei
-- >8 --
This patch
On Tue, 29 Jul 2025, Nathaniel Shead wrote:
> Tested on x86_64-pc-linux-gnu, OK for trunk if full bootstrap+regtest
> passes?
>
> -- >8 --
>
> For the sake of determining if there are other errors in user code to
> report early, many trait functions don't return error_mark_node if not
> called i
On 7/27/2025 8:51 PM, Mikael Morin wrote:
Le 27/07/2025 à 13:46, Yuao Ma a écrit :
On 7/27/2025 7:14 PM, Mikael Morin wrote:
Le 27/07/2025 à 11:37, Yuao Ma a écrit :
On 7/27/2025 5:19 PM, Mikael Morin wrote:
+gfc_charlen_type
+string_split (gfc_charlen_type stringlen, const CHARTYPE *str
> +(define_insn "@nds_vfwcvt_bf16"
> + [(set (match_operand:NDS_VWEXTBF 0 "register_operand"
> "=&vr")
> + (unspec_volatile:NDS_VWEXTBF
> + [(float_extend:NDS_VWEXTBF
> +(match_operand: 1 "register_operand" "
> vr"))]
> + UNSPEC_NDS_VFWCVTBF16
Am 29.07.25 um 15:56 schrieb Stefan Schulze Frielinghaus:
From: Stefan Schulze Frielinghaus
Targets hppa, m68k, pdp11, rx, sh, vax do not default to LRA. Since old
reload pass is still used, add option -mlra for those targets.
For hppa, register 0 cannot be used as a general register. Theref
> Am 29.07.2025 um 20:37 schrieb Pengfei Li :
>
> Hi,
>
> The comment in v2 is addressed. Tested again on both trunk and gcc-15.
>
> Ok for trunk and gcc-15?
>
Ok
Richard
> Changes in v3:
> - Extract the constant VF check out.
>
> Changes in v2:
> - Remove the condition of dr_safe_spe
> Am 29.07.2025 um 16:54 schrieb Pengfei Li :
>
> Hi,
>
> I have adjusted the test case as you suggested.
>
> Ok for trunk?
Ok
Thanks,
Richard
> Thanks,
> Pengfei
>
> -- >8 --
> This fixes a miscompilation issue introduced by the enablement of
> combined loop peeling and versioning. A t
> On Jul 28, 2025, at 12:48, Jakub Jelinek wrote:
>
> On Wed, Jul 23, 2025 at 05:59:22PM +, Qing Zhao wrote:
>> struct S {
>> int n;
>> int *p __attribute__((counted_by(n)));
>> } *f;
>> Int *g;
>> void setup (int **ptr, int count)
>> {
>> *ptr = __builtin_malloc (sizeof (int) * count);
>
This one is LGTM :)
On Tue, Jul 22, 2025 at 6:04 AM Jeff Law wrote:
>
>
>
> On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
> > This patch add basic support for the following XAndes ISA extensions:
> >
> > XANDESPERF
> > XANDESBFHCVT
> > XANDESVBFHCVT
> > XANDESVSINTLOAD
> > XANDESVPACKFPH
> > XANDESVDO
The failure of CI is unrelated, will commit it soon.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, July 29, 2025 11:23 AM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Chen, Ken ; Liu, Hongtao
; Li, Pan2
Jeff Law 於 2025年7月22日 週二 上午6:34寫道：
Hi Jeff,
Thanks your review.
> > +
> > +(define_insn "*nds_branch_imms7"
> > + [(set (pc)
> > + (if_then_else
> > + (match_operator 1 "equality_operator"
> > + [(match_operand:X 2 "register_operand" "r")
> > + (match_operand:X 3 "ad
r14-1902-g96c3539f2a3813 split TImode move with 2 DImode move, it's
supposed to optimize TImode in parameter/return since accoring to
psABI it's stored into 2 general registers.
But when TImode is not in parameter/return, it could create redundancy
in the PR.
The patch add a splitter to handle th
On Tue, Jul 22, 2025 at 6:40 AM Jeff Law wrote:
>
>
>
> On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
> > This extension defines instructions to perform scalar floating-point
> > conversion between the BFLOAT16 floating-point data and the IEEE-754
> > 32-bit single-precision floating-point (SP) data in
No worries, thanks!
在 2025/7/29 23:02, Kito Cheng 写道:
I thought I already merged that until today's RISC-V patchwork
meeting, committed to trunk :P
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, July 29, 2025 5:20 PM
> To: Alex Coplan ; Alice Carlotti
> ;
> pins...@gmail.com; ktkac...@nvidia.com; Richard Earnshaw
> ; Tamar Christina ;
> Wilco Dijkstra ; gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: [
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, July 29, 2025 5:20 PM
> To: Alex Coplan ; Alice Carlotti
> ;
> pins...@gmail.com; ktkac...@nvidia.com; Richard Earnshaw
> ; Tamar Christina ;
> Wilco Dijkstra ; gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: [PAT
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, July 29, 2025 1:43 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Alex Coplan ; Alice Carlotti
> ;
> pins...@gmail.com; ktkac...@nvidia.com; Richard Earnshaw
> ; Tamar Christina ;
> Wilco Dijkstra
> Subject: [PATCH] aarch64: Improve
On Tue, Jul 29, 2025 at 10:29:37PM +0200, Harald Anlauf wrote:
>
> - I am a little confused about the handling of the access specification.
> After the first "public :: g", NAG complains about the
>
> generic, public :: g ...
>
> and only allows
>
> generic :: g ...
>
> Then duplicate pub
> On 29 Jul 2025, at 18:41, Richard Sandiford wrote:
>
> This patch continues the work of making ACLE intrinsics use VNx16BI
> for svbool_t results. It deals with the floating-point forms of svcmp*.
>
> gcc/
> * config/aarch64/aarch64-sve.md (@aarch64_pred_fcm_acle)
> (*aarch64_pred_fcm_acle,
From: Pan Li
The unsigned avg ceil share the vaaddx.vx for the vx combine,
so add the test case to make sure it works well as expected.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/v
I checked, and GCC 14 (and others) uses https; not sure how http snuck
in here for the GCC 15 web pages?
Pushed.
Gerald
---
htdocs/gcc-15/index.html | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/htdocs/gcc-15/index.html b/htdocs/gcc-15/index.html
index d68da280..5670dd
> -Original Message-
> From: Richard Biener
> Sent: Monday, July 28, 2025 2:28 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Tamar Christina
>
> Subject: [PATCH] Record get_load_store_info results from analysis
>
> The following is a prototype-quality patch to make us record
Hi Kito,
Kito Cheng 於 2025年7月30日 週三 上午9:01寫道：
>
> > +(define_insn "@nds_vfwcvt_bf16"
> > + [(set (match_operand:NDS_VWEXTBF 0 "register_operand"
> > "=&vr")
> > + (unspec_volatile:NDS_VWEXTBF
> > + [(float_extend:NDS_VWEXTBF
> > +(match_operand: 1 "reg
Hi Harald,
>From a very quick perusal of the F2018 standard, I have come to the
tentative conclusion that:
(i) 'real module function realg (arg1, arg2)' is almost certainly a
correct requirement, although both flang-new and gfortran compile happily
without the module attribute; and
(ii) As far as
On Wed, Jul 30, 2025 at 11:45 AM H.J. Lu wrote:
>
> commit 4c80062d7b8c272e2e193b8074a8440dbb4fe588
> Author: H.J. Lu
> Date: Sun May 25 07:40:29 2025 +0800
>
> x86: Enable *mov_(and|or) only for -Oz
>
> disabled transformation from "movq $-1,reg" to "pushq $-1; popq reg" for
> -Oz. But fo
OK
(The zoned_time feature does work for this build config, and the error
should be present, but the { target cxx11_abi } selector doesn't consider
the "no dual ABI" case so the error doesn't match the dg-error. The
simplest fix is this patch.)
On Tue, 29 Jul 2025, 18:50 François Dumont, wrote
On Tue, 29 Jul 2025, 14:34 Björn Schäpers, wrote:
> From: Björn Schäpers
>
> I want assertions to be enabled, while compiling for bare metal and I
> don't have any printf variants at my hand (nor want I).
>
Then don't you want to use --disable-libstdcxx-verbose ?
> -- >8 --
> Mark it as weak
On Tue, 29 Jul 2025, Jakub Jelinek wrote:
> On Tue, Jul 29, 2025 at 11:20:25AM -0500, Robert Dubner wrote:
> > I removed the pick of 0eac9cfe, and I removed the pick of ed8761241ac529,
> > which had already been done by Thomas.
> >
> > I just applied the other 45 relevant commits, and pushed tha
Hi,
Just following up on this patch.
Would appreciate any feedback or suggestions on the implementation approach.
Thanks again!
Best,
Piyush
On 17/07/25 17:43, Piyush Raj wrote:
Hi,
This patch is an attempt to integrate the bpf-vmtest-tool with DejaGnu.
Instead of modifying gcc-dg specific p
r16-2614-g965564eafb721f had a typo where it would assume byte==0
rather than use the byte (offset) that was passed.
This fixes that typo and also fixes the comment since it is not just
about lowerpart subregs but all non-paradoxical subregs.
Pushed as obvious after bootstrap/test on x86_64-linux
r16-2590-ga51bf9e10182cf was not the correct fix for this in the end.
Instead a much simplier and localized fix is needed, just change the phi
that is being worked on with the new result and arguments that is from the
factored out operator.
This solves the issue of not having result in the IR and c
On Tue, Jul 22, 2025 at 11:13 PM Gerald Pfeifer wrote:
>
> On Tue, 15 Jul 2025, H.J. Lu wrote:
> >> This feels a bit complex to parse. How about something like
> >>
> >> + The new --enable-x86-64-mfentry configure option
> >> + makes -mfentry use __fentry__ instead
> >> + of mcount for
On 7/29/25 3:20 AM, Jakub Jelinek wrote:
Hi!
The PR13358 r0-92909 change changed the diagnostics on long long
in C++ (either with -std=c++98 or -Wlong-long), but unlike the
C FE we unfortunately warn even in the
__extension__ long long a;
etc. cases. The C FE in that case in
disable_extension_d
On 7/29/25 3:45 AM, Jakub Jelinek wrote:
Hi!
The P2843R3 Preprocessing is never undefined paper contains comments
that various compilers handle comma operators in preprocessor expressions
incorrectly and I think they are right.
In both C and C++ the grammar uses constant-expression non-terminal
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, July 29, 2025 4:33 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Alex Coplan ; Alice Carlotti
> ;
> pins...@gmail.com; ktkac...@nvidia.com; Richard Earnshaw
> ; Tamar Christina ;
> Wilco Dijkstra
> Subject: [PATCH] aarch64: Use VNx
From: Hans-Peter Nilsson
The change of default value for MAX_FIXED_MODE_SIZE was
approved contingent on not changing it for BPF, since it
could not be trivially ruled out to change the ABI for a
target. See thread at
"https://gcc.gnu.org/pipermail/gcc-patches/2025-July/690288.html";.
Since this
This patch removes unused local variables from three procedures.
gcc/m2/ChangeLog:
* gm2-compiler/M2GenGCC.mod (FoldBecomes): Remove all
local variables.
(CodeIndrX): Remove length.
Remove newstr.
* gm2-compiler/M2Range.mod (FoldTypeIndrX): Remove desType.
Hi,
I have updated the fix and the test case as you suggested.
Patch is re-tested on trunk and gcc-15. Ok for both trunk and gcc-15?
Thanks,
Pengfei
-- >8 --
This patch fixes a segmentation fault issue that can occur in vectorized
loops with an early break. When GCC vectorizes such loops, it ma
I thought I already merged that until today's RISC-V patchwork
meeting, committed to trunk :P
On Wed, Jun 25, 2025 at 9:21 PM Dongyan Chen
wrote:
>
> Automatically generate -mcpu and -mtune options in invoke.texi from
> the unified riscv-cores.def metadata, ensuring documentation stays in sync
>
On Mon, 28 Jul 2025, Jakub Jelinek wrote:
> On Sun, Jul 27, 2025 at 09:27:30PM -0400, Pietro Monteiro wrote:
> > On Mon, Jul 14, 2025, at 10:43 PM, Hans-Peter Nilsson wrote:
> > > Tested to fix build for MMIX (and to fix a few type-generic-builtin
> > > test-cases; c-c++-common/pr111309-1.c, gcc.d
On 2025-07-25 11:18, Uros Bizjak wrote:
On Thu, Jul 24, 2025 at 5:35 PM Artemiy Granat
wrote:
gcc/testsuite/ChangeLog:
* g++.dg/abi/regparm1.C: Use regparm attribute only if not in
64-bit mode.
* gcc.target/i386/20020224-1.c: Likewise.
* gcc.target/i386/pr10378
Hi Gerald,
Gerald Pfeifer wrote:
+ OpenACC 3.4: In Fortran, named constants (PARAMETER) used as
+ var in clauses are now accepted (and ignored as not being
+ required). The support for named constants has been added to the
+ specification and GCC for better compatibility with exi
Hi,
I have adjusted the test case as you suggested.
Ok for trunk?
Thanks,
Pengfei
-- >8 --
This fixes a miscompilation issue introduced by the enablement of
combined loop peeling and versioning. A test case that reproduces the
issue is included in the patch.
When performing loop peeling, GCC u
PING
> [PATCH] vect: Add missing skip-vector check for peeling with versioning
> [PR121020]
Le 29/07/2025 à 09:01, Paul Richard Thomas a écrit :
I haven't had time to track them down
but there are other places where code has had to be inserted to prevent
non-polymorphic references in a polymorphic way. I wonder if they cannot
be unified at some time?
Are there? gfc_get_class_from_e
PING
Ok for trunk and gcc-15?
> [PATCH] vect: Fix insufficient alignment requirement for speculative loads
> [PR121190]
This patch adds a token location parameter to CheckVariableAgainstKeyword
and dependants ensuring that the warning is generated from the
token associated with the variable rather than the end of the statement.
gcc/m2/ChangeLog:
PR modula2/121289
* gm2-compiler/M2Students.def (Chec
On Tue, 29 Jul 2025, Pengfei Li wrote:
> Hi Richi,
>
> > > > > > diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc
> > > > > > index 75e06ff28e6..8595c76eae2 100644
> > > > > > --- a/gcc/tree-vect-data-refs.cc
> > > > > > +++ b/gcc/tree-vect-data-refs.cc
> > > > > > @@ -2972,7
From: Björn Schäpers
I want assertions to be enabled, while compiling for bare metal and I
don't have any printf variants at my hand (nor want I).
-- >8 --
Mark it as weak, so users can provide their own assert handler.
libstc++-3/Changelog:
Mark __glibcxx_assert_fail as weak
If the index to svdupq_lane is variable, or is outside the range of DUP,
the fallback expansion is to convert to VNx2DI and use TBL. The problem
in this PR was that the conversion used subregs, and on big-endian
targets, a bitcast from VNx2DI to another element size requires a
REV[BHW] in the best
function_expander::get_reg_target didn't actually check for a register,
meaning that it could return a memory target instead. That doesn't
really matter for the current direct and indirect uses (svundef*,
svcreate*, and svset*) but it will for later patches.
Tested on aarch64-linux-gnu. OK to in
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the non-widening integer forms
of svcmp*. The handling of the PTEST patterns is similar to that
for the earlier svwhile* patch.
Unfortunately, on its own, this triggers a failure in the
pred_c
Patterns that fuse a predicate operation P with a PTEST use
aarch64_sve_same_pred_for_ptest_p to test whether the governing
predicates of P and the PTEST are compatible. Most patterns were also
written as define_insn_and_rewrites, with the rewrite replacing P's
original governing predicate with PT
There have been at least two distinct problems with using VNx8BI,
VNx4BI, and VNx2BI for predicates in which every bit is significant,
and which should therefore be represented as VNx16BI instead:
* PR121118: https://gcc.gnu.org/pipermail/gcc-patches/2025-July/691024.html
* PR121294: https://gcc.g
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svunpk* intrinsics.
gcc/
* config/aarch64/aarch64-sve.md (@aarch64_sve_punpk_acle)
(*aarch64_sve_punpk_acle): New patterns.
* config/aarch64/aarch64-sve-builtins-bas
The patterns for the svcmp_wide intrinsics used a VNx16BI
input predicate for all modes, instead of the usual .
That unnecessarily made some input bits significant, but more
importantly, it triggered an ICE in aarch64_sve_same_pred_for_ptest_p
when testing whether a comparison pattern could be fuse
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svcmp*_wide intrinsics.
Since the only uses of these patterns are for ACLE intrinsics,
there didn't seem much point adding an "_acle" suffix.
gcc/
* config/aarch64/aarch64.cc (@aar
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the floating-point forms of svcmp*.
gcc/
* config/aarch64/aarch64-sve.md (@aarch64_pred_fcm_acle)
(*aarch64_pred_fcm_acle, @aarch64_pred_fcmuo_acle)
(*aarch64_pred_fcmuo
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the predicate forms of svdup.
gcc/
* config/aarch64/aarch64-protos.h
(aarch64_emit_sve_pred_vec_duplicate): Declare.
* config/aarch64/aarch64.cc
(aarch64_emit_sv
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svac* intrinsics (floating-
point compare absolute).
gcc/
* config/aarch64/aarch64-sve.md (@aarch64_pred_fac):
Replace with...
(@aarch64_pred_fac_acle): ...this new
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the predicate forms of svdupq.
The general predicate expansion builds an equivalent integer vector
and then compares it with zero. This patch therefore relies on
the earlier patches to the com
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svmatch* and svnmatch*
intrinsics.
gcc/
* config/aarch64/aarch64-sve2.md (@aarch64_pred_):
Split SVE2_MATCH pattern into a VNx16QI_ONLY define_ins and a
VNx8HI_ONLY
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svpnext* intrinsics.
gcc/
* config/aarch64/iterators.md (PNEXT_ONLY): New int iterator.
* config/aarch64/aarch64-sve.md
(@aarch64_sve_): Restrict SVE_PITER pattern
Applied to trunk, thanks!
--Philipp.
On Tue, 29 Jul 2025 at 15:45, Jeff Law wrote:
>
>
>
> On 7/28/25 5:00 AM, Konstantinos Eleftheriou wrote:
> > While scanning the instructions and upon reaching an instruction that
> > doesn't satisfy the constraints that we have set, we were removing the
> >
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, July 29, 2025 1:08 PM
> To: Pengfei Li
> Cc: Tamar Christina ; Richard Biener
> ; gcc-patches@gcc.gnu.org; s...@gentoo.org
> Subject: Re: [PATCH] vect: Fix insufficient alignment requirement for
> speculative
> loads [PR121190]
Oh, I thought I fixed all those issue at
https://github.com/gcc-mirror/gcc/commit/35200a033dfcfe38ce5c066651f94e5475a40373,
thanks for fixing it :)
On Tue, Jul 29, 2025 at 9:40 PM Jeff Law wrote:
>
>
> On 7/28/25 9:39 AM, Christoph Müllner wrote:
> > Function riscv_ext_is_subset () uses structur
This should be present only on SLP nodes now. The RISC-V changes
are mechanical along the line of the SLP_TREE_TYPE changes. The
aarch64 changes are for removing vect_mem_access_type and gating
one problematical test with !m_costing_for_scalar (rather than
on a NULL node).
Bootstrapped and teste
On 7/28/25 5:00 AM, Konstantinos Eleftheriou wrote:
While scanning the instructions and upon reaching an instruction that
doesn't satisfy the constraints that we have set, we were removing the
already detected stores, but we were continuing adding stores from that
point onward. This was causin
> On Jul 28, 2025, at 17:39, Martin Uecker wrote:
>
> Am Montag, dem 28.07.2025 um 20:48 + schrieb Qing Zhao:
>>
>>> On Jul 28, 2025, at 16:09, Martin Uecker wrote:
>>>
>>> Am Montag, dem 28.07.2025 um 11:18 -0700 schrieb Yeoul Na:
> On Jul 28, 2025, at 10:27 AM, Qing Zha
The following is a prototype-quality patch to make us record the
get_load_store_info results from load/store analysis and re-use
them during transform. Rather than mass-replacing references to
variables I've kept the locals but made them read-only, only
adjusting a few elsval setters and adding a
On 7/29/25 7:41 AM, Richard Sandiford wrote:
This patch adds a new rule for distributing lowpart subregs through
ANDs, IORs, and XORs with a constant, in cases where one of the terms
then disappears. For example:
(lowart-subreg:QI (and:HI x 0x100))
simplifies to zero and
(lowart-subr
From: Stefan Schulze Frielinghaus
Targets hppa, m68k, pdp11, rx, sh, vax do not default to LRA. Since old
reload pass is still used, add option -mlra for those targets.
For hppa, register 0 cannot be used as a general register. Therefore,
use temporary registers r20 and r21 instead.
gcc/tests
This adderess TODO from the test file.
libstdc++-v3/ChangeLog:
* testsuite/std/format/ranges/format_kind.cc: New test.
Signed-off-by: Tomasz Kamiński
---
Tested on x86_64-linux. Pushed to trunk.
libstdc++-v3/testsuite/std/format/ranges/format_kind.cc | 4 +++-
1 file changed, 3 insert
On 7/28/25 3:38 AM, Konstantinos Eleftheriou wrote:
When having multiple stores with the same offset as the load, in the
case that we are eliminating the load, we were generating a mov instruction
for both of them, leading to the overwrite of the register containing the
loaded value.
This pat
Applied to trunk, thanks!
--Philipp.
On Tue, 29 Jul 2025 at 16:24, Jeff Law wrote:
>
>
>
> On 7/28/25 3:38 AM, Konstantinos Eleftheriou wrote:
> > When having multiple stores with the same offset as the load, in the
> > case that we are eliminating the load, we were generating a mov instruction
>
- if (len >= 3
+ if (!reassoc_insert_powi_p
+ && len >= 3
&& (!has_fma
/* width > 1 means ranking ops results in better
parallelism. Check curre
The following makes sure to not leak a set vectype on a stmt when
doing scalar IL costing as this can confuse vector cost models
which do not look at m_costing_for_scalar most of the time.
* tree-vectorizer.h (vector_costs::costing_for_scalar): New
accessor.
(add_stmt_cost)
> -Original Message-
> From: Pengfei Li
> Sent: Monday, July 21, 2025 12:07 PM
> To: gcc-patches@gcc.gnu.org
> Cc: rguent...@suse.de; s...@gentoo.org; Tamar Christina
> ; Pengfei Li
> Subject: [PATCH] vect: Add missing skip-vector check for peeling with
> versioning
> [PR121020]
>
> Thi
Reassoc carefully ranks operands to form reduction chains for
vectorization so we are careful to not apply any width related
changes in the early pass. Unfortunately we are not careful
enough. The following gates fma related re-ordering and also
the >= 3 ops tail "optimization" which is the culpr
Spencer Abson writes:
> This patch extends the expander for conditional smax, smin, add, sub, mul,
> min, max, and div to support partial SVE FP modes.
>
> If exceptions from undefined vector elements must be suppressed, this
> expansion converts the container-level predicate to an element-level o
PR121118 is about a case where we try to construct a predicate
constant using a permutation of a PFALSE and a WHILELO. The WHILELO
is a .H operation and its result has mode VNx8BI. However, the
permute instruction expects both inputs to be VNx16BI, leading to
an unrecognisable insn ICE.
VNx8BI i
On 7/29/25 4:34 PM, Juergen Christ wrote:
Loop peeling and minimal loop vectorization threshold prevented loop
vectorization in these examples. Adjust parameters in the test to
make the test pass.
Tested on s390x. Okay for main and gcc15?
Signed-off-by: Juergen Christ
PR testsuite/1
GCC doesn't support SME without SVE2, so the -march=armv8-a+ argument to
check_no_compiler_messages causes aarch64_asm__ok to return zero for SME
and any that implies it. This patch changes the baseline architecure to
armv9-a for these extensions.
The tests for ACLE SME2 intrinsics that require
It's needed by avx5124vnniw/avx5124fmaps which have been removed by
r15-656-ge1a7e2c54d52d0.
Ready push to trunk after passing regression test.
gcc/ChangeLog:
* config/i386/i386-modes.def: Remove VECTOR_MODES(FLOAT, 256)
and VECTOR_MODE (INT, SI, 64).
* config/i386/i386.c
On Mon, Jul 28, 2025 at 11:36 PM Martin Uecker wrote:
>
> Am Montag, dem 28.07.2025 um 17:45 -0700 schrieb Bill Wendling:
> > On Mon, Jul 28, 2025 at 4:29 PM Martin Uecker wrote:
> > > Am Montag, dem 28.07.2025 um 16:01 -0700 schrieb Bill Wendling:
> > > > On Mon, Jul 28, 2025 at 2:39 PM Martin U
Hi Jeff & Kito,
Thanks for all your review.
We'll Fixed these in next patch version.
Kito Cheng 於 2025年7月30日 週三 上午9:48寫道：
>
> On Tue, Jul 22, 2025 at 6:40 AM Jeff Law wrote:
> >
> >
> >
> > On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
> > > This extension defines instructions to perform scalar floa
On Tue, Jul 29, 2025 at 11:13 AM Yeoul Na wrote:
>
>
> On Jul 28, 2025, at 5:54 PM, Bill Wendling wrote:
>
> On Mon, Jul 28, 2025 at 4:52 PM Yeoul Na wrote:
>
>
> Could someone working on Linux answer my earlier question? Working on a
> compromise solution is one thing, but I’m trying to unders
On Wed, 23 Jul 2025, 1nfocalypse wrote:
> Implements Philox Engine (P2075R6) and associated tests.
>
> Implements additional feedback from v4 from Patrick Palka.
>
> While fixing the carry bit propagation, I noted an issue for the
> limb carry reset as well, which has been fixed, plus I snagged
Changes in v7:
* Clean up comments, inactive cases in tests.
* Restore symmetry of tests for bind_back and bind_front
* Add another test for type qualifier propagation, per review
* Add test verifying arguments are properly moved into the capture
object.
Changes in v6:
* Remove deletion of
Hi Paul!
Am 24.07.25 um 08:07 schrieb Paul Richard Thomas:
I forgot to include subroutine tests. Please find attached the patch with
updated testcases.
Paul
On Wed, 23 Jul 2025 at 17:53, Paul Richard Thomas <
paul.richard.tho...@gmail.com> wrote:
Hi All,
The attached implements the F2018 ge
On Tue, Jul 29, 2025 at 6:31 AM Richard Sandiford
wrote:
>
> gcc.target/aarch64/saturating_arithmetic_{1,2}.c expect w0 and w1 to
> be duplicated into vectors. The tests expected the duplication of w1
> to happen first, but the other order would be fine too. A later
> simplify-rtx.cc patch happe
An update on this version:
1. Sam reported two hangs when he tested the v7 with glibc and tinc.
I have fixed this issue in my local area.
2. David provided the patch for his latest change r16-2520-g6d9152659f4f6a
I have included into my latest version.
The v8 is under testing, will
On Tue, Jul 29, 2025 at 6:58 AM Stefan Schulze Frielinghaus
wrote:
>
> From: Stefan Schulze Frielinghaus
>
> Targets hppa, m68k, pdp11, rx, sh, vax do not default to LRA. Since old
> reload pass is still used, add option -mlra for those targets.
>
> For hppa, register 0 cannot be used as a gener
On Sun, 13 Jul 2025, Jonathan Wakely wrote:
> This is an anachronism: ChangeLog entries should never be part of the
> patch, because nobody should be editing them locally and including them
> in a commit. Whether you can self-approve or not isn't relevant.
Nice. In general we should be looking at
On Tue, Jul 29, 2025 at 7:40 AM Alfie Richards wrote:
>
> Hi All,
>
> Quick fixup for the gating (s/&&/|/) for an error I made.
>
> Only needed for trunk as the intrinsics were only added recently.
>
> Bootstrapped and reg tested on Aatch64.
Ok. Though this seems obvious since AARCH64_FL_SME2 and
The patch is trying to unroll the vectorized loop when there're
FMA/DOT_PRDO_EXPR reductions, it will break cross-iteration dependence
and enable more parallelism(since vectorize will also enable partial
sum).
When there's gather/scatter or scalarization in the loop, don't do the
unroll since the
commit 4c80062d7b8c272e2e193b8074a8440dbb4fe588
Author: H.J. Lu
Date: Sun May 25 07:40:29 2025 +0800
x86: Enable *mov_(and|or) only for -Oz
disabled transformation from "movq $-1,reg" to "pushq $-1; popq reg" for
-Oz. But for legacy integer registers, the former is 4 bytes and the
latter
Hi,
okay to push? Confirmed that I didn't break anything by running `make html`.
Filip Kastl
-- 8< --
This patch changes two things. Firstly, we document
-fdump-rtl--graph and other such options under -fdump-tree.
At least write a remark about this under -fdump-rtl. Secondly, the
documentati
Thoughts? Another suggestion raised on the PR was to just make this a
warning or some other non-fatal diagnostic (I suppose not attached to
any particular warning option?) and continue translation; I'm not
particularly fussed either way.
Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for t
On Tue, 29 Jul 2025, Robin Dapp wrote:
> > - if (len >= 3
> > + if (!reassoc_insert_powi_p
> > + && len >= 3
> > && (!has_fma
> > /* width > 1 means ranking ops results in better
> > parallelism. Check current value to avoi
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