Re: [PATCH] gcc: add trigonometric pi-based functions as gcc builtins

2025-05-18 Thread Yuao Ma
Hi Jakub, Thank you for your suggestion. I actually learned from your earlier patch (https://gcc.gnu.org/cgit/gcc/commit?id=7f940822) and had already planned to update tree-call-cdce.cc when handling these builtins. Your guidance is much appreciated! Best regards, Yuao _

Re: [to-be-committed][RISC-V] Avoid setting output object more than once in IOR/XOR synthesis

2025-05-18 Thread Jeff Law
On 5/18/25 8:53 AM, Mark Wielaard wrote: Hi Jeff, On Thu, May 15, 2025 at 10:11:19PM -0600, Jeff Law wrote: This has been tested in my tester and is currently bootstrapping on my BPI. Waiting on data from the pre-commit tester before moving forward... It looks like the Sourceware p550 and

Re: [PATCH] Partially lift restriction from loc_list_from_tree_1

2025-05-18 Thread Eric Botcazou
> OK. Thanks. > Btw, can we try to add a "guality" for gnat.dg? Or are you making sure to > add coverage to the gdb testsuite? Yes, the GDB testsuite will get a testcase. -- Eric Botcazou

Re: [PATCH] phiopt: Use mark_lhs_in_seq_for_dce instead of doing it inline

2025-05-18 Thread Richard Biener
> Am 18.05.2025 um 08:26 schrieb Andrew Pinski : > > Right now phiopt has the same code as mark_lhs_in_seq_for_dce > inlined into match_simplify_replacement. Instead let's use the > function in gimple-fold that does the same thing. > > Bootstrapped and tested on x86_64-linux-gnu. Ok Richard

[PATCH] match: Remove valueize_condition argument from gimple_extra template

2025-05-18 Thread Andrew Pinski
After r15-4791-gb60031e8f9f8fe, the valueize_condition argument becomes unused. I didn't notice that as there was -Wno-unused option being added while compiling gimple-match-exports.cc. This removes that too as there are no unused warnings. gcc/ChangeLog: * Makefile.in (gimple-match-expor

[PATCH] match: Undo maybe_push_res_to_seq in some cases [PR120331]

2025-05-18 Thread Andrew Pinski
While working on improving forwprop and removal of forward_propagate_into_gimple_cond/forward_propagate_into_comparison, I came cross a case where we end up with SSA_NAME in the resulting gimple_match_op and one statement in the sequence. This was the result of simplification of: ``` _3 = MIN_EXPR

Re: Subject: [PATCH] cobol: gcobc wrapper fixes and additions

2025-05-18 Thread James K. Lowden
On Sat, 5 Apr 2025 00:36:48 +0200 Simon Sobisch wrote: > * defaults to dialect GNU (gnucobol) > * more ibm and strict dialects supported > * Implemented -A, -Q, -E > * support known alias "-debug" for "--debug" > * fix -P, -T and -W consuming source files > * deduce output file name, as done by c

Re: cobol.1 fix for not using underscores in intrinsic function names

2025-05-18 Thread James K. Lowden
On Wed, 9 Apr 2025 23:12:39 +0200 Simon Sobisch wrote: > just stumbled over this and only have a mail client running, so... > patch as text. The change is in all those cases: change _ (likely > parsed from the parser or similar) to -. > > Kind regards, > Simon > > > > -BASECONVERT BIT_OF BIT_

[COMMITTED] Regenerate cobol/lang.opt.urls

2025-05-18 Thread Mark Wielaard
The Cobol frontend lang.opt got -M added, but lang.opt.urls wasn't regenerated. Fixes: 92b6485a75ca ("cobol: Eliminate exception "blob"; streamline some code generation.") gcc/cobol/ChangeLog: * lang.opt.urls: Regenerated. --- gcc/cobol/lang.opt.urls | 3 +++ 1 file changed, 3 insertio

Re: [PATCH v2 1/2] emit-rtl: Allow extra checks for paradoxical subregs [PR119966]

2025-05-18 Thread Dimitar Dimitrov
On Fri, May 16, 2025 at 06:01:43PM +0100, Richard Sandiford wrote: > Dimitar Dimitrov writes: > > When a paradoxical subreg is detected, validate_subreg exits early, thus > > skipping the important checks later in the function. > > > > Fix by continuing with the checks instead of declaring early t

Re: [PATCH v2 0/7] Remove -mavx10.1-256/512 and -mno-evex512

2025-05-18 Thread Hongtao Liu
On Wed, May 14, 2025 at 3:29 PM Haochen Jiang wrote: > > Hi all, > > This is the v2 patch to remove -mavx10.1/256-512 and -mno-evex512. I suppose > this time all the patches will not be held due to size. > > As mentioned in GCC 15, we will remove -mavx10.1-256/512 and -mno-evex512 > options in GCC

[PATCH v3] Extend vect_recog_cond_expr_convert_pattern to handle REAL_CST

2025-05-18 Thread liuhongt
Changed, here's the updated patch I'm going to check in. REAL_CST is handled if it can be represented in different floating point types without loss of precision or under fast math. gcc/ChangeLog: PR tree-optimization/103771 * match.pd (cond_expr_convert_p): Extend the match to h

[PATCH] [AUTOFDO] Don't scale bb_count with ipa_count when ipa_count is zero but count_max is not

2025-05-18 Thread liuhongt
From: "hongtao.liu" AutoFDO profile is a scaled profile, as a result, 0 sample does not mean never executed. especially there's profile from function body. Prevent combine_with_ipa_count·(ipa_count) from zeroing all bb->count. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} OK for trunk

[PATCH] RISC-V: Rename conflicting variables in gen-riscv-ext-texi.cc

2025-05-18 Thread Songhe Zhu
From: zhusonghe The variables `major` and `minor` in `gen-riscv-ext-texi.cc` conflict with the macros of the same name defined in ``, which are exposed when building with newer versions of GCC on older Linux distributions (e.g., Ubuntu 18.04). To resolve this, we rename them to `major_version` an

Re: [PATCH] RISC-V: Add new operand constraint: cR

2025-05-18 Thread Kito Cheng
Committed :) On Sat, May 17, 2025 at 9:36 PM Jeff Law wrote: > > > > On 5/14/25 9:20 PM, Kito Cheng wrote: > > This commit introduces a new operand constraint `cR` for the RISC-V > > architecture, which allows the use of an even-odd RVC general purpose > > register > > (x8-x15) in inline asm. >

[PATCH v1 0/8] RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost

2025-05-18 Thread pan2 . li
From: Pan Li This patch would like to introduce the combine of vec_dup + vsub.vv into vsub.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 15 in test. There will be two cases for the combine: Case 0: | .

[PATCH v1 1/8] RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost

2025-05-18 Thread pan2 . li
From: Pan Li This patch would like to combine the vec_duplicate + vrub.vv to the vrsub.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if the

[PATCH v1 4/8] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 15

2025-05-18 Thread pan2 . li
From: Pan Li Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Add asm check for vrsub with GR

[PATCH v1 2/8] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0

2025-05-18 Thread pan2 . li
From: Pan Li Add asm dump check and run test for vec_duplicate + vrsub.vv combine to vrsub.vx. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add vrsub asm check. *

[PATCH v1 5/8] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0

2025-05-18 Thread pan2 . li
From: Pan Li Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add asm check for vrsub case 1

[PATCH v1 8/8] RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC]

2025-05-18 Thread pan2 . li
From: Pan Li Tweak the asm check with define T uint8_t for adding more vx test easily, as well as less possibility to make mistake. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i

[PATCH v1 7/8] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

2025-05-18 Thread pan2 . li
From: Pan Li Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check for vrsub with GR

[PATCH v1 6/8] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 1

2025-05-18 Thread pan2 . li
From: Pan Li Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Add asm check for vrsub with GR

[PATCH v1 3/8] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1

2025-05-18 Thread pan2 . li
From: Pan Li Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Add vrsub asm dump check.

Re: [PATCH] RISC-V: Support Zilsd code gen

2025-05-18 Thread Kito Cheng
On Sat, May 17, 2025 at 9:34 PM Jeff Law wrote: > > > > On 5/14/25 9:14 PM, Kito Cheng wrote: > > This commit adds the code gen support for Zilsd, which is a > > newly added extension for RISC-V. The Zilsd extension allows > > for loading and storing 64-bit values using even-odd register > > pairs

Re: [PATCH] RISC-V: Add zvfbfa and zvfofp8min intrinsic.

2025-05-18 Thread Kito Cheng
Seems like you don't really add new intrinsics for those two new extensions? Also our policy is only to add extensions when they are ratified. I am happy to review the patch anyway, but just remind you we won't accept that until it is ratified :) On Mon, Apr 14, 2025 at 4:25 PM Dongyan Chen wrot

[PATCH] libstdc++: Implement C++23 P1659R3 starts_with and ends_with

2025-05-18 Thread Patrick Palka
Tested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- libstdc++-v3/ChangeLog: * include/bits/ranges_algo.h (__starts_with_fn, starts_with): Define. (__ends_with_fn, ends_with): Define. * include/bits/version.def (ranges_starts_ends_with): Define.

[PATCH] RISC-V: Rename conflicting variables in gen-riscv-ext-texi.cc

2025-05-18 Thread Songhe Zhu
From: zhusonghe The variables `major` and `minor` in `gen-riscv-ext-texi.cc` conflict with the macros of the same name defined in ``, which are exposed when building with newer versions of GCC on older Linux distributions (e.g., Ubuntu 18.04). To resolve this, we rename them to `major_version` an

RE: [PATCH][RFC] Allow the target to request a masked vector epilogue

2025-05-18 Thread Tamar Christina
> -Original Message- > From: Richard Biener > Sent: Friday, May 16, 2025 11:35 AM > To: gcc-patches@gcc.gnu.org > Cc: Richard Sandiford ; Tamar Christina > > Subject: [PATCH][RFC] Allow the target to request a masked vector epilogue > > Targets recently got the ability to request the vec

[r16-372 Regression] FAIL: gfortran.dg/specifics_1.f90 -O3 -g execution test on Linux/x86_64

2025-05-18 Thread haochen.jiang
On Linux/x86_64, 064cac730f88dc71c6da578f9ae5b8e092ab6cd4 is the first bad commit commit 064cac730f88dc71c6da578f9ae5b8e092ab6cd4 Author: Jan Hubicka Date: Sun May 4 10:52:35 2025 +0200 Improve maybe_hot handling in inliner heuristics caused FAIL: gcc.dg/tree-ssa/gen-vect-28.c scan-tree-

[r16-385 Regression] FAIL: gcc.dg/vect/vect-simd-clone-18d.c scan-tree-dump-times vect "[\\n\\r] [^\\n]* = foo\\.simdclone" 2 on Linux/x86_64

2025-05-18 Thread haochen.jiang
On Linux/x86_64, c9982eec2d3edc5306291d4628f08825ba46d483 is the first bad commit commit c9982eec2d3edc5306291d4628f08825ba46d483 Author: Thomas Schwinge Date: Mon May 5 10:21:35 2025 +0200 vect-simd-clone-1[6-8][cd].c: Expect in-branch clones for x86: Fix target selector syntax caused

[r16-645 Regression] FAIL: gcc.target/i386/vect-epilogues-5.c scan-tree-dump-times vect "loop vectorized using 64 byte vectors" 2 on Linux/x86_64

2025-05-18 Thread haochen.jiang
On Linux/x86_64, af7b84d0d02ffa23e4843e9555a888c9e80bd9b5 is the first bad commit commit af7b84d0d02ffa23e4843e9555a888c9e80bd9b5 Author: Richard Biener Date: Wed May 14 16:45:08 2025 +0200 Enhance -fopt-info-vec vectorized loop diagnostic caused FAIL: gcc.target/i386/vect-epilogues-4.c

[r16-517 Regression] FAIL: gcc.target/i386/pr78794.c scan-assembler pandn on Linux/x86_64

2025-05-18 Thread haochen.jiang
On Linux/x86_64, 993aa0bd28722c7f01fb8310f1c79814aef217ed is the first bad commit commit 993aa0bd28722c7f01fb8310f1c79814aef217ed Author: Jan Hubicka Date: Sat May 10 22:23:48 2025 +0200 i386: Fix some problems in stv cost model caused FAIL: gcc.target/i386/avx512vl-stv-rotatedi-1.c scan

[r16-531 Regression] FAIL: gcc.target/i386/vect-shiftv8qi.c scan-assembler-times psllw 2 on Linux/x86_64

2025-05-18 Thread haochen.jiang
On Linux/x86_64, 37e61c793c1b22bdcfbf142cd6086da2745be596 is the first bad commit commit 37e61c793c1b22bdcfbf142cd6086da2745be596 Author: Jan Hubicka Date: Sun May 11 23:49:11 2025 +0200 i386: Fix move costs in vectorizer cost model. caused FAIL: gcc.target/i386/pr108938-3.c scan-assembl

Re: [r16-372 Regression] FAIL: gfortran.dg/specifics_1.f90 -O3 -g execution test on Linux/x86_64

2025-05-18 Thread Andrew Pinski
On Sun, May 18, 2025 at 11:19 PM haochen.jiang wrote: > > On Linux/x86_64, > > 064cac730f88dc71c6da578f9ae5b8e092ab6cd4 is the first bad commit > commit 064cac730f88dc71c6da578f9ae5b8e092ab6cd4 > Author: Jan Hubicka > Date: Sun May 4 10:52:35 2025 +0200 > > Improve maybe_hot handling in inl

Re: [PATCH] [PR120276] regcprop: Replace partial_subreg_p by ordered_p && maybe_lt

2025-05-18 Thread Jennifer Schmitz
> On 16 May 2025, at 18:54, Richard Sandiford wrote: > > External email: Use caution opening links or attachments > > > Jennifer Schmitz writes: >> [PATCH] [PR120276] regcprop: Return from copy_value for unordered modes >> >> The ICE in PR120276 resulted from a comparison of VNx4QI and V8QI

Re: [PATCH v2] driver: Fix multilib_os_dir and multiarch_dir for those target use TARGET_COMPUTE_MULTILIB

2025-05-18 Thread Kito Cheng
Hi Jin: Thanks for heads up:) Hi Jeff: I've rebased that on the trunk and everything seems right, do you think it's OK for the trunk? On Mon, May 19, 2025 at 2:35 PM Jin Ma wrote: > On Sun, 16 Mar 2025 11:23:07 -0600, Jeff Law wrote: > > > > > > On 3/10/25 2:26 AM, Kito Cheng wrote: > > > Th

Re: [PATCH] RISC-V: Support Zilsd code gen

2025-05-18 Thread Kito Cheng
committed to trunk :) On Mon, May 19, 2025 at 11:49 AM Kito Cheng wrote: > On Sat, May 17, 2025 at 9:34 PM Jeff Law wrote: > > > > > > > > On 5/14/25 9:14 PM, Kito Cheng wrote: > > > This commit adds the code gen support for Zilsd, which is a > > > newly added extension for RISC-V. The Zilsd ex

[to-be-committed][RISC-V] Avoid multiple assignments to output object

2025-05-18 Thread Jeff Law
This is the next batch of changes to reduce multiple assignments to an output object. This time I'm focused on splitters in bitmanip.md. This doesn't convert every case. For example there is one case that is very clearly dependent on eliminating mvconst_internal and adjustment of a splitter

Re: [to-be-committed][RISC-V] Avoid setting output object more than once in IOR/XOR synthesis

2025-05-18 Thread Mark Wielaard
Hi Jeff, On Thu, May 15, 2025 at 10:11:19PM -0600, Jeff Law wrote: > This has been tested in my tester and is currently bootstrapping on > my BPI. Waiting on data from the pre-commit tester before moving > forward... It looks like the Sourceware p550 and spacemit-x60 builders do flag a bootstrap

[PATCH] cobol: Minor grammatical correction as the first issue.

2025-05-18 Thread Hugo Marrassé
Hi everyone, I started studying GCC and the new COBOL part when I noticed something that looked like a typing error. I thought it would make a good first issue to report, so here is my patch. Here is the patch From 4f7fd1e08151df26b37a5a1f2cbce2623f214361 Mon Sep 17 00:00:00 2001 From: pulk66-s

[PATCH v1 4/6] libstdc++: Add tests for layout_right.

2025-05-18 Thread Luc Grosheintz
Adds tests for layout_right and for the parts of layout_left that depend on layout_right. libstdc++-v3/ChangeLog: * testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add tests for layout_stride. * testsuite/23_containers/mdspan/layouts/ctors.cc: Add tests for

[PATCH v1 2/6] libstdc++: Add tests for layout_left.

2025-05-18 Thread Luc Grosheintz
Implements a suite of tests for the currently implemented parts of layout_left. The individual tests are templated over the layout type, to allow reuse as more layouts are added. libstdc++-v3/ChangeLog: * testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: New test. * tes

[PATCH v1 0/6] Implement layouts from mdspan.

2025-05-18 Thread Luc Grosheintz
Technically, this is the second iteration of these patches. Previous discussion can be found here: https://gcc.gnu.org/pipermail/libstdc++/2025-May/061350.html` The implementation of `layout_stride::mapping::is_exhaustive` needs to be discussed, because for empty extents, the standard seems to re

[PATCH v1 3/6] libstdc++: Implement layout_right from mdspan.

2025-05-18 Thread Luc Grosheintz
Implement the parts of layout_left that depend on layout_right; and the parts of layout_right that don't depend on layout_stride. libstdc++-v3/ChangeLog: * include/std/mdspan (layout_right): New class. Signed-off-by: Luc Grosheintz --- libstdc++-v3/include/std/mdspan | 153

Re: [PATCH 1/3] genemit: Remove support for string operands

2025-05-18 Thread Richard Sandiford
Jeff Law writes: > On 5/16/25 11:32 AM, Richard Sandiford wrote: >> gen_exp currently supports the 's' (string) operand type. It would >> certainly be possible to make the upcoming bytecode patch support >> that too. However, the rtx codes that have string operands should >> be very rarely used

Re: [PATCH 1/9] nds32: Avoid accessing beyond the operands[] array

2025-05-18 Thread Richard Sandiford
Jeff Law writes: > On 5/16/25 11:32 AM, Jeff Law wrote: >> >> >> On 5/16/25 11:21 AM, Richard Sandiford wrote: >>> This pattern used operands[2] to hold the shift amount, even though >>> the pattern doesn't have an operand 2 (not even as a match_dup). >>> This caused a build failure with -Werror

[PATCH v1 6/6] libstdc++: Add tests for layout_stride.

2025-05-18 Thread Luc Grosheintz
Implements the tests for layout_stride and for the features of the other two layouts that depend on layout_stride. libstdc++-v3/ChangeLog: * testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add tests for layout_stride. * testsuite/23_containers/mdspan/layouts/c

[PATCH v1 1/6] libstdc++: Implement layout_left from mdspan.

2025-05-18 Thread Luc Grosheintz
Implements the parts of layout_left that don't depend on any of the other layouts. libstdc++-v3/ChangeLog: * include/std/mdspan (layout_left): New class. Signed-off-by: Luc Grosheintz --- libstdc++-v3/include/std/mdspan | 240 1 file changed, 240 insert

Re: [PATCH 3/3] genemit: Use a byte encoding to generate insns

2025-05-18 Thread Richard Sandiford
Richard Biener writes: >> Am 16.05.2025 um 19:37 schrieb Richard Sandiford : >> >> genemit has traditionally used open-coded gen_rtx_FOO sequences >> to build up the instruction pattern. This is now the source of >> quite a bit of bloat in the binary, and also a source of slow >> compile times.

[PATCH] Fortran: fix FAIL of gfortran.dg/specifics_1.f90 after r16-372 [PR120099]

2025-05-18 Thread Harald Anlauf
Dear all, the attached proposed patch fixes PR120099 by modifying gfc_return_by_reference so that it returns true with -ff2c also for intrinsics returning complex numbers, as these are not pure in the GCC IR sense, and wrapper functions for the intrinsics were optimized out by DCE. The change on

[PATCH] gimple-fold: Implement simple copy propagation for aggregates [PR14295]

2025-05-18 Thread Andrew Pinski
This implements a simple copy propagation for aggregates in the similar fashion as we already do for copy prop of zeroing. Right now this only looks at the previous vdef statement but this allows us to catch a lot of cases that show up in C++ code. Also deletes aggregate copies that are to the sa

[PATCH v1 5/6] libstdc++: Implement layout_stride from mdspan.

2025-05-18 Thread Luc Grosheintz
Implements the remaining parts of layout_left and layout_right; and all of layout_stride. libstdc++-v3/ChangeLog: * include/std/mdspan(layout_stride): New class. Signed-off-by: Luc Grosheintz --- libstdc++-v3/include/std/mdspan | 219 +++- 1 file changed, 21

Re: [PATCH 6/9] genemit: Consistently use operand arrays in gen_* functions

2025-05-18 Thread Richard Sandiford
Jeff Law writes: > On 5/16/25 11:21 AM, Richard Sandiford wrote: >> One slightly awkward part about emitting the generator function >> bodies is that: >> >> * define_insn and define_expand routines have a separate argument for >>each operand, named "operand0" upwards. >> >> * define_split an

Re: [patch, fortran] PR120049 - ICE when using IS_C_ASSOCIATED ()

2025-05-18 Thread Harald Anlauf
Hi Jerry, I found 2 corner invalid cases which are silently accepted with your patch when iso_c_binding is used indirectly: print *, c_associated(c_loc(val), C_NULL_FUNPTR) print *, c_associated(C_NULL_FUNPTR, c_loc(val)) These should get rejected, too. Can you see how to catch these, too?

Re: AArch64: Enable early scheduling for -O3 and higher (PR118351)

2025-05-18 Thread Andrew Pinski
On Sun, May 18, 2025 at 2:09 PM Gerald Pfeifer wrote: > > On Mon, 3 Mar 2025, Wilco Dijkstra wrote: > > Enable the early scheduler on AArch64 for O3/Ofast. This means GCC15 > > benefits from much faster build times with -O2, but avoids the > > regressions in lbm which is very sensitive to minor s

Re: [patch, fortran] PR120049 - ICE when using IS_C_ASSOCIATED ()

2025-05-18 Thread Jerry D
On 5/18/25 2:10 PM, Harald Anlauf wrote: Hi Jerry, I found 2 corner invalid cases which are silently accepted with your patch when iso_c_binding is used indirectly:   print *, c_associated(c_loc(val), C_NULL_FUNPTR)   print *, c_associated(C_NULL_FUNPTR, c_loc(val)) These should get rejected

Re: [patch, fortran] PR120049 - ICE when using IS_C_ASSOCIATED ()

2025-05-18 Thread Jerry D
On 5/18/25 2:34 PM, Jerry D wrote: On 5/18/25 2:10 PM, Harald Anlauf wrote: Hi Jerry, I found 2 corner invalid cases which are silently accepted with your patch when iso_c_binding is used indirectly:    print *, c_associated(c_loc(val), C_NULL_FUNPTR)    print *, c_associated(C_NULL_FUNPTR, c_