[PATCH] libfortran: Fix up _gfortran_s{max,min}loc1_{4,8,16}_s{1,4} [PR120191]

Hi! There is a bug in _gfortran_s{max,min}loc1_{4,8,16}_s{1,4} which the following testcase shows. The functions return but then crash in the caller. Seems that is because buffer overflows, I believe those functions for if (mask == NULL || *mask) condition being false are supposed to fill in the r

Re: [PATCH v1 0/7] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost

This patch would like to introduce the combine of vec_dup + vsub.vv into vsub.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 15 in test. There will be two cases for the combine: The changes to add are very

libstdc++: Rewrite atomic builtin checks: Fix up 'GLIBCXX_ENABLE_BACKTRACE' check with 'size_t' [PR119667] (was: [PATCH] libstdc++: Rewrite atomic builtin checks [PR70560])

Hi! On 2025-04-29T21:09:17+0100, Jonathan Wakely wrote: > The GLIBCXX_ENABLE_BACKTRACE macro currently uses the > glibcxx_ac_atomic_int macro defined by the checks that this commit > removes from GLIBCXX_ENABLE_ATOMIC_BUILTINS. That wasn't a good check > anyway, because libbacktrace actually depe

[PATCH v4] RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.

This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1]. To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and supm extensions correctly at compile time. [1]https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc Changes for v4: - Fix the code bas

Re: libstdc++: Rewrite atomic builtin checks: Fix up 'GLIBCXX_ENABLE_BACKTRACE' check with 'size_t' [PR119667] (was: [PATCH] libstdc++: Rewrite atomic builtin checks [PR70560])

On Mon, 12 May 2025 at 09:52, Thomas Schwinge wrote: > > Hi! > > On 2025-04-29T21:09:17+0100, Jonathan Wakely wrote: > > The GLIBCXX_ENABLE_BACKTRACE macro currently uses the > > glibcxx_ac_atomic_int macro defined by the checks that this commit > > removes from GLIBCXX_ENABLE_ATOMIC_BUILTINS. Th

Re: [PATCH v1] libstdc++: More efficient weekday from year_month_day.

On Sun, 11 May 2025 at 12:34, Cassio Neri wrote: > > Hi all, > > After reflecting on my previous message and Andrew's, I now believe this > patch is not the best solution to optimise the day of the week. Instead, the > optimisation for n % 7 should be done by the compiler depending on the > pla

[PATCH v5] RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.

This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1]. To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and supm extensions correctly at compile time. [1]https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc Changes for v5: - Fix the testsuit

[PATCH] libfortran: Fix up _gfortran_s{max,min}loc2_{4,8,16}_s{1,4} [PR120191]

Hi! I've tried to write a testcase for the BT_CHARACTER maxloc/minloc with named or unnamed arguments and indeed the just posted patch fixed the arguments in there in multiple cases to match what the library expects. But the testcase still fails, due to library problems. One dealt with in this pa

[PATCH] testsuite/120222 - adjust gcc.dg/tree-ssa/gen-vect-28.c for inlining change

We now inline main_1, confusing the expected number of vectorizations. Pushed. PR testsuite/120222 * gcc.dg/tree-ssa/gen-vect-28.c: Use noipa on main_1. --- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/tests

Re: Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

Hi Mike, Irrespective of whether -Ofast is used or not, should’nt we generate XSCMPUDP instruction for ‘isgreater()’ operation? This is because XSCMPGTDP insn will generate a trap if either operand is an SNaN or a QNaN. Whereas, XSCMPUDP insn will generate a trap only if either operand is an SNa

[PATCH] Partially lift restriction from loc_list_from_tree_1

Hi, the function accepts all handled_component_p expressions and decodes them by means of get_inner_reference as expected, but bails out on bitfields: /* TODO: We can extract value of the small expression via shifting even for nonzero bitpos. */ if (list_ret == 0)

[PATCH] ext-dce: Only transform extend to subreg if TRULY_NOOP_TRUNCATION [PR 120050]

The tranform would be unsafe if !TRULY_NOOP_TRUNCATION because on these machines the hardware may look at bits outside of the given mode. gcc/ChangeLog: PR rtl-optimization/120050 * ext-dce.cc (ext_dce_try_optimize_insn): Only transform the insn if TRULY_NOOP_TRUNCATION. -

Re: [PATCH v2] loop2_unroll: split loop exit during unrolling of uncountable loops

On 4/23/2025 6:01 PM, Artemiy Volkov wrote: > Hi all, > > sending a v2 of > https://gcc.gnu.org/pipermail/gcc-patches/2025-April/680893.html after > fixing several issues with the original patch. Namely, the changes > since v1 are: > > - Remove the call to df_finish_pass () at the end of split_e

[Patch] Fortran: Use mpfr_sinu etc. with mpfr 4.2.0+ for degree trigonometric functions [PR120225]

C23 added the sinpi, cospi, etc. functions. Therefore, MPFR in 4.2.0 added the mpfr_ counter parts. I assume that those internally use the mpfr_sinu, mpfr_cosu, ... functions, which are also user accessible. In any case, MPFR makes the ...u functions available and explicitly documents that for u

[committed v2 14/14] arm: doc: cleanup documentation references to iWMMXT extensions

Now that the iwmmxt extensions have been removed, clean up the references to it in the documentation. We keep the -mcpu/-mtune/-march references as these are still accepted by the driver. gcc/ChangeLog: * doc/extend.texi: Remove the iwmmxt intrinsics. * doc/md.texi: Remove the iw

[committed v2 13/14] arm: remove iwmmxt registers from allocator tables

These registers can no-longer be allocated, so remove them from the various tables. gcc/ChangeLog: * config/arm/aout.h (REGISTER_NAMES): Remove iwmmxt registers. * config/arm/arm.h (FIRST_IWMMXT_REGNUM): Delete. (LAST_IWMMXT_REGNUM): Delete. (FIRST_IWMMXT_GR_REGNUM

Re: [PATCH v3] Consider frequency in cost estimation when converting scalar to vector.

> > gcc/ChangeLog: > > > > * config/i386/i386-features.cc > > (scalar_chain::mark_dual_mode_def): Weight > > n_integer_to_sse/n_sse_to_integer with bb frequency. > > (general_scalar_chain::compute_convert_gain): Ditto, and > > adjust function prototype to ret

Re: [PATCH] libstdc++: Restore std::scoped_lock for non-gthreads targets [PR120198]

On Mon, May 12, 2025 at 12:04 PM Jonathan Wakely wrote: > This was a regression introduced with using version.def to define > feature test macros. Could you add link to commit here, I think this is r14-3248-g083b7f2833d71d. > std::scoped_lock can be defined unconditionally > (including for free

Re: [PATCH] libstdc++: Remove #warning from for C++17 [PR120187]

On Mon, May 12, 2025 at 12:06 PM Jonathan Wakely wrote: > Although was removed from C++20, it was not formally > deprecated in C++17. In contrast, , , etc. were > formally deprecated in C++17 before being removed in C++20. > > Due to the widespread convention of including to detect > implementa

Re: [PATCH] gimple-fold: Don't replace `tmp = FP0 CMP FP1; if (tmp != 0)` over and over again when comparison can throw

On Mon, May 12, 2025 at 3:51 AM Richard Biener wrote: > > On Sat, May 10, 2025 at 3:19 AM Andrew Pinski > wrote: > > > > with -ftrapping-math -fnon-call-exceptions and: > > ``` > > tmp = FP0 CMP FP1; > > > > if (tmp != 0) ... > > ``` > > a call fold_stmt on the GIMPLE_COND will replace the above

[PING][PATCH][GCC15] Alpha: Fix base block alignment calculation regression

On Tue, 25 Feb 2025, Maciej W. Rozycki wrote: > Address this issue by recursing into COMPONENT_REF tree nodes until the > outermost one has been reached, which is supposed to be a MEM_REF one, > accumulating the offset as we go, fixing a commit e0dae4da4c45 ("Alpha: > Also use tree information

[pushed] c+: -Wabi false positive [PR120012]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- The warning compares the position of a field depending on whether or not the previous base/field is considered a POD for layout, but failed to consider whether the previous base/field is empty; layout of an empty base doesn't consider PODnes

Re: libgomp: Add a few more OpenMP/USM test cases

Thomas Schwinge wrote: On 2025-05-12T17:03:29+0200, I wrote: "Add effective-target 'offload_device_usm', 'libgomp.c-c++-common/target-usm-1.c'" On top, we could then add the attached "libgomp: Add a few more OpenMP/USM test cases"? These all PASS for GCN gfx90a with 'HSA_XNACK=1'. For the c

New Spanish PO file for 'cpplib' (version 15.1-b20250316)

Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'cpplib' has been submitted by the Spanish team of translators. The file is available at: https://translationproject.org/latest/cpplib/es.po (This file, 'cpplib-15.1-b202503

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[PATCH v2 1/3] aarch64: Recognize vector permute patterns which can be interpreted as AND [PR100165]

Certain permute that blends a vector with zero can be interpreted as an AND of a mask. This idea was suggested by Richard Sandiford when he was reviewing my patch which tries to optimizes certain vector permute with the FMOV instruction for the aarch64 target. For example, for the aarch64 target,

[PATCH v2 2/3] aarch64: Optimize AND with certain vector of immediates as FMOV [PR100165]

We can optimize AND with certain vector of immediates as FMOV if the result of the AND is as if the upper lane of the input vector is set to zero and the lower lane remains unchanged. For example, at present: v4hi f_v4hi (v4hi x) { return x & (v4hi){ 0x, 0x, 0, 0 }; } generates: f_v4h

[PATCH v2 3/3] aarch64: Add more vector permute tests for the FMOV optimization [PR100165]

This patch adds more tests for vector permutes which can now be optimized as FMOV with the generic PERM change and the aarch64 AND patch. Changes since v1: * v2: Add -mlittle-endian to the little endian tests explicitly and rename the tests accordingly. PR target/100165 gcc/testsuite/Cha

Re: [PATCH RFC] libstdc++: run testsuite with -Wabi

On Mon, 12 May 2025 at 16:13, Jason Merrill wrote: > > On 5/9/25 1:31 PM, Jonathan Wakely wrote: > > On Fri, 9 May 2025 at 18:13, Jonathan Wakely wrote: > >> > >> On Fri, 9 May 2025 at 11:19, Jonathan Wakely wrote: > >>> > >>> On Thu, 8 May 2025 at 20:56, Jason Merrill wrote: > > Test

[PATCH] c++: Add std::to_underlying to the set of stdlib functions that are always folded

This function is yet another stdlib function that is just a simple cast, so having it appear while debugging is arguably not useful. So add it to the existing handling that always-folds some stdlib functions. Add std::to_underlying to the set of stdlib functions that are always folded gcc/cp/Chan

RE: [PATCH 2/3] aarch64: Optimize AND with certain vector of immediates as FMOV [PR100165]

> Pengxuan Zheng writes: > > We can optimize AND with certain vector of immediates as FMOV if the > > result of the AND is as if the upper lane of the input vector is set > > to zero and the lower lane remains unchanged. > > > > For example, at present: > > > > v4hi > > f_v4hi (v4hi x) > > { > >

RE: [PATCH 1/3] Recognize vector permute patterns which can be interpreted as AND [PR100165]

> Richard Biener writes: > > On Sat, Apr 26, 2025 at 2:42 AM Pengxuan Zheng > wrote: > >> > >> Certain permute that blends a vector with zero can be interpreted as > >> an AND of a mask. This idea was suggested by Richard Sandiford when > >> he was reviewing my patch which tries to optimizes cert

Re: [PATCH 0/6] RISC-V: frm state-machine improvements

On 5/11/25 19:22, 钟居哲 wrote: > Hi, vineet. > > >> I have a feeling this has to do with following: > >> https://godbolt.org/z/Px9es7j1r > > I saw in there are 2 fsrm instruction inside the main loop in Clang generated > ASM which I think GCC is better. > > Correct me if I am wrong. Thanks. Yes you

[PATCH 3/3] libstdc++: Renamed bits/move_only_function.h to bits/funcwrap.h [PR119125]

The file now includes copyable_function in addition to move_only_function. PR libstdc++/119125 libstdc++-v3/ChangeLog: * include/bits/move_only_function.h: Move to... * include/bits/funcwrap.h: ...here. * doc/doxygen/stdheader.cc (init_map): Replaced move_only_func

Re: [PATCH] libstdc++: Restore std::scoped_lock for non-gthreads targets [PR120198]

On Mon, 12 May 2025 at 11:19, Tomasz Kaminski wrote: > > > > On Mon, May 12, 2025 at 12:04 PM Jonathan Wakely wrote: >> >> This was a regression introduced with using version.def to define >> feature test macros. > > Could you add link to commit here, I think this is r14-3248-g083b7f2833d71d. Do

[PATCH 2/3] libstdc++: Implement C++26 copyable_function [PR119125]

This patch implements C++26 copyable_function as specified in P2548R6. It also implements LWG 4255 that adjust move_only_function so constructing from empty copyable_function, produces empty functor. This falls from existing checks, after specializing __is_polymorphic_function_v for copyable_functi

[PATCH 0/3] libstdc++: Implement P2548R6 (copyable function)

This patch series implements the copyable_function as specified in P2548R6. It also modifies implementation of move_only_funtion to avoid doulbe indirection when constructing from other function wrappers, based on provision in C++26 [func.wrap.general] p2. Finally we rename bits/move_only_function.

[PATCH v2] libstdc++: Cleanup and stabilize format _Spec<_CharT> and _Pres_type.

These patch makes following changes to _Pres_type values: * _Pres_esc is replaced with separate _M_debug flag. * _Pres_s, _Pres_p do not overlap with _Pres_none. * hexadecimal presentation use same values for pointer, integer and floating point types. The members of _Spec<_CharT> are rearang

Re: [PATCH v20 2/4] c: Add _Countof operator

On Sun, 11 May 2025, Alejandro Colomar wrote: > +/* { dg-options "-Wno-declaration-after-statement -Wno-pedantic -Wno-vla" } > */ > +/* { dg-options "-Wno-pedantic -Wvla-parameter" } */ > +/* { dg-options "-Wno-declaration-after-statement -Wno-pedantic -Wno-vla" } > */ Most of these options a

Re: [PATCH] gimple-fold: extend vector simplification to match scalar bitwise optimizations [PR119196]

On Mon, 12 May 2025, Icen Zeyada wrote: > Generalize existing scalar gimple_fold rules to apply the same > bitwise comparison simplifications to vector types. Previously, an > expression like > > (x < y) && (x > y) > > would fold to `false` if x and y are scalars, but eq

Re: [PATCH] libstdc++: Fix constraint recursion in std::expected's operator== [PR119714]

On Mon, May 12, 2025 at 3:01 PM Patrick Palka wrote: > On Tue, 6 May 2025, Tomasz Kaminski wrote: > > > > > > > On Mon, May 5, 2025 at 8:50 PM Patrick Palka wrote: > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk/15? > > > > This LGTM. > > Out of curiosity, would declaring th

Re: [PATCH 1/3] libstdc++: Avoid double indirection in move_only_function when possible [PR119125]

On Mon, May 12, 2025 at 12:57 PM Tomasz Kamiński wrote: > Based on the provision in C++26 [func.wrap.general] p2 this patch adjust > the generic > move_only_function(_Fn&&) constructor, such that when _Fn refers to > selected > move_only_function instantiations, the ownership of the target object

[PUSHED] nvptx: Support '-mptx=5.0'

gcc/ * config/nvptx/nvptx-opts.h (enum ptx_version): Add 'PTX_VERSION_5_0'. * config/nvptx/nvptx.cc (ptx_version_to_string) (ptx_version_to_number): Adjust. * config/nvptx/nvptx.h (TARGET_PTX_5_0): New. * config/nvptx/nvptx.opt (Enum(ptx_versi

[PATCH v2 2/3] libstdc++: Implement C++26 copyable_function [PR119125]

This patch implements C++26 copyable_function as specified in P2548R6. It also implements LWG 4255 that adjust move_only_function so constructing from empty copyable_function, produces empty functor. This falls from existing checks, after specializing __is_polymorphic_function_v for copyable_functi

[PATCH v2 1/3] libstdc++: Avoid double indirection in move_only_function when possible [PR119125]

Based on the provision in C++26 [func.wrap.general] p2 this patch adjust the generic move_only_function(_Fn&&) constructor, such that when _Fn refers to selected move_only_function instantiations, the ownership of the target object is direclty transfered to constructor object. This avoid cost of

Re: [PATCH v1 0/7] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost

I think we need the run tests for each op combine up to a point. But for asm check, Seems we can put it together? I mean something like below: +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(int3

[PUSHED] GCN, nvptx libstdc++: Force use of '__atomic' builtins: revert 'atomicity_dir=cpu/generic/atomicity_builtins' hard-coding [PR119645]"

Thanks to commit 86627faec10da53d7532805019e5296fcf15ac09 "libstdc++: Rewrite atomic builtin checks [PR70560]", for both GCN, nvptx we now get: +configure:16060: checking for atomic builtins for _Atomic_word +[...] +configure:16073: result: yes ..., and thus may revert the 'atomicity_

[PUSHED] nvptx: Support '-march=sm_61'

gcc/ * config/nvptx/nvptx-sm.def: Add '61'. * config/nvptx/nvptx-gen.h: Regenerate. * config/nvptx/nvptx-gen.opt: Likewise. * config/nvptx/nvptx.cc (first_ptx_version_supporting_sm): Adjust. * config/nvptx/nvptx.opt (-march-map=sm_61, -march-map=sm_62

[PUSHED] GCN, nvptx offloading: Restrain 'WARNING: program timed out.' while in 'dynamic_cast'" [PR119692]

PR target/119692 libgomp/ * testsuite/libgomp.c++/pr119692-1-4.C: '{ dg-timeout 10 }'. * testsuite/libgomp.c++/pr119692-1-5.C: Likewise. * testsuite/libgomp.c++/target-exceptions-bad_cast-1.C: Likewise. * testsuite/libgomp.c++/target-exceptions-bad_ca

[PATCH v2 3/3] libstdc++: Renamed bits/move_only_function.h to bits/funcwrap.h [PR119125]

The file now includes copyable_function in addition to move_only_function. PR libstdc++/119125 libstdc++-v3/ChangeLog: * include/bits/move_only_function.h: Move to... * include/bits/funcwrap.h: ...here. * doc/doxygen/stdheader.cc (init_map): Replaced move_only_func

[PATCH v2 7/8] RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data

This commit drops the riscv_ext_version_table and instead uses the riscv_ext_info_t data structure to provide the version information for RISC-V extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Remove. (standard_extensions_p): Use

[PATCH v2 1/8] RISC-V: Introduce riscv-ext*.def to define extensions

Adding a new ISA extension to RISC-V GCC requires modifying several places: 1. riscv_ext_version_table for the extension version. 2. riscv.opt for the target option and variable. 3. riscv_ext_flag_table to bind the extension to its target option. 4. riscv_combine_info if this extension is just a ma

[PATCH v2 2/8] RISC-V: Use riscv-ext.def to generate target options and variables

Leverage the centralized riscv-ext.def definitions to auto-generate the target option parsing and associated internal flags, replacing manual listings in riscv.opt; `riscv_ext_flag_table` part will remove in later patch. gcc/ChangeLog: * config/riscv/gen-riscv-ext-opt.cc: New. * c

[PATCH v2 3/8] RISC-V: Generate extension table in documentation from riscv-ext.def

Automatically build the ISA extension reference table in invoke.texi from the unified riscv-ext.def metadata, ensuring documentation stays in sync with extension definitions and reducing manual maintenance. gcc/ChangeLog: * doc/invoke.texi: Replace hand‑written extension table with

[PATCH v2 4/8] RISC-V: Adjust riscv_can_inline_p

We don't hold any extenison flags in `target_flags`, so no need to gather the extenison flags in `target_flags`. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_can_inline_p): Drop extension flags check from `target_flags`. * config/riscv/riscv-subset.h (riscv_

[PATCH] libiberty: Fix off-by-one when collecting range expression

Fixes this error during build of fixincludes: In function ‘byte_regex_compile’, inlined from ‘xregcomp’ at ../libiberty/../../libiberty/regex.c:7973:11: ../libiberty/../../libiberty/regex.c:3477:29: warning: writing 1 byte into a region of size 0 [-Wstringop-overflow=] 3477 |

[PATCH v2 6/8] RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data

Consolidate implied-extension logic by removing the old `riscv_implied_info` array and using the `implied_exts` field in the unified riscv_ext_info_t structures generated from `riscv-ext.def`. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info::riscv_implied_

[PATCH v2 5/8] RISC-V: Introduce riscv_ext_info_t to hold extension metadata

Define a new riscv_ext_info_t struct to aggregate all ISA extension fields (name, version, flags, implied extensions, bitmask and extra flags) generated from riscv-ext.def. Also adjust riscv_ext_flag_table_t and riscv_implied_info_t to make it able to not hold extension name, this part will refact

[PATCH v2 8/8] RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data

Refactor extension flag handling by removing the old riscv_ext_flag_table and sourcing all flag definitions directly from the flags field of the unified riscv_ext_info_t structures generated from riscv-ext.def. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_extra_ext_flag_tab

Re: [PATCH 8/9] AArch64: rules for CMPBR instructions

On 09/05/2025 13:49, Kyrylo Tkachov wrote: > >> On 8 May 2025, at 21:10, Karl Meakin wrote: >> >> Add rules for lowering `cbranch4` to CBB/CBH/CB when >> CMPBR extension is enabled. >> >> gcc/ChangeLog: >> >> * config/aarch64/aarch64.md (cbranch4): Mmit CMPBR >> instructions if possible. >> (

Re: [PATCH v20 3/4] c: Add

On Mon, May 12, 2025 at 10:54:52AM +, Joseph Myers wrote: > On Sun, 11 May 2025, Alejandro Colomar wrote: > > > gcc/ChangeLog: > > > > * Makefile.in (USER_H): Add . > > * ginclude/stdcountof.h: Add countof macro. > > This is missing tests for the header. Hi Joseph, Yep, I hadn't fo

Re: [PATCH] [testsuite] [analyzer] [vxworks] define __STDC_WANT_LIB_EXT1__ to 1

On Thu, 2025-05-08 at 23:31 -0300, Alexandre Oliva wrote: > > vxworks' headers use #if instead of #ifdef to test for > __STDC_WANT_LIB_EXT1__, so the definition in the analyzer test > strotok-cppreference.c catches a bug there, but not something it's > meant to catch or that we could fix in GCC, s

Re: [PATCH] [testsuite] [vxworks] netinet includes atomic, reqs c++11

On Thu, 2025-05-08 at 23:29 -0300, Alexandre Oliva wrote: > > On vxworks, the included netinet/in.h header indirectly includes > , that fails on C++ <11.  Skip the test. > > Tested with gcc-14 targeting ppc-vx7r2 and ppc64-vx7r2.  Also tested > with trunk on ppc64le-linux-gnu, and with gcc-14 tar

Re: [AUTOFDO][AARCH64] Add support for profilebootstrap

Kugan Vivekanandarajah writes: > diff --git a/configure.ac b/configure.ac > index 730db3c1402..701284e38f2 100644 > --- a/configure.ac > +++ b/configure.ac > @@ -621,6 +621,14 @@ case "${target}" in > ;; > esac > > +autofdo_target="i386" > +case "${target}" in > + aarch64-*-*) > +auto

Add effective-target 'offload_device_usm', 'libgomp.c-c++-common/target-usm-1.c' (was: [committed] libgomp.fortran/map-alloc-comp-9{,-usm}.f90: Add unified_shared_memory variant)

Hi! On 2025-05-07T13:58:38+0200, Tobias Burnus wrote: > Committed asr16-445-g9565076f9b8105. This test supports mapping + accessing > the vtab > of the polymorphic variable on the host. Obviously, this only works if > the host pointer is device accessible ("unified-shared memory"). In > princ

libgomp: Add a few more OpenMP/USM test cases (was: Add effective-target 'offload_device_usm', 'libgomp.c-c++-common/target-usm-1.c')

Hi! On 2025-05-12T17:03:29+0200, I wrote: > "Add effective-target 'offload_device_usm', > 'libgomp.c-c++-common/target-usm-1.c'" On top, we could then add the attached "libgomp: Add a few more OpenMP/USM test cases"? These all PASS for GCN gfx90a with 'HSA_XNACK=1'. Grüße Thomas >From 8c04

PING (and v2) – [Patch] nvptx/nvptx.opt: Update -march-map= for newer sm_xxx

PING. There is actually a minor update as meanwhile CUDA 12.8 was released that added the 'f' suffix and sm_103 and sm_121. Still, the pattern remains the same; hence, a normal PING. On April 25, 2025, Tobias Burnus wrote: The idea of -march-map= is to simply and future proof select the best -

Re: [PATCH v20 2/4] c: Add _Countof operator

On Mon, May 12, 2025 at 10:54:34AM +, Joseph Myers wrote: > On Sun, 11 May 2025, Alejandro Colomar wrote: > > > +/* { dg-options "-Wno-declaration-after-statement -Wno-pedantic -Wno-vla" > > } */ > > > +/* { dg-options "-Wno-pedantic -Wvla-parameter" } */ > > > +/* { dg-options "-Wno-declar

Re: [PATCH RFC] libstdc++: run testsuite with -Wabi

On 5/9/25 1:31 PM, Jonathan Wakely wrote: On Fri, 9 May 2025 at 18:13, Jonathan Wakely wrote: On Fri, 9 May 2025 at 11:19, Jonathan Wakely wrote: On Thu, 8 May 2025 at 20:56, Jason Merrill wrote: Tested x86_64-pc-linux-gnu. Does this make sense for trunk? Yes, it looks useful. I'm goi

Re: [PATCH] vxworks: libgcc: include string.h for memset

On Fri, 9 May 2025 at 04:26, Alexandre Oliva wrote: > > gthr-vxworks-thread.c calls memset in __ghtread_cond_signal, but it > fails ot include , where this function is declared, and GCC > 14 rejects calls of undeclared functions. Include the required > header. > > Ok to install? > Sure, thanks

[COMMITTED] PR tree-optimization/120231 - Add dispatch for casts between integer and float.

PR 120231 highlights that we’ve never implemented range operators for casting between integers and floating-point types — in either direction. This patch fills in the missing dispatch infrastructure so that casts between int and float types can eventually be handled cleanly via range_operator.

[RFC] Enable automatic ChangeLog updates on devel/omp/gcc-15 branch

I have created the devel/omp/gcc-15 (aka "OG15") branch, but not yet populated it with patches carried over from devel/omp/gcc-14. These development branches are where we put bleeding-edge versions of OpenMP and OpenACC features. For previous branches we'd been using ChangeLog.omp files paral

Re: [PATCH v2 1/3] aarch64: Recognize vector permute patterns which can be interpreted as AND [PR100165]

Pengxuan Zheng writes: > +/* Recognize patterns suitable for the AND instructions. */ > +static bool > +aarch64_evpc_and (struct expand_vec_perm_d *d) > +{ > + /* Either d->op0 or d->op1 should be a vector of all zeros. */ > + if (d->one_vector_p || (!d->zero_op0_p && !d->zero_op1_p)) > +r

Re: [PATCH v1] contrib/: Add support for Link: tags

Hi Jonathan, On Mon, May 12, 2025 at 05:42:55PM +0100, Jonathan Wakely wrote: > On Mon, 12 May 2025 at 17:34, Jonathan Wakely wrote: > > > > On Mon, 12 May 2025 at 16:46, Alejandro Colomar wrote: > > > > > > contrib/ChangeLog: > > > > > > * gcc-changelog/git_commit.py (GitCommit): > > >

Re: [PATCH v21 2/3] c: Add

Hi Joseph, On Mon, May 12, 2025 at 04:43:45PM +, Joseph Myers wrote: > On Mon, 12 May 2025, Alejandro Colomar wrote: > > > + if (strcmp (xstr(countof), "_Alignas") != 0) > > countof should definitely not expand to _Alignas! D'oh! :-) > I don't recommend > posting untested patches. I s

Re: [PATCH 3/6] RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn

On 5/12/25 14:55, Jeff Law wrote: test_float_point_frm_static: 1: frrma5 <-- 2: fsrmi 2 3: fsrma5 <-- 4: callnormalize_vl 5: frrma5 <-- 6: fsrmi 3 7: fs

Re: [PATCH v21 1/3] c: Add _Countof operator

Hi Jonathan, On Mon, May 12, 2025 at 06:11:18PM +0100, Jonathan Wakely wrote: > On 12/05/25 17:53 +0200, Alejandro Colomar wrote: > > Suggested-by: Xavier Del Campo Romero > > Co-authored-by: Martin Uecker > > Acked-by: "James K. Lowden" > > What does this Acked-by: indicate?

Re: [PATCH] optabs: Remove cmov optab [PR120230]

On Mon, May 12, 2025 at 2:36 PM Richard Sandiford wrote: > > Andrew Pinski writes: > > cmov optab was added back in r0-24110-g1c0290eaac4094 > > (https://gcc.gnu.org/pipermail/gcc-patches/1999-September/018596.html) > > but it was never used. movcc is used instead and since > > r0-93453-gf90b7a5

Re: Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

On Mon, May 12, 2025 at 01:24:04PM +0530, Surya Kumari Jangala wrote: > Hi Mike, > Irrespective of whether -Ofast is used or not, should’nt we generate XSCMPUDP > instruction for ‘isgreater()’ operation? This is because XSCMPGTDP insn will > generate a trap if either operand is an SNaN or a QNaN.

[PATCH 3/3] cfgcleanup: small performance improvement in some cases

With some functions, there might be the case where every stack variable is a live at the end of a basic block. If that is the case then it is known that all stack variables will conflict with each other so there is no reason to go through figuring out what variables conflict with each other. Sin

[PATCH 1/3] cfgexpand: Reverse the order of going through the update_cache_list queue.

This is a small optimization, the reversed order of the walk of update_cache_list queue. The queue is pushed in Pre-order/NLR, reversing the order will reduce how many times we need to go through the loop as we update the nodes which might have a link back to another one first. Bootstrapped and

[PATCH 2/3] cfgexpand: Update cache during the original DFS walk

This is a small optimization which can improve how many times are need through the update loop. It can reduce the number of times in the update loop by maybe 1 times. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * cfgexpand.cc (vars_ssa_cache::operator()): Update the cach

Re: [PATCH] final: Fix get_attr_length for asm goto [PR118411]

On Sat, Jan 11, 2025 at 1:11 PM Jeff Law wrote: > > > > On 1/11/25 2:08 PM, Andrew Pinski (QUIC) wrote: > >> -Original Message- > >> From: Jeff Law > >> Sent: Saturday, January 11, 2025 8:12 AM > >> To: Andrew Pinski (QUIC) ; gcc- > >> patc...@gcc.gnu.org > >> Subject: Re: [PATCH] final:

Re: Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

On Mon, May 12, 2025 at 06:35:15PM -0400, Michael Meissner wrote: > On Mon, May 12, 2025 at 01:24:04PM +0530, Surya Kumari Jangala wrote: > > Hi Mike, > > Irrespective of whether -Ofast is used or not, should’nt we generate > > XSCMPUDP instruction for ‘isgreater()’ operation? This is because XSCM

[PATCH] c++: unifying specializations of non-primary tmpls [PR120161]

Bootstrapped and regtested on x86-64-pc-linux-gnu, does this look OK for trunk/15/14? -- >8 -- Here unification of P=Wrap::type, A=Wrap::type wrongly succeeds ever since r14-4112 which made the RECORD_TYPE case of unify no longer recurse into template arguments for non-primary templates (since th

[PATCH] aarch64: Remove cmov6 patterns

Since the cmov optab is not used and is being removed, the `cmov6` patterns from the aarch64 backend can also be removed. gcc/ChangeLog: * config/aarch64/aarch64.md (cmov6): Remove. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64.md | 32 1 f

Re: [PATCH] libstdc++: Make debug iterator pointer sequence const [PR116369]

On 31/03/25 22:20 +0200, François Dumont wrote: Hi Following this previous patch https://gcc.gnu.org/pipermail/libstdc++/2024-August/059418.html I've completed it for the _Safe_unordered_container_base type and implemented the rest of the change to store the safe iterator sequence as a point

[PATCH] c++: Allow -Wvirtual-move-assign to be more easily ignored

gcc/cp/ChangeLog: * method.cc (synthesized_method_walk): Check whether -Wvirtual-move-assign is enabled at the location of a base class's move assignment operator. gcc/testsuite/ChangeLog: * g++.dg/warn/ignore-virtual-move-assign.C: New test. Co-authored-

Re: [PATCH v2 3/3] aarch64: Add more vector permute tests for the FMOV optimization [PR100165]

Pengxuan Zheng writes: > diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c > b/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c > new file mode 100644 > index 000..adbf87243f6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c > @@ -0,0 +1,130 @@ > +/* { dg-do compil

Re: [PATCH] optabs: Remove cmov optab [PR120230]

Andrew Pinski writes: > cmov optab was added back in r0-24110-g1c0290eaac4094 > (https://gcc.gnu.org/pipermail/gcc-patches/1999-September/018596.html) > but it was never used. movcc is used instead and since > r0-93453-gf90b7a5a7913cc (cond-optab), > movcc becomes what cmov_optab was going to be;

Re: [PATCH v2 2/3] aarch64: Optimize AND with certain vector of immediates as FMOV [PR100165]

Pengxuan Zheng writes: > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > index 15f08cebeb1..98ce85dfdae 100644 > --- a/gcc/config/aarch64/aarch64.cc > +++ b/gcc/config/aarch64/aarch64.cc > @@ -23621,6 +23621,36 @@ aarch64_simd_valid_and_imm (rtx op) >return aarch64

Re: [PATCH] aarch64: Remove cmov6 patterns

Andrew Pinski writes: > Since the cmov optab is not used and is being removed, > the `cmov6` patterns from the aarch64 backend can > also be removed. > > gcc/ChangeLog: > * config/aarch64/aarch64.md (cmov6): Remove. OK, thanks. Richard > > Signed-off-by: Andrew Pinski > --- > gcc/config

[PATCH v2] gimple-fold: Don't replace `tmp = FP0 CMP FP1; if (tmp != 0)` over and over again when comparison can throw

with -ftrapping-math -fnon-call-exceptions and: ``` tmp = FP0 CMP FP1; if (tmp != 0) ... ``` a call fold_stmt on the GIMPLE_COND will replace the above with a new tmp each time and we even lose the eh informatin on the previous comparison too. Changes since v1: * v2: Use INTEGRAL_TYPE_P instead o

Re: [PATCH] optabs: Remove cmov optab [PR120230]

On Mon, May 12, 2025 at 8:54 AM Andrew Pinski wrote: > > cmov optab was added back in r0-24110-g1c0290eaac4094 > (https://gcc.gnu.org/pipermail/gcc-patches/1999-September/018596.html) > but it was never used. movcc is used instead and since > r0-93453-gf90b7a5a7913cc (cond-optab), > movcc becomes

Re: [PATCH] c++: Add std::to_underlying to the set of stdlib functions that are always folded

On Mon, 12 May 2025 at 21:35, Ville Voutilainen wrote: > > This function is yet another stdlib function that is just a simple > cast, so having > it appear while debugging is arguably not useful. So add it to the > existing handling > that always-folds some stdlib functions. > > Add std::to_underl

Re: [PATCH 3/6] RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn

On 5/10/25 9:55 PM, Vineet Gupta wrote: On 5/10/25 07:17, Jeff Law wrote: On 5/9/25 2:27 PM, Vineet Gupta wrote: This showed up when debugging the testcase for PR119164. RISC-V FRM mode-switching state machine has special handling for transitions to and from a call_insn as FRM needs to save

Re: [PATCH] c++: Add std::to_underlying to the set of stdlib functions that are always folded

On Mon, 12 May 2025 at 23:57, Jonathan Wakely wrote: > > On Mon, 12 May 2025 at 21:35, Ville Voutilainen > wrote: > > > > This function is yet another stdlib function that is just a simple > > cast, so having > > it appear while debugging is arguably not useful. So add it to the > > existing hand

[COMMITTED] Remove negative ranges using trailing zero masks.

When there are trailing 0's in the bitmask, I previously modified set_range_from_bitmask () to remove the lower positive ranges which do not match the value to help with some optimizations.   It helps with lower range comparisons and generally seemed to be a good thing. This reworks it clean i

Re: [PATCH 3/6] RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn

On 5/12/25 4:17 PM, Vineet Gupta wrote: On 5/12/25 14:55, Jeff Law wrote: test_float_point_frm_static: 1: frrma5 <-- 2: fsrmi 2 3: fsrma5 <-- 4: callnormalize_vl 5: frrma5 <-- 6: fsrmi 3

[pushed: r16-579] diagnostics: improvements to experimental-html output [PR116792]

Add barebones support for * diagnostic metadata rules * quoted source * generated patches * execution paths Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r16-579-ge4ccad8faf5266. gcc/ChangeLog: PR other/116792 * diagnostic-format-html.cc: Includ

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