Re: [PATCH,LRA] Restrict the reuse of spill slots [PR117868]

Am 11.01.25 um 19:15 schrieb Denis Chertykov: The fix for PR117868. [...] PR rtl-optimization/117868 gcc/ * lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Reuse slots only without allocated memory or only with equal or smaller registers with equal or smaller alignmen

Re: [PATCH] More memory leak fixes

On Fri, 10 Jan 2025, Richard Biener wrote: > The following were found compiling SPEC CPU 2017 with valgrind. > > Bootstrap and regtest pending on x86_64-unknown-linux-gnu. > > * tree-vect-slp.cc (vect_analyze_slp): Release saved_stmts > vector. > (vect_build_slp_tree_2): Releas

[PATCH v2] c++/modules: Don't emit imported deduction guides [PR117397]

On Sun, Jan 12, 2025 at 04:14:41AM +1100, Nathaniel Shead wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk? > > -- >8 -- > > The ICE in the linked PR is caused because name lookup finds duplicate > copies of the deduction guides, causing a checking assert to fail. > > Thi

[PATCH] testsuite: Fix test failing with -fimplicit-constexpr [PR118277]

While testing an unrelated C++ patch with "make check-c++-all", I noticed that r15-6760-g38a13ea4117b96 added a test case that fails with -fimplicit-constexpr. The problem is that this test unconditionally expects an error stating that a non-constexpr function is called, but that function is auto-

[patch, fortran, committed] Fix union member access

Hello world, I have committed the attached patch as obvious and simple after regression-testing. I could not construct a test case that actually failed, though, but the logic was wrong (pointer aliasing and the field that was accessed had the wrong offset). Commit is r15-6831-g40754a3b9bef83bf4

Re: [PATCH] c++/modules: Fix linkage checks for exported using-decls

On Fri, Jan 03, 2025 at 05:18:55PM +, xxx wrote: > From: yxj-github-437 <2457369...@qq.com> > > This patch attempts to fix an error when build module std. The reason for the > error is __builrin_va_list (aka struct __va_list) is an internal linkage. so > attempt to handle this builtin type by

[Regression] [pushed] c++: reduce redundant deprecated warnings

Hi Jason, This change caused the 99957.cc test to regress on arm-none-eabi. FAIL: 20_util/pair/cons/99957.cc -std=gnu++17 (test for warnings, line 25) FAIL: 20_util/pair/cons/99957.cc -std=gnu++17 (test for warnings, line 26) FAIL: 20_util/pair/cons/99957.cc -std=gnu++17 (test for warnings

[PATCH 1/2] RISC-V: Improve bitwise and ashift reassociation for single-bit immediate without zbs [PR 115921]

When zbs is not available, there's nothing special with single-bit immediates and we should perform reassociation as normal immediates. gcc/ChangeLog: PR target/115921 * config/riscv/riscv.md (_shift_reverse): Only check popcount_hwi if !TARGET_ZBS. --- gcc/config/riscv/r

[PATCH] gcc/d: give dependency files better filenames

Regstrapped on x86_64-pc-linux-gnu. I've also checked the generated dependency files are correct by hand and "instrumented" the build to fail if two dependency files are the same, by doing the following: DPOSTCOMPILE = ! test -f $(DEPFILE).Po && mv ... ... and confirmed no further conflicts of

Re: [PATCH] testsuite: arm: Require 16-bit float support

On 2024-11-19 15:01, Richard Earnshaw (lists) wrote: On 18/11/2024 12:00, Christophe Lyon wrote: Hi Torbjörn, On 11/18/24 10:37, Torbjorn SVENSSON wrote: On 2024-11-08 20:37, Torbjorn SVENSSON wrote: On 2024-11-08 12:24, Richard Earnshaw (lists) wrote: On 05/11/2024 20:06, Torbjörn S

Re: [PATCH,LRA] Restrict the reuse of spill slots [PR117868]

вс, 12 янв. 2025 г. в 15:38, Georg-Johann Lay : > > Am 11.01.25 um 19:15 schrieb Denis Chertykov: > > The fix for PR117868. > > [...] > > > > PR rtl-optimization/117868 > > gcc/ > > * lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Reuse slots > > only without allocated memor

Re: [PATCH,LRA] Restrict the reuse of spill slots [PR117868]

Am 12.01.25 um 13:54 schrieb Denis Chertykov: вс, 12 янв. 2025 г. в 15:38, Georg-Johann Lay : Am 11.01.25 um 19:15 schrieb Denis Chertykov: The fix for PR117868. [...] PR rtl-optimization/117868 gcc/ * lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Reuse slots only

[PATCH 0/2] RISC-V bitwise-ashift reassoc improvements [PR 115921]

Each change below is logically intact on its own, they are just in a series because of a false dependency. Please review separately. Xi Ruoyao (2): RISC-V: Improve bitwise and ashift reassociation for single-bit immediate without zbs [PR 115921] RISC-V: Remove zba check in bitwise and ash

[PATCH 2/2] RISC-V: Remove zba check in bitwise and ashift reassociation [PR 115921]

The test case long test (long x, long y) { return ((x | 0x1ff) << 3) + y; } is now compiled (-O2 -march=rv64g_zba) to li a4,4096 slliw a5,a0,3 addia4,a4,-8 or a5,a5,a4 addwa0,a5,a1 ret Despite this check was originally intended t

Re: [PATCH v2 2/7] Alpha: Optimize block moves coming from longword-aligned source

On Mon, 6 Jan 2025, Jeff Law wrote: > > gcc/ > > * config/alpha/alpha.cc (alpha_expand_block_move): Merge loaded > > data from pairs of SImode registers into single DImode registers > > if to be used with unaligned stores. > > > > gcc/testsuite/ > > * gcc.target/alpha/memc

Re: [PATCH 1/2] Alpha: Add memory clobbers to `builtin_longjmp' expansion

On Mon, 6 Jan 2025, Jeff Law wrote: > > gcc/ > > * config/alpha/alpha.md (builtin_longjmp): Add memory clobbers. > OK Applied now, thanks for your review. Maciej

Re: [PATCH 2/2] Alpha: Restore frame pointer last in `builtin_longjmp' [PR64242]

On Mon, 6 Jan 2025, Jeff Law wrote: > > gcc/ > > PR middle-end/64242 > > * gcc/config/alpha/alpha.md (`builtin_longjmp'): Restore frame > > pointer last. Add frame clobber and schedule blockage. > OK. Applied now (with an obvious correction to ChangeLog), thanks for your review

Re: [PATCH v2 1/7] Alpha: Always respect -mbwx, -mcix, -mfix, -mmax, and their inverse

On Mon, 6 Jan 2025, Jeff Law wrote: > > gcc/ > > * config/alpha/alpha.cc (alpha_option_override): Ignore CPU > > flags corresponding to features the enabling or disabling of > > which has been requested with an individual feature option. > > > > gcc/testsuite/ > > * gcc.ta

Re: [PATCH v2 3/7] Alpha: Fix a block move pessimisation with zero-extension after LDWU

On Mon, 6 Jan 2025, Jeff Law wrote: > > gcc/ > > * config/alpha/alpha.cc (alpha_expand_block_move): Use a HImode > > subreg of a DImode register to hold data from an aligned HImode > > load. > Generally OK. > > > > + data_regs[nregs++] = gen_rtx_SUBREG (HImode, tmp, 0); > W

[patch, fortran] Dump all symbol attributes with -fdump-fortran-original

Hell world, after finding that an attribute I was looking for was not in the -fdump-fortran-original dump, I started putting in attributes and didn't stop until I had them all (or so I hope :-) It should be easier to read than looking at the symbol attributes in a debugging session, and could ho

[PATCH] crc: Fix up some crc related wrong code issues [PR117997, PR118415]

Hi! As mentioned in the second PR, using table names like crc_table_for_crc_8_polynomial_0x12 in the user namespace is wrong, user could have defined such variables in their code and as can be seen on the last testcase, then it just misbehaves. At minimum such names should start with 2 underscores

[pushed: r15-6838] c: UX improvements to 'too {few, many} arguments' errors (v5) [PR118112]

Thanks Jason for notes on v4 of the patch. The C parts of the patch are relatively simple, approved by Joseph, and IMHO will be very helpful to users for GCC 15's C23-by-default migration. For the C++ parts, I don't feel 100% comfortable that I understand all the issues Jason is pointing out, an

[PATCH] [ifcombine] propagate signbit mask to XOR right-hand operand

If a single-bit bitfield takes up the sign bit of a storage unit, comparing the corresponding bitfield between two objects loads the storage units, XORs them, converts the result to signed char, and compares it with zero: ((signed char)(a. ^ c.) >= 0). fold_truth_andor_for_ifcombine recognizes t

[committed] lto: Fix empty fnctl.h build error with MinGW.

MSYS2+MinGW contains headers without defining expected contents. This fix checks that the fcntl function is actually defined. Bootstrapped/regtested on x86_64-linux. Committed as obvious. gcc/ChangeLog: * lockfile.cc (LOCKFILE_USE_FCNTL): New. (lockfile::lock_write): Use LOCKFILE

[committed] lto: Pass cache checksum by reference [PR118181]

Bootstrapped/regtested on x86_64-linux. Committed as obvious. PR lto/118181 gcc/ChangeLog: * lto-ltrans-cache.cc (ltrans_file_cache::create_item): Pass checksum by reference. * lto-ltrans-cache.h: Likewise. --- gcc/lto-ltrans-cache.cc | 2 +- gcc/lto-ltrans-cache

Re: [PATCH] [ifcombine] propagate signbit mask to XOR right-hand operand

On Mon, 13 Jan 2025, Alexandre Oliva wrote: > > If a single-bit bitfield takes up the sign bit of a storage unit, > comparing the corresponding bitfield between two objects loads the > storage units, XORs them, converts the result to signed char, and > compares it with zero: ((signed char)(a. ^ c

Re: [PATCH V4 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension.

Hi, Kito: The reason is not the patch set itself. Must merge Jiawei and Shihua's patches first that are [PATCH V2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip extension's testcases. and [PATCH v3 1/2] RISC-V: Update Xsfvfnrcl

[PATCH v2 2/4] RISC-V: Add Zicfilp ISA extension.

This patch only support landing pad value is 1. The next version will implement function signature based labeling scheme. RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi gcc/ChangeLog: * gcc/common/config/riscv/riscv-common.cc: Add ZICFILP ISA string. * gcc/config.gc

[PATCH v2 1/4] RISC-V: Add Zicfiss ISA extension.

This patch is implemented according to the RISC-V CFI specification. It supports the generation of shadow stack instructions in the prologue, epilogue, non-local gotos, and unwinding. RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi gcc/ChangeLog: * common/config/riscv/riscv-common.cc:

[PATCH v2 4/4] RISC-V: Add -fcf-protection=[full|branch|return] to enable zicfiss, zicfilp.

gcc/ChangeLog: * gcc/config/riscv/riscv.cc (is_zicfilp_p): New function. (is_zicfiss_p): New function. * gcc/config/riscv/riscv-zicfilp.cc: Update. * gcc/config/riscv/riscv.h: Update. * gcc/config/riscv/riscv.md: Update. gcc/testsuite/ChangeLog:

[PATCH v2] c: improve UX for -Wincompatible-pointer-types [PR116871]

On Sat, 2025-01-11 at 20:51 +0100, Jakub Jelinek wrote: > On Sat, Jan 11, 2025 at 08:25:32PM +0100, Jakub Jelinek wrote: > > That is not true. > > Implementation-wise, in C17 say > void foo (); > void bar (void); > TYPE_ARG_TYPES (TREE_TYPE (foo_decl)) == NULL > TYPE_ARG_TYPES (TREE_TYPE (bar_decl

[PATCH] c++: Inhibit subsequent warnings/notes in diagnostic_groups with an inhibited warning [PR118163,PR118392]

Hi, On 9 Jan 2025, at 20:08, Simon Martin wrote: > On 9 Jan 2025, at 20:00, Marek Polacek wrote: > >> On Thu, Jan 09, 2025 at 12:05:43PM -0500, Patrick Palka wrote: >>> On Wed, 8 Jan 2025, Jason Merrill wrote: >>> On 12/21/24 11:35 AM, Simon Martin wrote: > When erroring out due to an in

Re: [PATCH, v2] Fortran: implement F2018 intrinsic OUT_OF_RANGE [PR115788]

Hi Thomas, Am 11.01.25 um 23:38 schrieb Thomas Koenig: Hi Harald, Thanks for pointing this out!  I've also added a few gcc_unreachable() to prevent other potential false positives, see attached. Just a couple of documentation nits:  The documentation says INTEGER or REAL only, but it also wo

[PATCH] c++: Inhibit subsequent warnings/notes in diagnostic_groups with an inhibited warning [PR118163,PR118392]

[ Fixing David’s email address :-/ ] Hi, On 9 Jan 2025, at 20:08, Simon Martin wrote: > On 9 Jan 2025, at 20:00, Marek Polacek wrote: > >> On Thu, Jan 09, 2025 at 12:05:43PM -0500, Patrick Palka wrote: >>> On Wed, 8 Jan 2025, Jason Merrill wrote: >>> On 12/21/24 11:35 AM, Simon Martin wrote

Re: [patch, fortran] Dump all symbol attributes with -fdump-fortran-original

Hi Thomas, Am 12.01.25 um 19:33 schrieb Thomas Koenig: Hell world, after finding that an attribute I was looking for was not in the -fdump-fortran-original dump, I started putting in attributes and didn't stop until I had them all (or so I hope :-)  It should be easier to read than looking at t

Re: [PATCH v3] RISC-V: Fix riscv_modes_tieable_p

Compared to the patch v2, I added Zfinx check and Zfh check. Please help to review again. Thanks, Zhijin >From 9ddb402cebe868050ebc2f75e4d87238161411b4 Mon Sep 17 00:00:00 2001 From: Zhijin Zeng Date: Sat, 11 Jan 2025 12:09:11 +0800 Subject: [PATCH] RISC-V: Fix mode compatibility between floati

Re: [PATCH v2] RISC-V: Fix ICE for unrecognizable insn `UNSPEC_VSETVL` for XTheadVector

> > Looking at the log for the reload pass, it is found that "Changing pseudo > > 209 > > in operand 3 of insn 69 on equiv 0x 1". It converts the vl operand in insn > > from the expected register(reg:DI 209) to the constant 1(const_int 1 [0x1]). > > > > This conversion occurs because, although the

Re: [PATCH] crc: Fix up some crc related wrong code issues [PR117997, PR118415]

On 1/12/25 11:47 AM, Jakub Jelinek wrote: Hi! As mentioned in the second PR, using table names like crc_table_for_crc_8_polynomial_0x12 in the user namespace is wrong, user could have defined such variables in their code and as can be seen on the last testcase, then it just misbehaves. At min

Re: [PATCH] crc: Fix up some crc related wrong code issues [PR117997, PR118415]

On 1/12/25 11:47 AM, Jakub Jelinek wrote: Hi! As mentioned in the second PR, using table names like crc_table_for_crc_8_polynomial_0x12 in the user namespace is wrong, user could have defined such variables in their code and as can be seen on the last testcase, then it just misbehaves. At min

Re: [patch, fortran] Dump all symbol attributes with -fdump-fortran-original

Hi Harald, there is one irregularity here (partial lower case instead of consistently upper case: +  if (attr->oacc_declare_copyin) +    fputs (" OACC-DECLARE-copyin", dumpfile); Otherwise this is OK. Thanks for catching this! Committed with the fix as r15-6840-gf4fa0b7d493a4ba217d989d3df75