Re: [PATCH] ifcombine field merge: handle bitfield zero tests in range tests

> Am 18.12.2024 um 03:19 schrieb Alexandre Oliva : > >  > Some bitfield compares with zero are optimized to range tests, so > instead of X & ~(Bit - 1) != 0 what reaches ifcombine is X > (Bit - 1), > where Bit is a power of two and X is unsigned. > > This patch recognizes this optimized form

Re: [PATCH 0/5] LoongArch: CRC optimization

在 2024/12/16 下午9:19, Xi Ruoyao 写道: A generic CRC optimization pass has been implemented in r15-5850. But without target-specific code, it'll only optimize the CRC loop to a table lookup. With LoongArch-specific code we can do it better: for 64-bit LoongArch and the IEEE 802.3 polynomial or th

Re: [PATCH] noncontiguous ifcombine: skip marking of non-SSA_NAMEs [PR117915]

> Am 17.12.2024 um 14:35 schrieb Alexandre Oliva : > >  > When ifcombine_mark_ssa_name is called directly, rather than by > ifcombine_mark_ssa_name_walk, we need to check that name is an > SSA_NAME at the caller or in the function itself. For convenience and > safety, I'm moving the checks fr

[PATCH v2] LoongArch: Support immediate_operand for vec_cmp

We can't vectorize the code into instructions like vslti.w that compare with immediate_operand, because we miss immediate_operand support for integer comparisons. gcc/ChangeLog: * config/loongarch/lasx.md (vec_cmp): Remove. (vec_cmpu): Remove. * config/loongarch/loongarch.

[PATCH v2] LoongArch: Implement vector cbranch optab for LSX and LASX

In order to support vectorization of loops with multiple exits, this patch adds the implementation of the conditional branch optab for LoongArch LSX/LASX instructions. This patch causes the gen-vect-{2,25}.c tests to fail. This is because the support for vectorizing loops with multiple exits has

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