On 10/1/24 12:44 PM, Simon Martin wrote:
Hi Jason,
On 30 Sep 2024, at 19:56, Jason Merrill wrote:
On 9/23/24 4:44 AM, Simon Martin wrote:
Hi Jason,
On 20 Sep 2024, at 18:01, Jason Merrill wrote:
On 9/20/24 5:21 PM, Simon Martin wrote:
The following code triggers an ICE
=== cut here ===
c
The problem here is remove_unused_var is called on a name that is
defined by a phi node but it deletes it like removing a normal statement.
remove_phi_node should be called rather than gsi_remove for phinodes.
Note there is a possibility of using simple_dce_from_worklist instead
but that is for an
On Wed, Sep 11, 2024 at 11:26:42PM +0200, Jakub Jelinek wrote:
> Hi!
>
> The following patch implements the clang -Wheader-guard warning, which warns
> if a valid multiple inclusion header guard's #ifndef/#if !defined directive
> is immediately (no other non-line directives nor other (non-comment)
Marek Polacek writes:
> On Wed, Sep 11, 2024 at 11:26:42PM +0200, Jakub Jelinek wrote:
> [...]
>> --- gcc/testsuite/c-c++-common/cpp/Wheader-guard-1-1.h.jj2024-09-11
>> 19:26:39.912834079 +0200
>> +++ gcc/testsuite/c-c++-common/cpp/Wheader-guard-1-1.h 2024-09-11
>> 19:02:02.414054285
On Tue, Oct 01, 2024 at 11:10:03AM +0100, Jonathan Wakely wrote:
> Let's use an inline variable. A function-local static requires
> __cxa_guard_acquire, which (for some targets, including the ones
> affected by this change) uses __gthread_active_p which will
> recursively re-enter the variable's in
Soumya AR writes:
> Currently, we vectorize CTZ for SVE by using the following operation:
> .CTZ (X) = (PREC - 1) - .CLZ (X & -X)
>
> Instead, this patch expands CTZ to RBIT + CLZ for SVE, as suggested in
> PR109498.
>
> The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression
Kyrylo Tkachov writes:
> Hi all,
> I'd like to use a value of 64 bytes for the L1 cache size for Armv9-A
> generic tuning.
> As described in g:9a99559a478111f7fbeec29bd78344df7651c707 this value is used
> to set the std::hardware_destructive_interference_size value which we want to
> be not overly
On Sun, Sep 29, 2024 at 5:28 PM Jeff Law wrote:
>
>
>
> On 9/25/24 2:30 AM, Eikansh Gupta wrote:
> > This patch simplify `min(a,b) op max(a,b)` to `a op b`. This optimization
> > will work for all the binary commutative operations. So, the `op` here can
> > be one of {plus, mult, bit_and, bit_xor,
On Sat, 28 Sept 2024 at 18:37, Jason Merrill wrote:
>
> On 9/27/24 7:29 PM, Nathaniel Shead wrote:
> > On Fri, Sep 27, 2024 at 03:55:14PM -0400, Jason Merrill wrote:
> >> On 9/27/24 3:38 PM, Jonathan Wakely wrote:
> >>> On Fri, 27 Sept 2024 at 19:46, Jason Merrill wrote:
>
> On 9/26/24
On Tue, Sep 24, 2024 at 10:58 AM Eikansh Gupta
wrote:
>
> This patch simplify `(trunc)copysign ((extend)x, CST)` to `copysign (x,
> -1.0/1.0)`
> depending on the sign of CST. Previously, it was simplified to `copysign (x,
> CST)`.
> It can be optimized as the sign of the CST matters, not the val
Hi Jason,
On 30 Sep 2024, at 19:56, Jason Merrill wrote:
> On 9/23/24 4:44 AM, Simon Martin wrote:
>> Hi Jason,
>>
>> On 20 Sep 2024, at 18:01, Jason Merrill wrote:
>>
>>> On 9/20/24 5:21 PM, Simon Martin wrote:
The following code triggers an ICE
=== cut here ===
class base {}
On 10/1/2024 2:07 PM, Richard Sandiford wrote:
writes:
Introduce two new unspecs, UNSPEC_COND_SMAX and UNSPEC_COND_SMIN,
corresponding to rtl operators smax and smin. UNSPEC_COND_SMAX is used
to generate fmaxnm instruction and UNSPEC_COND_SMIN is used to generate
fminnm instruction.
With th
On 9/30/24 8:16 AM, Yangyu Chen wrote:
Currently, we lack support for TARGET_CAN_INLINE_P on the RISC-V
ISA. As a result, certain functions cannot be optimized with inlining
when specific options, such as __attribute__((target("arch=+v"))) .
This can lead to potential performance issues when b
writes:
> The AArch64 FEAT_FAMINMAX extension introduces instructions for
> computing the floating point absolute maximum and minimum of the
> two vectors element-wise.
>
> This patch adds code generation for famax and famin in terms of existing
> unspecs. With this patch:
> 1. famax can be expres
On Sat, 2024-09-21 at 19:43 +0200, Jakub Jelinek wrote:
> Hi!
>
> It seems that we currently require
> 1) enabling at least c,c++,fortran,d in --enable-languages
> 2) first doing make html
> before one can successfully regenerate-opt-urls, otherwise without 2)
> one gets
> make regenerate-opt-urls
This is another case of load hoisting breaking UID order in the
preheader, this time between two hoistings. The easiest way out is
to do what we do for the main stmt - copy instead of move.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
PR tree-optimization/116902
P
On Tue, 1 Oct 2024 at 14:05, Frank Scheiner wrote:
>
> Hi Jonathan,
>
> On 01.10.24 11:28, Jonathan Wakely wrote:
> > On Mon, 30 Sept 2024 at 18:26, Frank Scheiner wrote:
> >> The following patch adds a workaround for this on the libstdc++
> >> testsuite side.
> >
> > Thanks for the patch. Please
Hi Tomáš,
one small nit: I would prefer to use i = -1 as the initializer for component of
the derived type, because 0 is a default generated one and that way one can
distinguish them. With that, ok for mainline and thanks for the patch.
- Andre
On Wed, 25 Sep 2024 17:20:12 +0200
Tomáš Trnka wro
Hi Andre,
On 9/27/24 15:17, Andre Vieira (lists) wrote:
Resending as v2 so CI picks it up.
v2 LGTM
Thanks,
Christophe
This patch refactors and fixes an issue where
arm_mve_dlstp_check_dec_counter
was making an assumption about the form of what a candidate for a dec_insn.
This dec_insn i
Hi!
Ranger cache during initialization reserves number of basic block slots
in the m_workback vector (in an inefficient way by doing create (0)
and safe_grow_cleared (n) and truncate (0) rather than say create (n)
or reserve (n) after create). The problem is that some passes split bbs and/or
crea
This patch implements 4 rules for logarithmic identities in match.pd
under -funsafe-math-optimizations:
1) logN(1.0/a) -> -logN(a). This avoids the division instruction.
2) logN(C/a) -> logN(C) - logN(a), where C is a real constant. Same as 1).
3) logN(a) + logN(b) -> logN(a*b). This reduces the nu
Applied this patchlet for a build warning.
Johann
--
AVR: avr-passes.cc - Fix a build warning.
gcc/
* config/avr/avr-passes.cc
(avr_split_fake_addressing_move): Fix
a build warning.
diff --git a/gcc/config/avr/avr-passes.cc b/gcc/config/avr/avr-passes.cc
inde
0001-RISC-V-libgcc-Fix-incorrect-and-missing-.cfi_offset-.patch
Description: Binary data
Andrew Carlotti writes:
> This is necessary to prevent reload assuming that a direct FP->FPMR move
> is valid.
>
> Bootstrapped and regression tested; ok for master?
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64.cc (aarch64_register_move_cost):
> Increase costs involving MOVEABLE_SYS
This is necessary to prevent reload assuming that a direct FP->FPMR move
is valid.
Bootstrapped and regression tested; ok for master?
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_register_move_cost):
Increase costs involving MOVEABLE_SYSREGS.
diff --git a/gcc/config/aarc
On Thu, 12 Sep 2024, Patrick Palka wrote:
> (Sorry to resurrect this thread so late, I lost track of this patch...)
>
> On Fri, 2 Dec 2022, Jason Merrill wrote:
>
> > On 12/2/22 09:30, Patrick Palka wrote:
> > > On Thu, 1 Dec 2022, Jason Merrill wrote:
> > >
> > > > On 12/1/22 14:51, Patrick Pa
> On 1 Oct 2024, at 09:48, Tamar Christina wrote:
>
> External email: Use caution opening links or attachments
>
>
> Hi Soumya,
>
> Nice patch!
>
>> -Original Message-
>> From: Kyrylo Tkachov
>> Sent: Tuesday, October 1, 2024 7:55 AM
>> To: Soumya AR
>> Cc: gcc-patches@gcc.gnu.or
Andrew Carlotti writes:
> I've tested this with a hacked in FP8 intrinsic.
Looks good.
> Is this patch ok for master,
> or should it wait until we've implemented the intrinsics?
IMO it would be OK to apply...
> @@ -1190,6 +1194,10 @@ aarch64_init_simd_builtin_types (void)
>aarch64_simd_typ
Jennifer Schmitz writes:
> This patch implements the optabs reduc_and_scal_,
> reduc_ior_scal_, and reduc_xor_scal_ for Advanced SIMD
> integers for TARGET_SVE in order to use the SVE instructions ANDV, ORV, and
> EORV for fixed-width bitwise reductions.
> For example, the test case
>
> int32_t fo
Hi Soumya,
Nice patch!
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Tuesday, October 1, 2024 7:55 AM
> To: Soumya AR
> Cc: gcc-patches@gcc.gnu.org; Richard Sandiford
> Subject: Re: [PATCH] aarch64: Optimise calls to ldexp with SVE FSCALE
> instruction
>
> Hi Soumya
>
> > On 3
On Tue, Oct 1, 2024 at 12:01 PM Eric Botcazou wrote:
>
> Hi,
>
> the attached Ada testcase compiled with -O -flto exhibits a wrong code issue
> when the 3 optimizations NRV + RSO + inlining are applied to the same call: if
> the LHS of the call is marked write-only before inlining, then it will ke
On 10/1/24 7:31 AM, Giuseppe D'Angelo wrote:
Hello,
Attaching an updated patch.
Thanks, I'm pushing this with a few tweaks:
+unaccessible base class of @var{derived_type}.
"inaccessible"
+ const bool via_virtual =
+ binfo_via_virtual (binfo, data->t) != NULL_TREE;
Moved
Hi!
Some passes like the bitint lowering queue some statements on edges and only
commit them at the end of the pass. If they use ranger at the same time,
the ranger might see such SSA_NAMEs and ICE on those. The following patch
instead just punts on them.
Bootstrapped/regtested on x86_64-linux
> On 12 Sep 2024, at 16:43, Eric Gallager wrote:
>
>
>
> On Wed, Sep 11, 2024 at 11:51 AM Srinath Parvathaneni
> wrote:
>>
>> This patch adds support for aarch64 gcs build attributes.
>
> Hi, just wondering if you could clarify what "GCS" stands for in this
> context? When I see it, my fir
GCC maintainers:
Version 2: Fixed the wording in the changelog per the feedback. With
this change the patch was approved by Kewen.
The patch removed the built-in __builtin_vsx_xvcvuxwdp as it is covered
by the overloaded vec_doubleo built-in.
The patch has been tested on Power 10 LE and
GCC maintainers:
Version 2, fixed the changelog, updated the wording in the documentation
and updated the argument types in the vsx-builtin-3.c test file.
The following patch adds missing test cases for the overloaded vec_perm
built-in. It also fixes and issue with printing the 128-bit va
Hi Jonathan,
On 01.10.24 11:28, Jonathan Wakely wrote:
On Mon, 30 Sept 2024 at 18:26, Frank Scheiner wrote:
The following patch adds a workaround for this on the libstdc++
testsuite side.
Thanks for the patch. Please CC libstd...@gcc.gnu.org for all
libstdc++ patches, as per https://gcc.gnu.o
writes:
> Introduce two new unspecs, UNSPEC_COND_SMAX and UNSPEC_COND_SMIN,
> corresponding to rtl operators smax and smin. UNSPEC_COND_SMAX is used
> to generate fmaxnm instruction and UNSPEC_COND_SMIN is used to generate
> fminnm instruction.
>
> With these new unspecs, we can generate SVE2 max/
I just pushed it to the trunk.
Thanks,
Saurabh
On 9/20/2024 3:09 PM, Claudio Bantaloukas wrote:
The ACLE defines a new scalar type, __mfp8. This is an opaque 8bit types that
can only be used by fp8 intrinsics. Additionally, the mfloat8_t type is made
available in arm_neon.h and arm_sve.h as an
On Mon, 30 Sept 2024 at 18:26, Frank Scheiner wrote:
>
> We see:
>
> ```
> FAIL: 17_intro/names.cc -std=gnu++17 (test for excess errors)
> FAIL: 17_intro/names_pstl.cc -std=gnu++17 (test for excess errors)
> FAIL: experimental/names.cc -std=gnu++17 (test for excess errors)
> ```
>
> ...on ia64-l
GCC maintainers:
version 2, added the reference to the patch where the removal of the
built-ins was missed. Note, patch was approved by Kewen with this change.
The following patch removes two redundant built-ins
__builtin_vsx_vperm_8hi and __builtin_vsx_vperm_8hi_uns. The built-ins
are c
GCC maintainers:
Version 2, added the argument changes for the__builtin_vsx_uns_double[e
| o | h | l ]_v4si built-ins. Added support to the vector {un,}signed
int to vector float builtins so they are supported using Altivec
instructions if VSX is not available per the feedback comments.
Th
On Mon, 16 Sep 2024, Patrick Palka wrote:
> On Thu, 30 Nov 2023, Patrick Palka wrote:
>
> > On Fri, 3 Nov 2023, Patrick Palka wrote:
> >
> > > On Tue, 3 May 2022, Jason Merrill wrote:
> > >
> > > > On 5/2/22 14:50, Patrick Palka wrote:
> > > > > Currently when checking the constraints of a clas
Hi Thomas,
one small nit:
diff --git a/gcc/fortran/check.cc b/gcc/fortran/check.cc
index dd79a49a0c9..afab66a901f 100644
--- a/gcc/fortran/check.cc
+++ b/gcc/fortran/check.cc
@@ -637,6 +637,38 @@ int_or_real_or_char_check_f2003 (gfc_expr *e, int n)
return true;
}
+/* Check that an expression
On Mon, Sep 30, 2024 at 11:50 PM Andrew Pinski wrote:
>
> Take:
> ```
> if (t_3(D) != 0)
> goto ;
> else
> goto ;
>
>
> _8 = c_4(D) != 0;
> _9 = (int) _8;
>
>
> # e_2 = PHI <_9(3), 0(2)>
> ```
>
> We should factor out the conversion here as that will allow a simplfication t
The AArch64 FEAT_FAMINMAX extension introduces instructions for
computing the floating point absolute maximum and minimum of the
two vectors element-wise.
This patch adds code generation for famax and famin in terms of existing
unspecs. With this patch:
1. famax can be expressed as taking UNSPEC_
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, September 24, 2024 12:29 PM
> To: Prathamesh Kulkarni
> Cc: Richard Sandiford ; Thomas Schwinge
> ; gcc-patches@gcc.gnu.org
> Subject: RE: Re-compute TYPE_MODE and DECL_MODE while streaming in for
> accelerator
>
> External e
Introduce two new unspecs, UNSPEC_COND_SMAX and UNSPEC_COND_SMIN,
corresponding to rtl operators smax and smin. UNSPEC_COND_SMAX is used
to generate fmaxnm instruction and UNSPEC_COND_SMIN is used to generate
fminnm instruction.
With these new unspecs, we can generate SVE2 max/min instructions us
Hi Jonathan, Joseph,
On 01.10.24 15:32, Jonathan Wakely wrote:
On Tue, 1 Oct 2024 at 14:05, Frank Scheiner wrote:
On 01.10.24 11:28, Jonathan Wakely wrote:
On Mon, 30 Sept 2024 at 18:26, Frank Scheiner wrote:
It looks like the glibc header also defines "bits" without using the
implementation
On Tue, 1 Oct 2024 at 16:53, Frank Scheiner wrote:
>
> Hi Jonathan, Joseph,
>
> On 01.10.24 15:32, Jonathan Wakely wrote:
> > On Tue, 1 Oct 2024 at 14:05, Frank Scheiner wrote:
> >> On 01.10.24 11:28, Jonathan Wakely wrote:
> >>> On Mon, 30 Sept 2024 at 18:26, Frank Scheiner wrote:
> >>> It looks
On Thu, Sep 26, 2024 at 2:25 PM wrote:
>
> From: Pan Li
>
> This patch would like to support the form 2 of the scalar signed
> integer SAT_SUB. Aka below example:
>
> Form 2:
> #define DEF_SAT_S_SUB_FMT_2(T, UT, MIN, MAX) \
> T __attribute__((noinline)) \
> sat_s_sub_##T##
When we're computing ANTIC for PRE we treat edges to not yet visited
blocks as having a maximum ANTIC solution to get at an optimistic
solution in the iteration. That assumes the edges visted eventually
execute. This is a wrong assumption that can lead to wrong code
(and not only non-optimality)
The following avoids querying ranges of vector entities.
Bootstrapped on x86_64-unknown-linux-gnu, testing in progress.
Richard.
PR tree-optimization/116905
* tree-vect-stmts.cc (supportable_indirect_convert_operation):
Fix guard for vect_get_range_info.
* gcc.dg
writes:
> The AArch64 FEAT_FAMINMAX extension introduces instructions for
> computing the floating point absolute maximum and minimum of the
> two vectors element-wise.
>
> This patch introduces SVE2 faminmax intrinsics. The intrinsics of this
> extension are implemented as the following builtin f
The following adds SLP support for vectorizing single-lane inductions
with variable length vectors.
Bootstrapped and tested on x86_64-unknown-linux-gnu.
PR tree-optimization/116566
* tree-vect-loop.cc (vectorizable_induction): Handle single-lane
SLP for VLA vectors.
---
g
Hi,
the attached Ada testcase compiled with -O -flto exhibits a wrong code issue
when the 3 optimizations NRV + RSO + inlining are applied to the same call: if
the LHS of the call is marked write-only before inlining, then it will keep
the mark after inlining although it may be read in GIMPLE f
Hi all,
this rather old PR reported a parsing bug, when a coarray'ed character substring
ref is to be parsed, aka CHARACTER(:) :: str[:] ... str(2:5). In this case the
parser confused the substring ref with an array-ref, because an array_spec was
present. This patch fixes this by requesting only c
From: Saurabh Jha
This patch series a revised version of an earlier patch series:
https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662951.html.
The main change in this patch series is the introduction of the two
unspecs, UNSPEC_COND_SMAX and UNSPEC_COND_SMIN, and using them for
existing
On Mon, Sep 30, 2024 at 8:40 PM Tamar Christina wrote:
>
> Hi Victor,
>
> Thanks! This looks good to me with one minor comment:
>
> > -Original Message-
> > From: Victor Do Nascimento
> > Sent: Monday, September 30, 2024 2:34 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Tamar Christina ; ri
The AArch64 FEAT_FAMINMAX extension introduces instructions for
computing the floating point absolute maximum and minimum of the
two vectors element-wise.
This patch introduces SVE2 faminmax intrinsics. The intrinsics of this
extension are implemented as the following builtin functions:
* sva[max
I've tested this with a hacked in FP8 intrinsic. Is this patch ok for master,
or should it wait until we've implemented the intrinsics?
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc (MODE_d_mf8): New.
(MODE_q_mf8): New.
(QUAL_mf8): New.
(aarch64_lookup_simd_
Tamar Christina writes:
> Thanks for the review,
> Will get started on it but one question...
>
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Monday, September 30, 2024 6:33 PM
>> To: Tamar Christina
>> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
>> ; Marcus Shawcroft
On Tue, 1 Oct 2024, Jennifer Schmitz wrote:
> This patch implements 4 rules for logarithmic identities in match.pd
> under -funsafe-math-optimizations:
> 1) logN(1.0/a) -> -logN(a). This avoids the division instruction.
> 2) logN(C/a) -> logN(C) - logN(a), where C is a real constant. Same as 1).
>
With single-lane SLP we miss to use the power realing loads causing
some testsuite FAILs. r14-2430-g4736ddd11874fe exempted SLP of
non-grouped accesses because that could have been only splats
where the scheme isn't used anyway, but now with single-lane SLP
it can be contiguous accesses.
Bootstra
GCC maintainers:
The following version 2 of a series of patches for PowerPC removes some
built-ins that are covered by existing overloaded built-ins.
Additionally, there are patches to add missing testcases and
documentation. The original version of the patch series was posted on
8/7/2024.
On 10/1/24 1:25 AM, Tsung Chun Lin wrote:
0001-RISC-V-libgcc-Fix-incorrect-and-missing-.cfi_offset-.patch
From 06a370a0a2329dd4da0ffcab7c35ea7df2353baf Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Tue, 1 Oct 2024 14:42:56 +0800
Subject: [PATCH] RISC-V/libgcc: Fix incorrect and missing .cfi_
Applied as obvious.
Johann
--
AVR: avr.cc - Drop a superfluous sub-condition in avr_out_compare.
In avr.cc::avr_out_compare() there is this condition:
if (n_bytes == 4
&& eqne_p
&& AVR_HAVE_ADIW
&& REGNO (xreg) >= REG_22
&& (xval == const0
Hello,
Attaching an updated patch.
Thank you,
--
Giuseppe D'Angelo
From 14f433c3ab7e9f14f9b0ce8efc56871bfb780928 Mon Sep 17 00:00:00 2001
From: Giuseppe D'Angelo
Date: Mon, 29 Jul 2024 17:43:20 +0200
Subject: [PATCH] Introduce __builtin_is_virtual_base_of
P2985R0 (C++26) introduces std::is_vir
From: Richard Biener
Hi, this is the backport of the fix for PR116585 to GCC14.
bootstrapped and regress tested on both X86 and aarch64.
Okay for committing?
thanks.
Qing.
===
split_constant_offset when looking through SSA defs can end up
picking SSA leafs that ar
From: Richard Biener
Hi, this is the backport of the fix for PR116585 to GCC13.
bootstrapped and regress tested on both X86 and aarch64.
Okay for committing?
thanks.
Qing.
===
split_constant_offset when looking through SSA defs can end up
picking SSA leafs that are subject to abnormal coa
From: Richard Biener
Hi, this is the backport of the fix for PR116585 to GCC12.
bootstrapped and regress tested on both X86 and aarch64.
Okay for committing?
thanks.
Qing.
split_constant_offset when looking through SSA defs can end up
picking SSA leafs that are subje
Hi Jennifer,
> -Original Message-
> From: Jennifer Schmitz
> Sent: Tuesday, September 24, 2024 9:23 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Tamar Christina ; Richard Sandiford
> ; Kyrylo Tkachov
> Subject: Re: [RFC][PATCH] AArch64: Remove
> AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
>
>
>
Hi Jennifer,
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, October 1, 2024 12:20 PM
> To: Jennifer Schmitz
> Cc: gcc-patches@gcc.gnu.org; Kyrylo Tkachov
> Subject: Re: [PATCH] [PR113816] AArch64: Use SVE bit op reduction for vector
> reductions
>
> Jennifer Schmitz w
Hi Andre,
Am 01.10.24 um 09:43 schrieb Andre Vehreschild:
Hi all,
this rather old PR reported a parsing bug, when a coarray'ed character substring
ref is to be parsed, aka CHARACTER(:) :: str[:] ... str(2:5). In this case the
parser confused the substring ref with an array-ref, because an array
Tested x86_64-pc-linux-gnu, applying to trunk.
-- 8< --
There have been various problems with -std=c++14 -fconcepts; let's stop
defining the feature test macro in that case.
gcc/c-family/ChangeLog:
* c-cppbuiltin.cc (c_cpp_builtins): Don't define __cpp_concepts
before C++17.
---
Phiopt match_and_simplify might move a well defined VCE assign statement
from being conditional to being uncondtitional; that VCE might no longer
being defined. It will need a rewrite into a cast instead.
This adds the rewriting code to move_stmt for the VCE case.
This is enough to fix the issue a
Hi,
this changes the stack checking method (that of -fstack-check) used on Linux
from the traditional model (probe then move SP) to the model implemented for
-fstack-clash-protection (probe while moving SP). The rationale is that the
latter is in widespread use on Linux and thus thought to be mor
gcc.target/powerpc/p9-vec-length-full-8.c was expecting all loops to
use -with-len fully masked vectorization to avoid epilogues because
the loops needed peeling for gaps. With SLP we have improved things
here and the loops using V2D[IF]mode no longer need peeling for gaps
since the target can com
As we now SLP non-grouped stores we have to adjust the expected
count.
Pushed.
PR testsuite/116654
* gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c: Adjust.
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --
I missed { dg-add-options float16 }.
Pushed.
* gcc.dg/pr116905.c: Add float16 options.
---
gcc/testsuite/gcc.dg/pr116905.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/pr116905.c b/gcc/testsuite/gcc.dg/pr116905.c
index 0a2b96ac1c1..89de8525b25 100644
--- a/gcc
On Tue, 1 Oct 2024, Qing Zhao wrote:
> From: Richard Biener
>
> Hi, this is the backport of the fix for PR116585 to GCC14.
> bootstrapped and regress tested on both X86 and aarch64.
>
> Okay for committing?
OK.
> thanks.
>
> Qing.
>
> ===
>
> split_constant_offs
On Tue, 1 Oct 2024, Qing Zhao wrote:
> From: Richard Biener
>
> Hi, this is the backport of the fix for PR116585 to GCC13.
> bootstrapped and regress tested on both X86 and aarch64.
>
> Okay for committing?
OK.
> thanks.
>
> Qing.
>
> ===
> split_constant_offset when looking through SSA
On Tue, 1 Oct 2024, Qing Zhao wrote:
> From: Richard Biener
>
> Hi, this is the backport of the fix for PR116585 to GCC12.
> bootstrapped and regress tested on both X86 and aarch64.
>
> Okay for committing?
OK.
> thanks.
>
> Qing.
>
>
>
> split_constant_offset when
Hi,
the macro is documented like this in the internal manual:
-- Macro: WIDEST_HARDWARE_FP_SIZE
A C expression for the size in bits of the widest floating-point
format supported by the hardware. If you define this macro, you
must specify a value less than or equal to mode precisi
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