Re: [PATCH v1] Match: Support form 2 for scalar signed integer .SAT_ADD

2024-09-10 Thread Richard Biener
On Tue, Sep 10, 2024 at 1:05 AM Li, Pan2 wrote: > > Thanks Richard for comments. > > >> + The T and UT are type pair like T=int8_t, UT=uint8_t. */ > >> +(match (signed_integer_sat_add @0 @1) > >> + (cond^ (ge (bit_and:c (bit_xor:c @0 (nop_convert@2 (plus (nop_convert @0) > >> +

Re: [PATCH v2 1/2] RISC-V: Fix ICE caused by early ggc_free on DECL for RVV intrinsics in LTO.

2024-09-10 Thread Richard Biener
On Tue, Sep 10, 2024 at 7:56 AM Jin Ma wrote: > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc > (function_builder::add_function): > Check the final DECl to make sure it is valid. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/bug-10.c: New test

RE: [PATCH v1] Match: Support form 2 for scalar signed integer .SAT_ADD

2024-09-10 Thread Li, Pan2
Thanks a lot. > It's just the number of patterns generated > is 2^number-of-:c, so it's good to prune known unnecessary combinations. I see, will make the changes as your suggestion and commit it if no surprise from test suites. > Yes, all commutative binary operators require matching types on

[PATCH] x86: Refine V4BF/V2BF FMA Testcase

2024-09-10 Thread Levy Hsu
Simple testcase fix, ok for trunk? gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_2-partial-bf-vector-fma-1.c: Separated 32-bit scan and removed register checks in spill situations. --- .../i386/avx10_2-partial-bf-vector-fma-1.c | 12 1 file changed, 8 i

Re: [PATCH v2 1/2] RISC-V: Fix ICE caused by early ggc_free on DECL for RVV intrinsics in LTO.

2024-09-10 Thread Jin Ma
> > + /* If the code of DECL is ERROR_MARK or invalid code, usually > > "ggc_freed", we > > + use integer_zero_node instead of it. This will be very helpful for the > > + ggc_free. */ > > + if (TREE_CODE (decl) == ERROR_MARK || TREE_CODE (decl) >= MAX_TREE_CODES) > > +decl = integer

Re: [PATCH] x86: Refine V4BF/V2BF FMA Testcase

2024-09-10 Thread Hongtao Liu
On Tue, Sep 10, 2024 at 3:35 PM Levy Hsu wrote: > > Simple testcase fix, ok for trunk? Ok. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/avx10_2-partial-bf-vector-fma-1.c: Separated 32-bit > scan > and removed register checks in spill situations. > --- > .../i386/avx10_2-par

[COMMITTED 1/7] ada: Whitespace cleanup in declaration of calendar-related routines

2024-09-10 Thread Marc Poulhiès
From: Piotr Trojanek Code cleanup. gcc/ada/ * libgnat/s-os_lib.ads: Remove extra whitespace. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/libgnat/s-os_lib.ads | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/ada/libgnat/s-os_lib.

Re: [PATCH v2 1/2] RISC-V: Fix ICE caused by early ggc_free on DECL for RVV intrinsics in LTO.

2024-09-10 Thread Richard Biener
On Tue, Sep 10, 2024 at 9:38 AM Jin Ma wrote: > > > > + /* If the code of DECL is ERROR_MARK or invalid code, usually > > > "ggc_freed", we > > > + use integer_zero_node instead of it. This will be very helpful for > > > the > > > + ggc_free. */ > > > + if (TREE_CODE (decl) == ERROR_M

[COMMITTED 3/7] ada: Evaluate calls to GNAT.Source_Info routines in semantic checking

2024-09-10 Thread Marc Poulhiès
From: Piotr Trojanek When semantic checking mode is active, i.e. when switch -gnatc is present or when the frontend is operating in the GNATprove mode, we now rewrite calls to GNAT.Source_Info routines in evaluation and not expansion (which is disabled in these modes). This is needed to recogniz

[COMMITTED 7/7] ada: Include missing associated header file

2024-09-10 Thread Marc Poulhiès
From: Eric Botcazou memmodel.h must be included alongside tm_p.h for the sake of the SPARC port. gcc/ada/ * gcc-interface/misc.cc: Include memmodel.h before tm_p.h. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/gcc-interface/misc.cc | 1 + 1 file changed, 1 insertio

[COMMITTED 2/7] ada: Simplify code for inserting checks into expressions

2024-09-10 Thread Marc Poulhiès
From: Piotr Trojanek Code cleanup; semantics is unaffected. gcc/ada/ * checks.adb (Remove_Checks): Combine CASE alternatives. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/checks.adb | 34 -- 1 file changed, 12 insertions(+), 22 delet

[COMMITTED 4/7] ada: Normalize span generation on different platforms

2024-09-10 Thread Marc Poulhiès
From: Viljar Indus The total number of characters on a source code line is different on Windows and Linux based systems (CRLF vs LF endings). Use the last non line change character to adjust printing the spans that go over the end of line. gcc/ada/ * diagnostics-pretty_emitter.adb (Get_

[COMMITTED 5/7] ada: First controlling parameter: report error without Extensions allowed

2024-09-10 Thread Marc Poulhiès
From: Javier Miranda Enable reporting an error when this new aspect/pragma is set to True, and the sources are compiled without language extensions allowed. gcc/ada/ * sem_ch13.adb (Analyze_One_Aspect): Call Error_Msg_GNAT_Extension() to report an error when the aspect F

[COMMITTED 6/7] ada: Use the same warning character in continuations

2024-09-10 Thread Marc Poulhiès
From: Viljar Indus gcc/ada/ * gcc-interface/decl.cc: Use same warning characters in continuation messages. * gcc-interface/trans.cc: Likewise. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/gcc-interface/decl.cc | 8 gcc/ada/gcc-interface/tr

[PATCH] Enable tune fuse_move_and_alu for GNR/GNR-D.

2024-09-10 Thread liuhongt
According to Intel Software Optimization Manual[1], the Redwood cove microarchitecture supports LD+OP and MOV+OP macro fusions. The patch enables MOV+OP tune for GNR. [1] https://www.intel.com/content/www/us/en/content-details/814198/intel-64-and-ia-32-architectures-optimization-reference-manual

Re: [PATCH] ada: Fix gcc-interface/misc.cc compilation on SPARC

2024-09-10 Thread Marc Poulhiès
Eric Botcazou writes: >> commit 72c6938f29cbeddb3220720e68add4cf09ffd794 >> Author: Eric Botcazou >> Date: Sun Aug 25 15:20:59 2024 +0200 >> >> ada: Streamline handling of low-level peculiarities of record field >> layout >> >> broke the Ada build on SPARC: >> >> In file included from ./tm

Re: [PATCH] MIPS: Add some floating point instructions support for MIPSr6

2024-09-10 Thread 梅杰
在 2024/9/3 08:30, YunQiang Su 写道: > Jie Mei 于2024年7月26日周五 14:50写道: >> >> This patch adds some floating point instructiions from mips32r6, >> for instance, MINA/MAXA.fmt, RINT.fmt, CLASS.fmt etc. >> >> Also add built-in functions to MIPSr6 to better handle tests >> for MIPSr6. >> >> gcc/ChangeLog:

Re: [PATCH] MIPS: Add some floating point instructions support for MIPSr6

2024-09-10 Thread Xi Ruoyao
On Tue, 2024-09-10 at 16:50 +0800, 梅杰 wrote: > As for the function `__builtin_rint`, although it exists, however, after > defining the instruction in `mips.md`, GCC still won't generate `RINT.fmt` > instruction for MIPS, it generates following code instead: > > > lui $28,%hi(__gnu_local_

Re: [PATCH 6/8] gcn: Add else operand to masked loads.

2024-09-10 Thread Andrew Stubbs
On 06/09/2024 09:47, Robin Dapp wrote: So we only found two instances of this problem and both were related to _Bools. In case you have more cases, it would be greatly appreciated to verify the series with them. If you don't mind, would it be possible to comment out the zeroing, re-run the test

[PATCH] tree-optimization/116658 - latent issue in vect_is_slp_load_node

2024-09-10 Thread Richard Biener
Permute nodes do not have a representative so we have to guard vect_is_slp_load_node against those. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/116658 * tree-vect-slp.cc (vect_is_slp_load_node): Make sure node isn't a permute.

Re: [PATCH v3] c++: Ensure ANNOTATE_EXPRs remain outermost expressions in conditions [PR116140]

2024-09-10 Thread Alex Coplan
On 27/08/2024 10:55, Alex Coplan wrote: > Hi, > > This is a v3 that hopefully addresses the feedback from both Jason and > Jakub. v2 was posted here: > https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660191.html Gentle ping on this C++ patch: https://gcc.gnu.org/pipermail/gcc-patches/2024-

Re: [PATCH RFA] libstdc++: fix C header include guards

2024-09-10 Thread Jonathan Wakely
On Tue, 10 Sept 2024 at 05:10, Jason Merrill wrote: > > Tested x86_64-pc-linux-gnu, OK for trunk? I'm going to have to do some digging ... I _think_ there's some obscure reason for this. Maybe a weird bootstrap situation. Or maybe I made that up as rationale for a scripting error. > > -- 8< -- >

[Patch][RFC] Fortran/OpenMP: Middle-end support for mapping of DT with allocatable components

2024-09-10 Thread Tobias Burnus
Background: OpenMP states that for 'map(var)', all allocatable components of 'var' will automatically also be mapped ('deep mapping'). Thus, for type(t), allocatable :: var(:) this leads to a pseudo code like: map(var, storage_size(var)) do i = lbound(var), ubound(var) if (allocated(va

Re: [Patch][RFC] Fortran/OpenMP: Middle-end support for mapping of DT with allocatable components

2024-09-10 Thread Jakub Jelinek
On Tue, Sep 10, 2024 at 12:19:33PM +0200, Tobias Burnus wrote: > Background: OpenMP states that for 'map(var)', all allocatable components > of 'var' will automatically also be mapped ('deep mapping'). Not a review, just a comment. This kind of recursive mapping is also what needs to happen for d

Re: [PATCH] MATCH: add abs support for half float

2024-09-10 Thread Richard Biener
On Thu, Sep 5, 2024 at 3:19 AM Kugan Vivekanandarajah wrote: > > Thanks for the explanation. > > > > On 2 Sep 2024, at 9:47 am, Andrew Pinski wrote: > > > > External email: Use caution opening links or attachments > > > > > > On Sun, Sep 1, 2024 at 4:27 PM Kugan Vivekanandarajah > > wrote: > >>

Re: [PATCH] match: Change (A * B) + (-C) to (B - C/A) * A, if C multiple of A [PR109393]

2024-09-10 Thread Richard Biener
On Fri, Sep 6, 2024 at 2:44 PM wrote: > > From: kelefth > > The following function: > > int foo(int *a, int j) > { > int k = j - 1; > return a[j - 1] == a[k]; > } > > does not fold to `return 1;` using -O2 or higher. The cause of this is that > the expression `4 * j + (-4)` for the index comp

Re: [Patch][RFC] Fortran/OpenMP: Middle-end support for mapping of DT with allocatable components

2024-09-10 Thread Tobias Burnus
Hi Jakub, Jakub Jelinek wrote: On Tue, Sep 10, 2024 at 12:19:33PM +0200, Tobias Burnus wrote: Background: OpenMP states that for 'map(var)', all allocatable components of 'var' will automatically also be mapped ('deep mapping'). Not a review, just a comment. This kind of recursive mapping is

RE: [nvptx] Pass -m32/-m64 to host_compiler if it has multilib support

2024-09-10 Thread Prathamesh Kulkarni
> -Original Message- > From: Thomas Schwinge > Sent: Monday, September 9, 2024 8:50 PM > To: Prathamesh Kulkarni ; Richard Biener > > Cc: Andrew Pinski ; gcc-patches@gcc.gnu.org; Jakub > Jelinek > Subject: RE: [nvptx] Pass -m32/-m64 to host_compiler if it has > multilib support > > Exte

[PATCH v2] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Qing Zhao
Hi, This is the 2nd version of the patch after the long discussion. We finally decided to keep the previous design that returns a pointer to the counted_by object. Compared to the first version, the major changes are: 1. change the name of the builtin from __builtin_get_counted_by to __built

Re: [PING^4] [PATCH] Add a bootstrap-native build config

2024-09-10 Thread Andi Kleen
On Tue, Sep 10, 2024 at 03:29:08AM +, Ramana Radhakrishnan wrote: > > diff --git a/config/bootstrap-native.mk b/config/bootstrap-native.mk > > new file mode 100644 > > index ..a4a3d8594089 > > --- /dev/null > > +++ b/config/bootstrap-native.mk > > @@ -0,0 +1

[RFC 0/4] Hard Register Constraints

2024-09-10 Thread Stefan Schulze Frielinghaus
This series introduces hard register constraints. The first patch enables hard register constraints for asm statements and for machine descriptions. The subsequent patch adds some basic error handling for asm statements. The third patch adds some verification of register names used in machine de

[RFC 2/4] Error handling for hard register constraints

2024-09-10 Thread Stefan Schulze Frielinghaus
This implements some basic error handling for hard register constraints including potential conflics with register asm operands. In contrast to register asm operands, hard register constraints allow more than just one register per operand. Even more than just one register per alternative. For ex

[RFC 4/4] Rewrite register asm into hard register constraints

2024-09-10 Thread Stefan Schulze Frielinghaus
Currently a register asm already materializes during expand. This means, a hard register is allocated for the very first access of a register asm as e.g. in an assignment. As a consequence this might lead to suboptimal register allocation if the assignment and the using asm statement are spread f

[RFC 1/4] Hard register constraints

2024-09-10 Thread Stefan Schulze Frielinghaus
Implement hard register constraints of the form {regname} where regname must be any valid register name for the target. Such constraints may be used in asm statements as a replacement for register asm and in machine descriptions. Due to optimizations it is not unexpected if two or more inputs req

[RFC 3/4] genoutput: Verify hard register constraints

2024-09-10 Thread Stefan Schulze Frielinghaus
Since genoutput has no information about hard register names we cannot statically verify those names in constraints of the machine description. Therefore, we have to do it at runtime. Although verification shouldn't be too expensive, restrict it to checking builds. This should be sufficient since

Re: [PATCH v3] c++: Ensure ANNOTATE_EXPRs remain outermost expressions in conditions [PR116140]

2024-09-10 Thread Jason Merrill
On 9/10/24 6:10 AM, Alex Coplan wrote: On 27/08/2024 10:55, Alex Coplan wrote: Hi, This is a v3 that hopefully addresses the feedback from both Jason and Jakub. v2 was posted here: https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660191.html Gentle ping on this C++ patch: https://gcc.gn

Re: [PATCH] c++: ICE with -Wtautological-compare in template [PR116534]

2024-09-10 Thread Jason Merrill
On 8/29/24 12:23 PM, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk/14? -- >8 -- Pre r14-4793, we'd call warn_tautological_cmp -> operand_equal_p with operands wrapped in NON_DEPENDENT_EXPR, which works, since o_e_p bails for codes it doesn't know. But now we p

Re: [PATCH] c++: mutable temps in rodata [PR116369]

2024-09-10 Thread Jason Merrill
On 8/29/24 4:15 PM, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk/14/13? OK. -- >8 -- Here we wrongly mark the reference temporary for g TREE_READONLY, so it's put in .rodata and so we can't modify its subobject even when the subobject is marked mutable. Th

RE: [nvptx] Pass -m32/-m64 to host_compiler if it has multilib support

2024-09-10 Thread Thomas Schwinge
Hi Prathamesh! On 2024-09-10T13:22:10+, Prathamesh Kulkarni wrote: >> -Original Message- >> From: Thomas Schwinge >> Sent: Monday, September 9, 2024 8:50 PM >> > Could you please test the patch for gcn backend ? I've successfully tested x86_64 host with GCN as well as nvptx offload

Re: [RFC 0/4] Hard Register Constraints

2024-09-10 Thread Joseph Myers
A new feature for asm statements definitely needs documenting in the GCC manual. -- Joseph S. Myers josmy...@redhat.com

Re: [PATCH v2] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

2024-09-10 Thread Jeff Law
On 9/8/24 3:28 PM, Christoph Müllner wrote: On Sat, Sep 7, 2024 at 7:08 PM Jeff Law wrote: On 9/6/24 5:32 AM, Jin Ma wrote: In the process of DF to SI, we generally use "unsigned_fix" rather than "truncate" for conversion. Although this has no effect in general, unexpected ICE often occu

Re: [PATCH v2] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Martin Uecker
Am Dienstag, dem 10.09.2024 um 13:51 + schrieb Qing Zhao: >   #define alloc(P, FAM, COUNT) ({ \ >     typeof(P) __p; \ >     size_t __size = sizeof(*P) + sizeof(*P->FAM) * COUNT; \ >     __p = kmalloc(__size, GFP); \ >     typeof(_Generic(__builtin_counted_by_ref(__p->FAM), \ >   

RE: [nvptx] Pass -m32/-m64 to host_compiler if it has multilib support

2024-09-10 Thread Prathamesh Kulkarni
> -Original Message- > From: Thomas Schwinge > Sent: Tuesday, September 10, 2024 8:19 PM > To: Prathamesh Kulkarni ; Richard Biener > > Cc: Andrew Pinski ; gcc-patches@gcc.gnu.org; Jakub > Jelinek > Subject: RE: [nvptx] Pass -m32/-m64 to host_compiler if it has > multilib support > > Ex

[patch,avr] Tweak 32-bit comparisons.

2024-09-10 Thread Georg-Johann Lay
The order in which multi-byte EQ and NE comparisons are performing the byte comparisons does not matter, and there are situations where using SBIW on the high word can save an instruction. This is for trunk. Johann -- AVR: Tweak 32-bit EQ and NE comparisons. The order in which multi-byte EQ a

Re: [PATCH v2] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

2024-09-10 Thread Christoph Müllner
On Tue, Sep 10, 2024 at 5:25 PM Jeff Law wrote: > > > > On 9/8/24 3:28 PM, Christoph Müllner wrote: > > On Sat, Sep 7, 2024 at 7:08 PM Jeff Law wrote: > >> > >> > >> > >> On 9/6/24 5:32 AM, Jin Ma wrote: > >>> In the process of DF to SI, we generally use "unsigned_fix" rather than > >>> "truncate

Re: [PATCH] c++, coroutines: Fix handling of bool await_suspend() [PR115905].

2024-09-10 Thread Jason Merrill
On 9/7/24 6:45 AM, Iain Sandoe wrote: As noted in the PR the action of the existing implementation was to treat a false value from await_suspend () as equivalent to "do not suspend". Actually it needs to be the equivalent of "resume" - and we need to restart the dispatcher - since the await_susp

Re: [PATCH] c++, v3: Fix get_member_function_from_ptrfunc with -fsanitize=bounds [PR116449]

2024-09-10 Thread Jason Merrill
On 9/6/24 2:38 PM, Jakub Jelinek wrote: On Wed, Sep 04, 2024 at 10:31:48PM +0200, Franz Sirl wrote: Hmm, it just occured to me, how about adding !NONVIRTUAL here? When NONVIRTUAL is true, there is no conditional stmt at all, or? Yeah, that makes sense, the problem doesn't happen in that case.

[patch,avr] Reorder avr.cc so it requires less forward declarations.

2024-09-10 Thread Georg-Johann Lay
This patch reorders functions in avr.cc so that less forward declarations are needed. Johann -- AVR: avr.cc - Reorder functions to require less forward decls. gcc/ * config/avr/avr.cc (avr_init_machine_status): Move code to... (avr_option_override) : ...lambda. (avr_ins

[committed] libstdc++: Add missing exception specifications in tests

2024-09-10 Thread Jonathan Wakely
Tested x86_64-linux. Pushed to trunk. -- >8 -- Since r15-3532-g7cebc6384a0ad6 18_support/new_nothrow.cc fails in C++98 mode because G++ diagnoses missing exception specifications for the user-defined (de)allocation functions. Add throw(std::bad_alloc) and throw() for C++98 mode. Similarly, 26_n

[PATCH v2] gimple ssa: Don't use __builtin_popcount in switch exp transform

2024-09-10 Thread Filip Kastl
Hi, This is the second version of this patch. See the previous version here: https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662462.html In this verison I added a conversion to unsigned type to the bitmagic that I generate as Andrew suggested. Bootstrapped and regtested on x86_64-linu

[PATCH] RISC-V: Align vconfig for TARGER_SFB_ALU

2024-09-10 Thread Dusan Stojkovic
This patch addresses a missed opportunity to fuse vsetvl_infos. Instead of checking whether demands for merging configurations of vsetvl_info are all met, the demands are checked individually. The case in question occurs because of the conditional move instruction which sifive-7, sifive-p400 a

Re: [PATCH v2] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Qing Zhao
Thanks a lot for the tips. I updated the 2 testing cases per your suggestion, they work well. I will send the 3rd version of the patch soon. Qing > On Sep 10, 2024, at 11:42, Martin Uecker wrote: > > Am Dienstag, dem 10.09.2024 um 13:51 + schrieb Qing Zhao: >> #define alloc(P, FAM, COUN

[PATCH] c++: Don't crash when mangling member with anonymous union type [PR100632]

2024-09-10 Thread Simon Martin
We currently crash upon the following valid code (the case from the PR, invalid, can be made valid by simply adding a definition for f at line 2) === cut here === struct B { const int *p; }; template void f() {} struct Nested { union { int k; }; } nested; template void f(); === cut here === The p

Re: [PATCH v2] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Jakub Jelinek
On Tue, Sep 10, 2024 at 06:02:45PM +, Qing Zhao wrote: > > #define alloc(P, FAM, COUNT) ({ \ > > __auto_type __p = &(P); \ > > __auto_type __c = (COUNT); \ > > size_t __size = sizeof(*(*__p)) + sizeof(*(*__p)->FAM) * __c; \ Shouldn't that be size_t __size = offsetof(__typeof(*__p), FAM) +

[PATCH v3] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Qing Zhao
Hi, This is the 3rd version of the patch. compared to the 2nd version, the only change is the update in testing cases per Martin's suggestions. when the 2nd version is compared to the first version, the major changes are: 1. change the name of the builtin from __builtin_get_counted_by to __bui

[PATCH] c++: Implement for namespace statics CWG 2867 - Order of initialization for structured bindings [PR115769]

2024-09-10 Thread Jakub Jelinek
Hi! The following patch on top of the https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662507.html patch adds CWG 2867 support for namespace locals. Those vars are just pushed into {static,tls}_aggregates chain, then pruned from those lists, separated by priority and finally emitted into

Re: [PATCH v2] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Qing Zhao
> On Sep 10, 2024, at 14:09, Jakub Jelinek wrote: > > On Tue, Sep 10, 2024 at 06:02:45PM +, Qing Zhao wrote: >>> #define alloc(P, FAM, COUNT) ({ \ >>> __auto_type __p = &(P); \ >>> __auto_type __c = (COUNT); \ >>> size_t __size = sizeof(*(*__p)) + sizeof(*(*__p)->FAM) * __c; \ > > Shouldn

Re: [PATCH v2] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Jakub Jelinek
On Tue, Sep 10, 2024 at 06:31:23PM +, Qing Zhao wrote: > > > > On Sep 10, 2024, at 14:09, Jakub Jelinek wrote: > > > > On Tue, Sep 10, 2024 at 06:02:45PM +, Qing Zhao wrote: > >>> #define alloc(P, FAM, COUNT) ({ \ > >>> __auto_type __p = &(P); \ > >>> __auto_type __c = (COUNT); \ > >>>

Re: [PATCH v2] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Martin Uecker
Am Dienstag, dem 10.09.2024 um 20:36 +0200 schrieb Jakub Jelinek: > On Tue, Sep 10, 2024 at 06:31:23PM +, Qing Zhao wrote: > > > > > > > On Sep 10, 2024, at 14:09, Jakub Jelinek wrote: > > > > > > On Tue, Sep 10, 2024 at 06:02:45PM +, Qing Zhao wrote: > > > > > #define alloc(P, FAM, COU

Re: [PATCH v2] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Qing Zhao
> On Sep 10, 2024, at 14:48, Martin Uecker wrote: > > Am Dienstag, dem 10.09.2024 um 20:36 +0200 schrieb Jakub Jelinek: >> On Tue, Sep 10, 2024 at 06:31:23PM +, Qing Zhao wrote: >>> >>> On Sep 10, 2024, at 14:09, Jakub Jelinek wrote: On Tue, Sep 10, 2024 at 06:02:45PM +00

RE: [PATCH 1/2]middle-end: refactor type to be explicit in operand_equal_p [PR114932]

2024-09-10 Thread Tamar Christina
ping > -Original Message- > From: Tamar Christina > Sent: Tuesday, August 20, 2024 2:06 PM > To: gcc-patches@gcc.gnu.org > Cc: nd ; rguent...@suse.de; j...@ventanamicro.com > Subject: [PATCH 1/2]middle-end: refactor type to be explicit in > operand_equal_p > [PR114932] > > Hi All, > >

RE: [PATCH 2/2]middle-end: use two's complement equality when comparing IVs during candidate selection [PR114932]

2024-09-10 Thread Tamar Christina
ping > -Original Message- > From: Tamar Christina > Sent: Tuesday, August 20, 2024 2:06 PM > To: gcc-patches@gcc.gnu.org > Cc: nd ; rguent...@suse.de; j...@ventanamicro.com > Subject: [PATCH 2/2]middle-end: use two's complement equality when comparing > IVs during candidate selection [PR1

[committed] libstdc++: std::string move assignment should not use POCCA trait [PR116641]

2024-09-10 Thread Jonathan Wakely
Tested x86_64-linux. Pushed to trunk. Backports to follow. -- >8 -- The changes to implement LWG 2579 (r10-327-gdb33efde17932f) made std::string::assign use the propagate_on_container_copy_assignment (POCCA) trait, for consistency with operator=(const basic_string&). However, this also unintentio

[committed] libstdc++: Only use std::ios_base_library_init() for ELF [PR116159]

2024-09-10 Thread Jonathan Wakely
Tested x86_64-linux. Pushed to trunk. Backport to follow. -- >8 -- The undefined std::ios_base_library_init() symbol that is referenced by is only supposed to be used for targets where symbol versioning is supported. The mingw-w64 target defaults to --enable-symvers=gnu due to using GNU ld but

[PATCH v4] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Qing Zhao
Hi, This is the 4th version of the patch. Compared to the 3rd version, the only change is the size calculation in the testing case. The 3rd version compared to the 2nd version, the major change is: the update in testing cases per Martin's suggestions. when the 2nd version is compared to the firs

Re: [PATCH v4] Provide new GCC builtin __builtin_counted_by_ref [PR116016]

2024-09-10 Thread Jakub Jelinek
On Tue, Sep 10, 2024 at 09:28:04PM +, Qing Zhao wrote: > @@ -11741,6 +11770,54 @@ c_parser_postfix_expression (c_parser *parser) > set_c_expr_source_range (&expr, loc, close_paren_loc); > break; > } > + case RID_BUILTIN_COUNTED_BY_REF: > + { > + vec

[PATCH v1] RISC-V: Fix asm check for Vector SAT_* due to middle-end change

2024-09-10 Thread pan2 . li
From: Pan Li The middle-end change makes the effect on the layout of the assembly for vector SAT_*. This patch would like to fix it and make it robust. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust asm check and make it robust.

[PATCH] c++: decltype(auto) deduction of statement-expression [PR116418]

2024-09-10 Thread Patrick Palka
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/backports? -- >8 -- r8-7538 for PR84968 made strip_typedefs_expr diagnose seeing STATEMENT_LIST, which effectively makes us reject statement-expressions noexcept-specifiers (we already diagnose them in template argumen

RE: [PATCH v2 2/2] RISC-V: Fix ICE due to inconsistency of RVV intrinsic list in lto and cc1.

2024-09-10 Thread Li, Pan2
> * gcc.target/riscv/rvv/base/bug-11.c: New test. Seems you missed this file in patch v2? > +/* Helper for init_builtins in LTO. */ > +static void > +handle_pragma_vector_for_lto () > +{ > + struct pragma_intrinsic_flags backup_flags; > + > + riscv_pragma_intrinsic_flags_pollute (&backup_flags

[RFC PATCH] Enable vectorization for unknown tripcount in very cheap cost model but disable epilog vectorization.

2024-09-10 Thread liuhongt
GCC12 enables vectorization for O2 with very cheap cost model which is restricted to constant tripcount. The vectorization capacity is very limited w/ consideration of codesize impact. The patch extends the very cheap cost model a little bit to support variable tripcount. But still disable peel

Re: [PATCH] i386: Fix incorrect avx512f-mask-type.h include

2024-09-10 Thread Hongtao Liu
On Thu, Sep 5, 2024 at 10:05 AM Haochen Jiang wrote: > > Hi all, > > In avx512f-mask-type.h, we need SIZE being defined to get > MASK_TYPE defined correctly. Fix those testcases where > SIZE are not defined before the include for avv512f-mask-type.h. > > Note that for convert intrins in AVX10.2, t

[PATCH] aarch64: Emit ADD X, Y, Y instead of SHL X, Y, #1 for SVE instructions

2024-09-10 Thread Soumya AR
On Neoverse V2, SVE ADD instructions have a throughput of 4, while shift instructions like SHL have a throughput of 2. We can lean on that to emit code like: addz31.b, z31.b, z31.b instead of: lslz31.b, z31.b, #1 The implementation of this change for SVE vectors is similar to a prior pat

[PATCH v3 1/5] Genmatch: Add control flow graph match for case 0 and case 1

2024-09-10 Thread pan2 . li
From: Pan Li The gen_phi_on_cond can only support below control flow for cond from day 1. Aka: +--+ | def | | ... | +-+ | cond |-->| def | +--+ | ... | | +-+ | | v | +-+ | | PHI |<--+ +-+ U

[PATCH v3 3/5] Genmatch: Refine the gen_phi_on_cond by match_cond_with_binary_phi

2024-09-10 Thread pan2 . li
From: Pan Li This patch would like to leverage the match_cond_with_binary_phi to match the phi on cond, and get the true/false arg if matched. This helps a lot to simplify the implementation of gen_phi_on_cond. Before this patch: basic_block _b1 = gimple_bb (_a1); if (gimple_phi_num_args (_a1)

[PATCH v3 4/5] Match: Support form 3 for scalar signed integer .SAT_ADD

2024-09-10 Thread pan2 . li
From: Pan Li This patch would like to support the form 3 of the scalar signed integer .SAT_ADD. Aka below example: Form 3: #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ T __attribute__((noinline))\ sat_s_add_##T##_fmt_3 (T x, T y)

[PATCH v3 2/5] Match: Add interface match_cond_with_binary_phi for true/false arg

2024-09-10 Thread pan2 . li
From: Pan Li When matching the cond with 2 args phi node, we need to figure out which arg of phi node comes from the true edge of cond block, as well as the false edge. This patch would like to add interface to perform the action and return the true and false arg in TREE type. There will be som

[PATCH v3 5/5] RISC-V: Fix vector SAT_ADD dump check due to middle-end change

2024-09-10 Thread pan2 . li
From: Pan Li This patch would like fix the dump check times of vector SAT_ADD. The middle-end change makes the match times from 2 to 4 times. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/b