[PATCH V4 4/5] RISC-V: Quick and simple fixes to testcases that break due to reordering

The following test cases are easily fixed with small updates to the expected assembly order. Additionally make calling-convention testcases more robust PR target/113249 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: update * gcc.target

Re: [PATCH v2 1/4] c++: Implement __add_pointer built-in trait

On Wed, Feb 14, 2024 at 12:19 PM Patrick Palka wrote: > > On Wed, 14 Feb 2024, Ken Matsui wrote: > > > This patch implements built-in trait for std::add_pointer. > > > > gcc/cp/ChangeLog: > > > > * cp-trait.def: Define __add_pointer. > > * semantics.cc (finish_trait_type): Handle CPTK_

[PATCH v3 1/4] c++: Implement __add_pointer built-in trait

This patch implements built-in trait for std::add_pointer. gcc/cp/ChangeLog: * cp-trait.def: Define __add_pointer. * semantics.cc (finish_trait_type): Handle CPTK_ADD_POINTER. gcc/testsuite/ChangeLog: * g++.dg/ext/has-builtin-1.C: Test existence of __add_pointer.

PING: [PATCH v3 0/8] Optimize more type traits

IIRC, all libstdc++ patches were already reviewed. It would be great if gcc patches were reviewed as well. Thank you for your time. Sincerely, Ken Matsui On Fri, Jan 5, 2024 at 9:08 PM Ken Matsui wrote: > > Changes in v3: > > - Rebased on top of master. > - Fixed __is_pointer in cpp_type_trait

Re: [PATCH] Skip gnat.dg/div_zero.adb on RISC-V

LGTM, thanks :) On Wed, Feb 14, 2024 at 10:11 PM Andreas Schwab wrote: > > Like AArch64 and POWER, RISC-V does not support trap on zero divide. > > gcc/testsuite/ > * gnat.dg/div_zero.adb: Skip on RISC-V. > --- > gcc/testsuite/gnat.dg/div_zero.adb | 2 +- > 1 file changed, 1 insertion(+)

[PATCH] icf: Reset SSA_NAME_{PTR,RANGE}_INFO in successfully merged functions [PR113907]

Hi! AFAIK we have no code in LTO streaming to stream out or in SSA_NAME_{RANGE,PTR}_INFO, so LTO effectively throws it all away and let vrp1 and alias analysis after IPA recompute that. There is just one spot, for IPA VRP and IPA bit CCP we save/restore ranges and set SSA_NAME_{PTR,RANGE}_INFO e.

[PATCH] lower-bitint: Ensure we don't get coalescing ICEs for (ab) SSA_NAMEs used in mul/div/mod [PR113567]

Hi! The build_bitint_stmt_ssa_conflicts hook has a special case for multiplication, division and modulo, where to ensure there is no overlap between lhs and rhs1/rhs2 arrays we make the lhs conflict with the operands. On the following testcase, we have # a_1(ab) = PHI lab: a_3(ab) = a_1(ab) %

Re: GCN RDNA2+ vs. GCC vectorizer "Reduce using vector shifts"

On Wed, 14 Feb 2024, Andrew Stubbs wrote: > On 14/02/2024 13:43, Richard Biener wrote: > > On Wed, 14 Feb 2024, Andrew Stubbs wrote: > > > >> On 14/02/2024 13:27, Richard Biener wrote: > >>> On Wed, 14 Feb 2024, Andrew Stubbs wrote: > >>> > On 13/02/2024 08:26, Richard Biener wrote: > >

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