[PATCH] ggc-common: Fix save PCH assertion

Hi! We are getting a gnuradio PCH ICE /usr/include/pybind11/stl.h:447:1: internal compiler error: in gt_pch_save, at ggc-common.cc:693 0x1304e7d gt_pch_save(_IO_FILE*) ../../gcc/ggc-common.cc:693 0x12a45fb c_common_write_pch() ../../gcc/c-family/c-pch.cc:175 0x18ad711 c_parse_fina

[PATCH] wide-int: Fix up wi::bswap_large [PR113722]

Hi! Since bswap has been converted from a method to a function we miscompile the following testcase. The problem is the assumption that the passed in len argument (number of limbs in the xval array) is the upper bound for the bswap result, which is true only if precision is <= 64. If precision i

[r14-8768 Regression] FAIL: libgomp.fortran/non-rectangular-loop-1.f90 -O1 execution test on Linux/x86_64

On Linux/x86_64, 85094e2aa6dba7908f053046f02dd443e8f65d72 is the first bad commit commit 85094e2aa6dba7908f053046f02dd443e8f65d72 Author: Tamar Christina Date: Fri Feb 2 23:52:27 2024 + middle-end: check memory accesses in the destination block [PR113588]. caused FAIL: libgomp.fortra

[PATCH] LoongArch: Fix wrong LSX FP vector negation

We expanded (neg x) to (minus const0 x) for LSX FP vectors, this is wrong because -0.0 is not 0 - 0.0. This causes some Python tests to fail when Python is built with LSX enabled. Use the vbitrevi.{d/w} instructions to simply reverse the sign bit instead. We are already doing this for LASX and n

Pushed: [PATCH] LoongArch: Fix an ODR violation

On Fri, 2024-02-02 at 10:42 +0800, chenglulu wrote: > LGTM! > > Thanks! Pushed r14-8773. > 在 2024/2/2 上午5:54, Xi Ruoyao 写道: > > When bootstrapping GCC 14 --with-build-config=bootstrap-lto, an ODR > > violation is detected: > > > > ../../gcc/config/loongarch/loongarch-opts.cc:57: warning: >

[PATCH 1/4] df: Add -ftrack-subreg-liveness option

Add new flag -ftrack-subreg-liveness to enable track-subreg-liveness. This flag is enabled at -O3/fast. gcc/ChangeLog: * common.opt: add -ftrack-subreg-liveness option. * opts.cc: auto aneble -ftrack-subreg-liveness in -O3/fast --- gcc/common.opt | 4 gcc/opts.cc| 1 +

[PATCH 0/4] Add DF_LIVE_SUBREG data and apply to IRA and LRA

Hi, These patches are used to add a new data flow DF_LIVE_SUBREG, which will track subreg liveness and then apply it to IRA and LRA passes (enabled via -O3 or -ftrack-subreg-liveness). These patches are for GCC 15. These patches are separated from the subreg-coalesce patches submitted a few month

[PATCH 2/4] df: Add DF_LIVE_SUBREG problem

This patch add a new DF problem, named DF_LIVE_SUBREG. This problem is extended from the DF_LR problem and support track the subreg liveness of multireg pseudo if these pseudo satisfy the following conditions: 1. the mode size greater than it's REGMODE_NATURAL_SIZE. 2. the reg is used in insns

[PATCH 4/4] lra: Apply DF_LIVE_SUBREG data

This patch apply the DF_LIVE_SUBREG to LRA pass. More changes were made to the LRA than the IRA since the LRA will modify the DF data directly. The main big changes are centered on the lra-lives.cc file. gcc/ChangeLog: * lra-coalesce.cc (update_live_info): Extend to DF_LIVE_SUBREG.

[PATCH 3/4] ira: Apply DF_LIVE_SUBREG data

This patch simple replace df_get_live_in to df_get_subreg_live_in and replace df_get_live_out to df_get_subreg_live_out. gcc/ChangeLog: * ira-build.cc (create_bb_allocnos): Switch to DF_LIVE_SUBREG df data. (create_loop_allocnos): Ditto. * ira-color.cc (ira_loop_edge_freq)

[committed] d: Merge dmd. druntime e770945277, phobos 6d6e0b9b9

Hi, This patch merges the D front-end and runtime library with upstream dmd e770945277, and the standard runtime library with phobos 6d6e0b9b9. Synchronizing with the upstream release candidate as of 2024-01-27. D front-end changes: - Import latest fixes from dmd v2.107.0-beta.1. - Hex

Re: [PATCH v2] RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems.

On Jan 30 2024, Christoph Müllner wrote: > retested Nope. ../../gcc/config/riscv/thead.cc:1144:22: error: invalid suffix on literal; C++11 requires a space between literal and string macro [-Werror=literal-suffix] 1144 | fprintf (file, "(%s),"HOST_WIDE_INT_PRINT_DEC",%u", reg_names[REGN

Re: [PATCH] ggc-common: Fix save PCH assertion

> Am 03.02.2024 um 09:36 schrieb Jakub Jelinek : > > Hi! > > We are getting a gnuradio PCH ICE > /usr/include/pybind11/stl.h:447:1: internal compiler error: in gt_pch_save, > at ggc-common.cc:693 > 0x1304e7d gt_pch_save(_IO_FILE*) >../../gcc/ggc-common.cc:693 > 0x12a45fb c_common_write_p

Re: [PATCH] wide-int: Fix up wi::bswap_large [PR113722]

> Am 03.02.2024 um 09:46 schrieb Jakub Jelinek : > > Hi! > > Since bswap has been converted from a method to a function we miscompile > the following testcase. The problem is the assumption that the passed in > len argument (number of limbs in the xval array) is the upper bound for the > bsw

[committed] MAINTAINERS: Update my e-mail address

* MAINTAINERS: Update my e-mail address. --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index b47e0465852..3720344308e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -124,7 +124,7 @@ sparc port David S. Miller

[PATCH 1/2] xtensa: Recover constant synthesis for HImode after LRA transition

After LRA transition, HImode constants that don't fit into signed 12 bits are no longer subject to constant synthesis: /* example */ void test(void) { short foo = 32767; __asm__ ("" :: "r"(foo)); } ;; before .literal_position .literal .LC0, 32767 te

[PATCH 2/2] xtensa: Fix missing mode warning in "*eqne_zero_masked_bits"

gcc/ChangeLog: * config/xtensa/xtensa.md (*eqne_zero_masked_bits): Add missing ":SI" to the match_operator. --- gcc/config/xtensa/xtensa.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 5242eb3c0

Re: [patch, libgfortran] PR111022 ES0.0E0 format gave ES0.dE0 output with d too high.

Jerry, Steve, Am 03.02.24 um 04:24 schrieb Steve Kargl: Jerry, The patch looks good to me, but please give Harald a chance to comment. I just tested it a little, and it looked good. We even get a runtime error on E0.0 now as required. :-) Thanks for the patch! Harald

[PATCH] libitm: small update for C++20

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- C++20 DR 2237 disallows simple-template-id in cdtors, so you can't write template struct S { S(); // should be S(); }; This hasn't been a problem until now but I'm adding a warning about it to -Wc++20-compat

[PATCH] c++: DR2237, cdtor and template-id tweaks [PR107126]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? I'm not certain OPT_Wc__20_extensions is the best thing for something from [diff.cpp17]; would you prefer something else? -- >8 -- Since my r11-532 changes to implement DR2237, for this test: template struct S { S(); }; in C

Re: [PATCH 1/2] xtensa: Recover constant synthesis for HImode after LRA transition

Hi Suwa-san, On Sat, Feb 3, 2024 at 6:20 AM Takayuki 'January June' Suwa wrote: > After LRA transition, HImode constants that don't fit into signed 12 bits > are no longer subject to constant synthesis: with this change I get multiple ICEs during libgomp, libgfortran and libstdc++ builds, e.g.:

[committed] libatomic: Provide FPU exception defines for hppa

Tested on hppa64-hp-hpux11.11. Committed to trunk. Dave --- libatomic: Provide FPU exception defines for hppa The exception defines in do not match the exception bits in the FPU status register on hppa-linux and hppa64-hpux11.11. On linux, they match the trap enable bits. On 64-bit hpux, the

[PATCH 1/2 v2] libdecnumber: fixed multiple potential access-out-of bounds errors by moving range conditions before reads.

Multiple `for` loops across `libdecnumber` contain boolean expressions where memory is accessed prior to checking if the pointer is still within a valid range, which can lead to out-of-bounds reads. This patch moves the range conditions to appear before the memory accesses in each conjunction s

[committed] Fix xfail for 32-bit hppa*-*-* in gcc.dg/pr84877.c

Tested on hppa-unknown-linux-gnu. Committed to trunk. Dave --- Fix xfail for 32-bit hppa*-*-* in gcc.dg/pr84877.c 2024-02-03 John David Anglin gcc/testsuite/ChangeLog: * gcc.dg/pr84877.c: Adjust xfail parentheses. diff --git a/gcc/testsuite/gcc.dg/pr84877.c b/gcc/testsuite/gcc.dg/

Re: [PATCH]middle-end: check memory accesses in the destination block [PR113588].

Toon Moene writes: > On 2/1/24 22:33, Tamar Christina wrote: > >> Bootstrapped Regtested on aarch64-none-linux-gnu and x86_64-pc-linux-gnu no >> issues. >> Also checked both with --enable-lto --with-build-config='bootstrap-O3 >> bootstrap-lto' --enable-multilib >> and --enable-lto --with-buil

[committed] d: Merge dmd, druntime a6f1083699, phobos 31dedd7da

Hi, This patch merges the D front-end and runtime library with upstream dmd a6f1083699, and the standard library with phobos 31dedd7da. D front-end changes: - Import dmd v2.107.0. - Character postfixes can now also be used for integers of size two or four. D run-time c

Re: [PATCH] LoongArch: libsanitizer: Enable build lsan and tsan for loongarch64.

在 2024/2/2 下午6:01, Jakub Jelinek 写道: On Tue, Jan 30, 2024 at 10:09:51AM +0800, Lulu Cheng wrote: From: chenguoqi libsanitizer/ChangeLog: * configure.tgt: Enable tsan and lsan for loongarch64. * tsan/Makefile.am: Add tsan_rtl_loongarch64.S to EXTRA_libtsan_la_SOURCES. This

[PATCH v2] LoongArch: libsanitizer: Enable Lsan and Tsan for loongarch64.

From: chenguoqi libsanitizer/ChangeLog: * configure.tgt: Enable tsan and lsan for loongarch64. * tsan/Makefile.am (EXTRA_libtsan_la_SOURCES): Add tsan_rtl_loongarch64.S. * tsan/Makefile.in: Regenerate. --- libsanitizer/configure.tgt| 5 + libsanitizer/tsa

Re: Re: [PATCH] RISC-V: Allow LICM hoist POLY_INT configuration code sequence

Hi, kito and Robin and Jeff. I didn't commit this patch yet since I found there is an ICE caused by this patch: during RTL pass: loop2_unroll dump file: bug.c.286r.loop2_unroll bug.c: In function 'crashIt': bug.c:23:1: internal compiler error: in decompose, at wide-int.h:1049 23 | } |

Re: [PATCH] LoongArch: Avoid out-of-bounds access in loongarch_symbol_insns

在 2024/2/2 下午5:55, Xi Ruoyao 写道: We call loongarch_symbol_insns with mode = MAX_MACHINE_MODE sometimes. But in loongarch_symbol_insns: if (LSX_SUPPORTED_MODE_P (mode) || LASX_SUPPORTED_MODE_P (mode)) return 0; And LSX_SUPPORTED_MODE_P is defined as: #define LSX_SUPPORTED_MOD

Re: [PATCH] LoongArch: Fix wrong LSX FP vector negation

在 2024/2/3 下午4:58, Xi Ruoyao 写道: We expanded (neg x) to (minus const0 x) for LSX FP vectors, this is wrong because -0.0 is not 0 - 0.0. This causes some Python tests to fail when Python is built with LSX enabled. Use the vbitrevi.{d/w} instructions to simply reverse the sign bit instead. We

Re: Repost [PATCH 4/6] PowerPC: Make MMA insns support DMR registers.

Hi Mike, on 2024/1/6 07:39, Michael Meissner wrote: > This patch changes the MMA instructions to use either FPR registers > (-mcpu=power10) or DMRs (-mcpu=future). In this patch, the existing MMA > instruction names are used. > > A macro (__PPC_DMR__) is defined if the MMA instructions use the D

[r14-8768 Regression] FAIL: libgomp.fortran/non-rectangular-loop-1.f90 -O1 execution test on Linux/x86_64

On Linux/x86_64, 85094e2aa6dba7908f053046f02dd443e8f65d72 is the first bad commit commit 85094e2aa6dba7908f053046f02dd443e8f65d72 Author: Tamar Christina Date: Fri Feb 2 23:52:27 2024 + middle-end: check memory accesses in the destination block [PR113588]. caused FAIL: libgomp.fortra

Re: [PATCH v4 5/5] Add documentation for musttail attribute

On 2/2/24 02:09, Andi Kleen wrote: gcc/ChangeLog: * doc/extend.texi: Document [[musttail]] --- gcc/doc/extend.texi | 16 1 file changed, 16 insertions(+) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 142e41ab8fbf..866f6c4a9fed 100644 --- a/gcc/doc/exte

Re: Repost [PATCH 5/6] PowerPC: Switch to dense math names for all MMA operations.

Hi Mike, on 2024/1/6 07:40, Michael Meissner wrote: > This patch changes the assembler instruction names for MMA instructions from > the original name used in power10 to the new name when used with the dense > math > system. I.e. xvf64gerpp becomes dmxvf64gerpp. The assembler will emit the > sa