[PATCH v2] rs6000: Fix ASAN linker errors for Power ELF V1 ABI [PR113284]

v1: https://inbox.sourceware.org/gcc-patches/20240109105253.332676-1-...@linux.ibm.com/ v1 -> v2: Move the .LASANPC label to the .text section (Jakub). Jakub okay-ed this version in the GCC Bugzilla. Bootstrap and regtest running on ppc64le-redhat-linux and powerpc64-linux-gnu. Ok for

Re: [PATCH v8 1/4] c++: P0847R7 (deducing this) - prerequisite changes. [PR102609]

On Tuesday, January 9th, 2024 at 3:52 PM, Jason Merrill wrote: > > > On 1/9/24 17:34, waffl3x wrote: > > > On Tuesday, January 9th, 2024 at 2:56 PM, Jason Merrill ja...@redhat.com > > wrote: > > > > > > Is the type of an implicit object parameter specified elsewhere? I have > > look

Re: [PATCH 0/5] RISC-V: Relax the -march string for accept any order

Oops, I should leave more context here: Actually we discussed that years ago, and most people agree with that, but I guess we are just missing that, and also the ISA string isn't so terribly long yet at that moment, however...the number of extensions are growth so fast in last year, so I think it'

[Committed] RISC-V: Robostify dynamic lmul test

While working on refining the cost model, I notice this test will generate unexpected scalar xor instructions if we don't tune cost model carefully. Add more assembler to avoid future regression. Committed. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: A

[PATCH V2 2/4][RFC] RISC-V: Add vector related reservations

This patch copies the vector reservations from generic-ooo.md and inserts them into generic.md and sifive.md. Creates new vector crypto related insn reservations. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_crypto_aes): create reservation (generic_ooo_crypto_sha): d

[PATCH V2 0/4][RFC] RISC-V: Associate typed insns to dfa reservation

This series is a prototype for adding all typed instructions to a dfa scheduling pipeline. This is what I currently have for cleaning up the cost models. Adding the vector insns to the dfa pipelines changes the expected output of a lot of test cases as expected. Should I update the expected outp

[PATCH V2 4/4][RFC] RISC-V: Enable assert for insn_has_dfa_reservation

Enables assert that every typed instruction is associated with a dfa reservation gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert Signed-off-by: Edwin Lu --- V2: - No changes --- gcc/config/riscv/riscv.cc | 6 -- 1 file changed, 4 insertions(+), 2

[PATCH V2 1/4][RFC] RISC-V: Add non-vector types to dfa pipelines

This patch adds non-vector related insn reservations and updates/creates new insn reservations so all non-vector typed instructions have a reservation. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation (generic_ooo_branch): ditto * config/

[PATCH V2 3/4][RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249

Use default cost model scheduling on these test cases. All these tests introduce scan dump failures with -mtune generic-ooo. Since the vector cost models are the same across all three tunes, some of the tests in PR113249 will be fixed with this patch series. Unfortunately, 40 unique testsuite fail

[PATCH, rs6000] Refactor expand_compare_loop and split it to two functions

Hi, This patch refactors function expand_compare_loop and split it to two functions. One is for fixed length and another is for variable length. These two functions share some low level common help functions. Besides above changes, the patch also does: 1. Don't generate load and compare loop w

Re: [PATCH v3] LoongArch: testsuite:Added support for vector object detection.

在 2024/1/10 上午3:51, Andreas Schwab 写道: gcc: gcc.dg/vect/vect-outer-4a-big-array.c -flto -ffat-lto-objects: error executing dg-final: unknown effective target keyword `loongarch*-*-*' gcc: gcc.dg/vect/vect-outer-4a-big-array.c: error executing dg-final: unknown effective target keyword `loonga

[PATCH] RISC-V: Minor tweak dynamic cost model

While working on cost model, I notice one case that dynamic lmul cost doesn't work well. Before this patch: foo: lui a4,%hi(.LANCHOR0) li a0,1953 li a1,63 addia4,a4,%lo(.LANCHOR0) li a3,64 vsetvli a2,zero,e32,mf2,ta,ma

Re: [PATCH 0/5] RISC-V: Relax the -march string for accept any order

On Tue, Jan 9, 2024 at 4:59 PM Kito Cheng wrote: > > Oops, I should leave more context here: > > Actually we discussed that years ago, and most people agree with that, but I > guess we are just missing that, and also the ISA string isn't so terribly > long yet at that moment, however...the numbe

[PATCH] Update documents for fcf-protection=

After r14-2692-g1c6231c05bdcca, the option is defined as EnumSet and -fcf-protection=branch won't unset any others bits since they're in different groups. So to override -fcf-protection, an explicit -fcf-protection=none needs to be added and then with -fcf-protection=XXX Bootstrapped and regtested

[PATCH] config: delete unused CYG_AC_PATH_LIBERTY macro

Nothing uses this, so delete it to avoid confusion. config/ChangeLog: * acinclude.m4 (CYG_AC_PATH_LIBERTY): Delete. --- config/acinclude.m4 | 22 -- 1 file changed, 22 deletions(-) diff --git a/config/acinclude.m4 b/config/acinclude.m4 index 0abccafa0353..f18f0d6e8c7

[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH] Add -mevex512 into invoke.texi

Hi Richard, It seems that I send out a not updated patch. This patch should what I want to send. Thx, Haochen gcc/ChangeLog: * doc/invoke.texi: Add -mevex512. --- gcc/doc/invoke.texi | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc

Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

Thanks for your patience. LGTM from myside. I think it's pretty clean now. I can image in the future when some day the theadvector is no longer used, we can remove it very easily. And also, the theadvector won't affect our RVV1.0 maintain since it's isolated cleanly. But I'd like to wait fo

Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

Hi Juzhe, Thank you for so many useful comments for this patch! There are some more patches to support xtheadvector special instrinsics as well as handle register overlap issue and rewrite assembly output. https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641774.html https://gcc.gnu.org/pip

Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

Hi Kito, Thank you for your support again. I believe we can get all our xtheadvector patches ready before the end of Feb. May I please ping the arch patch again? https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641801.html This is the patch that all the following patches rely on. Joshua

Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp" - [(set (match_operand: 0 "register_operand""=vr, vr, vr, vr") + [(set (match_operand: 0 "register_operand""=vr, vr, vr, vr, &vr, &vr, &vr, &vr")

[PATCH V2] RISC-V: Minor tweak dynamic cost model

v2 update: Robostify tests. While working on cost model, I notice one case that dynamic lmul cost doesn't work well. Before this patch: foo: lui a4,%hi(.LANCHOR0) li a0,1953 li a1,63 addia4,a4,%lo(.LANCHOR0) li a3,64 vsetvli

Re:[pushed] [PATCH v2 0/4] Adjust option handling code

Pushed to r14-7085...r14-7088 在 2024/1/8 上午9:14, Yang Yujie 写道: This patchset performs some code cleanup, and is bootstrapped and regtested on loongarch64-linux-gnu. Changes from v1 -> v2: * Replaced all TARGET_ macros from .opt. * Fixed definition of ISA_HAS_LAMCAS. Yang Yujie (4): LoongAr

RE: [PATCH v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option

Thanks Jeff and Richard for confirmation and comments. It looks like firstly we should address the issue of the original commits in v4 and then back to if there is something we need to deal with option no-signed-zero for the riscv. Pan -Original Message- From: Jeff Law Sent: Wednesda

[PATCH] RISC-V: Refine unsigned avg_floor/avg_ceil

This patch is inspired by LLVM patches: https://github.com/llvm/llvm-project/pull/76550 https://github.com/llvm/llvm-project/pull/77473 Use vaaddu for AVG vectorization. Before this patch: vsetivlizero,8,e8,mf2,ta,ma vle8.v v3,0(a1) vle8.v v2,0(a2) vwadd

Re: [PATCH] strub: Only unbias stack point for SPARC_STACK_BOUNDARY_HACK [PR113100]

on 2024/1/8 19:44, Richard Biener wrote: > On Mon, Jan 8, 2024 at 3:35 AM Kewen.Lin wrote: >> >> Hi, >> >> As PR113100 shows, the unbiasing introduced by r14-6737 can >> cause the scrubbing to overrun and screw some critical data >> on stack like saved toc base consequently cause segfault on >> Po

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we use "group_overlap" and "enabled" attribu

Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

+ (and (eq_attr "group_overlap" "th") + (match_test "TARGET_XTHEADVECTOR")) + (const_string "no") + + (and (eq_attr "group_overlap" "rvv") + (match_test "TARGET_VECTOR && !TARGET_XTHEADVECTOR")) + (const_string "no") + ] Change it into: + (and (eq_attr "group_overlap" "thv_disabled")

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we use "group_overlap" and "enabled" attribu

Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

LGTM from myside. Give another a few more days that some one want to chime in. juzhe.zh...@rivai.ai From: Jun Sha (Joshua) Date: 2024-01-10 14:51 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmi

Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html This patch is ok from my side. juzhe.zh...@rivai.ai 发件人： joshua 发送时间： 2024-01-10 10:57 收件人： juzhe.zh...@rivai.ai; gcc-patches 抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; jinma; cooper.qu

Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

Why do you add theadvector shapes ? I think you can reuse the current existing shapes. +thead-vector-builtins.o: \ + $(srcdir)/config/riscv/thead-vector-builtins.cc \ + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \ + $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \

[PATCH][wwwdoc] gcc-14: Add arm cortex-m52 cpu support

Hi Gerald, The Arm Cortex-M52 CPU has been added to the upstream: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642230.html I would like to document this on the gcc-14 changes.html page. Attached is the patch for gcc-wwwdocs repository. Is it OK? Regards, jasonwucjFrom 2513e83f0749045

Re: [PATCH] RISC-V: Refine unsigned avg_floor/avg_ceil

LGTM! On Wed, Jan 10, 2024 at 1:05 PM Juzhe-Zhong wrote: > > This patch is inspired by LLVM patches: > https://github.com/llvm/llvm-project/pull/76550 > https://github.com/llvm/llvm-project/pull/77473 > > Use vaaddu for AVG vectorization. > > Before this patch: > > vsetivlizero,8,

Re：Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

These xttheadvector speical intrinsics are different from rvv1.0 in determining function name from base name. We cannot directly reuse the existing shapes. In order not to invade existing shapes, we add new shapes for new functions. Also, we create new thead-vector-builtins.cc for xtheadvector fun

Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

Why do you need to invade existing shapes ? juzhe.zh...@rivai.ai 发件人： joshua 发送时间： 2024-01-10 15:16 收件人： juzhe.zh...@rivai.ai; gcc-patches 抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; jinma; cooper.qu 主题： Re：Re：[PATCH v5] RISC-V: Handle differences betwee

RE: [PATCH] RISC-V: Refine unsigned avg_floor/avg_ceil

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Wednesday, January 10, 2024 3:12 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jeffreya...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH] RISC-V: Refine unsigned avg_floor/avg_ceil LGT

[PATCH v2] LoongArch: testsuite:Added support for loongarch.

The function of this test is to check that the compiler supports vectorization using SLP and vec_{load/store/*}_lanes. However, vec_{load/store/*}_lanes are not supported on LoongArch, such as the corresponding "st4/ld4" directives on aarch64. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-21

[PATCH v1] LoongArch: testsuite:Fixed a bug that added a target check error.

After the code is committed in r14-6948, GCC regression testing on some architectures will produce the following error: "error executing dg-final: unknown effective target keyword `loongarch*-*-*'" gcc/testsuite/ChangeLog: * lib/target-supports.exp: Removed an issue with "target keyword"

回复：Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

For example +/* th_loadstore_width_def class. */ +struct th_loadstore_width_def : public build_base +{ + void build (function_builder &b, + const function_group_info &group) const override + { +/* Report an error if there is no xtheadvector. */ +if (!TARGET_XTHEADVECTOR) +

Re：Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

I'm confused why I cannot add new shapes. I think adding new shapes is the basic part in implementation for new intrinsics. -- 发件人：juzhe.zh...@rivai.ai 发送时间：2024年1月10日(星期三) 15:17 收件人："cooper.joshua"; "gcc-patches" 抄　送：Jim Wils

[PATCH] i386: Add AVX10.1 related macros

Hi all, This patch aims to add AVX10.1 related macros for libgomp's request. The request comes following: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642025.html Ok for trunk? Thx, Haochen gcc/ChangeLog: PR target/113288 * config/i386/i386-c.cc (ix86_target_macros_i

[PATCH] Document refactoring of the option -fcf-protection=x.

To override -fcf-protection, -fcf-protection=none needs to be added and then with -fcf-protection=xxx. --- htdocs/gcc-14/changes.html | 6 ++ 1 file changed, 6 insertions(+) diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index e3a68998..72b0d291 100644 --- a/htdocs/gcc-1

[PATCH] c++: side effect in nullptr_t conversion fix

According C++ standard [conv.lval]p3.1: If T is cv std::nullptr_t, the result is a null pointer constant. [Note: Since the conversion does not access the object to which the glvalue refers, there is no side effect even if T is volatile-qualified, and the glvalue can refer to an inactive member of a

Re: [PATCH] c++: side effect in nullptr_t conversion fix

On Tue, Jan 09, 2024 at 11:20:02AM +0300, Dmitry Drozodv wrote: > diff --git a/gcc/cp/cvt.cc b/gcc/cp/cvt.cc > index cbed847b343..14462356a0e 100644 > --- a/gcc/cp/cvt.cc > +++ b/gcc/cp/cvt.cc > @@ -218,8 +218,9 @@ cp_convert_to_pointer (tree type, tree expr, bool > dofold, > ? bu

Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477]

On Mon, 8 Jan 2024, Jeff Law wrote: > > > On 1/8/24 09:57, Andrew Pinski wrote: > > On Mon, Jan 8, 2024 at 6:44?AM Uros Bizjak wrote: > >> > >> Instead of converting XOR or PLUS of two values, ANDed with two constants > >> that > >> have no bits in common, to IOR expression, convert IOR or XOR

RE: [ARC PATCH] Table-driven ashlsi implementation for better code/rtx_costs.

HI Roger, It looks good. Thank you for your contribution, Claudiu -Original Message- From: Roger Sayle Sent: Sunday, December 24, 2023 1:38 AM To: gcc-patches@gcc.gnu.org Cc: 'Claudiu Zissulescu' ; 'Jeff Law' Subject: [ARC PATCH] Table-driven ashlsi implementation for better code/rt

[PATCH] vect: Ensure both NITERSM1 and NITERS are INTEGER_CSTs or neither of them [PR113210]

Hi! On the following testcase e.g. on riscv64 or aarch64 (latter with -O3 -march=armv8-a+sve ) we ICE, because while NITERS is INTEGER_CST, NITERSM1 is a complex expression like (short unsigned int) (a.0_1 + 255) + 1 > 256 ? ~(short unsigned int) (a.0_1 + 255) : 0 where a.0_1 is unsigned char. T

Re: [PATCH] sparc: Char arrays are 64-bit aligned on SPARC

> Hello Eric! Thank you for reviewing the patches! You're welcome. > No, this warning is not from GCC, it is from binutils ld. I forgot to > mention that in the message. I get a similar warning from older versions > of ld, so I do not think it is a new warning. It is also there with GCC 10. I se

Re: [PATCH] testsuite: Skip ifcvt-4.c for SPARC V8

> Conditional moves are not available in SPARC V8. > > gcc/testsuite/ChangeLog: > > * gcc.dg/ifcvt-4.c: Skip for SPARC V8 OK. -- Eric Botcazou

[PATCH] c-family: copy attribute diagnostic fixes [PR113262]

Hi! The copy attributes is allowed on decls as well as types and even has checks whether decl (set to *node) is DECL_P or TYPE_P, but for diagnostics unconditionally uses DECL_SOURCE_LOCATION (decl), which obviously only works if it applies to a decl. The following patch fixes that, bootstrapped/

Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477]

On Mon, 8 Jan 2024, Uros Bizjak wrote: > On Mon, Jan 8, 2024 at 5:57?PM Andrew Pinski wrote: > > > > On Mon, Jan 8, 2024 at 6:44?AM Uros Bizjak wrote: > > > > > > Instead of converting XOR or PLUS of two values, ANDed with two constants > > > that > > > have no bits in common, to IOR expression

[committed] libgomp: Use absolute pathname to testsuite/flock [PR113192]

Hi! When flock program doesn't exist, libgomp configure attempts to offer a fallback version using a perl script, but we weren't using absolute filename to that, so it apparently failed to work correctly. The following patch arranges for it to get the absolute filename. Tested by John David in t

Re: [PATCH] vect: Ensure both NITERSM1 and NITERS are INTEGER_CSTs or neither of them [PR113210]

On Tue, 9 Jan 2024, Jakub Jelinek wrote: > Hi! > > On the following testcase e.g. on riscv64 or aarch64 (latter with > -O3 -march=armv8-a+sve ) we ICE, because while NITERS is INTEGER_CST, > NITERSM1 is a complex expression like > (short unsigned int) (a.0_1 + 255) + 1 > 256 ? ~(short unsigned in

Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477]

On Tue, Jan 9, 2024 at 9:58 AM Richard Biener wrote: > > On Mon, 8 Jan 2024, Uros Bizjak wrote: > > > On Mon, Jan 8, 2024 at 5:57?PM Andrew Pinski wrote: > > > > > > On Mon, Jan 8, 2024 at 6:44?AM Uros Bizjak wrote: > > > > > > > > Instead of converting XOR or PLUS of two values, ANDed with two

Fix PR rtl-optimization/113140

This is a small regression present on the mainline and 13 branch, although the underlying problem has probably been there for ages, in the form of a segfault during the delay slot scheduling pass, for a function that falls through to exit without any RTL instruction generated for the end of func

Fix PR rtl-optimization/113140

This is a small regression present on the mainline and 13 branch, although the underlying problem has probably been there for ages, in the form of a segfault during the delay slot scheduling pass, for a function that falls through to exit without any RTL instruction generated for the end of func

[Ada] Fix PR ada/113195

This is a small regression present on the mainline and 13 branch, in the form of an internal error in gigi on anonymous access type equality. We now need to also accept them too for anonymous access types that point to compatible object subtypes in the language sense. Tested on SPARC64/Linux,

Re:[PATCH] Support libcall __float{,un}sibf by SF when it is not supported for _bf16

ping

Re:[PATCH v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension

ping Ref: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636932.html

Re: [PATCH] RISC-V: Fix loop invariant check

OK. I'm still a bit unsure about whether SSA_NAME_IS_DEFAULT_DEF can really occur but if it does it's not wrong to treat it as loop invariant. Regards Robin

Re:[PATCH] Support libcall __float{,un}sibf by SF when it is not supported for _bf16

I apologize for not attaching a reference link. Ref: https://patchwork.ozlabs.org/project/gcc/patch/2023091908.2089-1-ji...@linux.alibaba.com/ https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641119.html BR Jin

Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477]

On Tue, 9 Jan 2024, Uros Bizjak wrote: > On Tue, Jan 9, 2024 at 9:58?AM Richard Biener wrote: > > > > On Mon, 8 Jan 2024, Uros Bizjak wrote: > > > > > On Mon, Jan 8, 2024 at 5:57?PM Andrew Pinski wrote: > > > > > > > > On Mon, Jan 8, 2024 at 6:44?AM Uros Bizjak wrote: > > > > > > > > > > Instea

Re: [PATCH]middle-end: thread through existing LCSSA variable for alternative exits too [PR113237]

On Sun, 7 Jan 2024, Tamar Christina wrote: > Hi All, > > Builing on top of the previous patch, similar to when we have a single exit if > we have a case where all exits are considered early exits and there are > existing > non virtual phi then in order to maintain LCSSA we have to use the existi

[Ada] Fix PR ada/112781 (1/2)

This is a regression present on the mainline and 13 branch, in the form of a series of internal errors (3) on a function call returning the extension of a limited interface. This is only a partial fix for the first two assertion failures triggered by this case; the third one is the most problema

Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477]

On Tue, Jan 09, 2024 at 10:39:50AM +0100, Richard Biener wrote: > > x86 can't combine IOR/XOR in any meaningful way, but can combine the > > sequence of PLUS (together with MULT) RTXes to LEA. > > Btw, this looks like a three-insn combination even with IOR so a > pattern for this case would work a

Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477]

On Tue, Jan 9, 2024 at 10:44 AM Richard Biener wrote: > > On Tue, 9 Jan 2024, Uros Bizjak wrote: > > > On Tue, Jan 9, 2024 at 9:58?AM Richard Biener wrote: > > > > > > On Mon, 8 Jan 2024, Uros Bizjak wrote: > > > > > > > On Mon, Jan 8, 2024 at 5:57?PM Andrew Pinski wrote: > > > > > > > > > > On

Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477]

On Tue, 9 Jan 2024, Uros Bizjak wrote: > On Tue, Jan 9, 2024 at 10:44?AM Richard Biener wrote: > > > > On Tue, 9 Jan 2024, Uros Bizjak wrote: > > > > > On Tue, Jan 9, 2024 at 9:58?AM Richard Biener wrote: > > > > > > > > On Mon, 8 Jan 2024, Uros Bizjak wrote: > > > > > > > > > On Mon, Jan 8, 202

[Ada] Fix PR ada/112781 (2/2)

The problem occurs when this function call is the expression of a return in a function returning the limited interface; in this peculiar case, there is a mismatch between the callee, which has BIP formals but is not a BIP call, and the caller, which is a BIP function, that is spotted by an asser

Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477]

On Tue, Jan 9, 2024 at 11:06 AM Richard Biener wrote: > > On Tue, 9 Jan 2024, Uros Bizjak wrote: > > > On Tue, Jan 9, 2024 at 10:44?AM Richard Biener wrote: > > > > > > On Tue, 9 Jan 2024, Uros Bizjak wrote: > > > > > > > On Tue, Jan 9, 2024 at 9:58?AM Richard Biener wrote: > > > > > > > > > > O

Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477]

On Tue, Jan 9, 2024 at 11:19 AM Uros Bizjak wrote: > > On Tue, Jan 9, 2024 at 11:06 AM Richard Biener wrote: > > > > On Tue, 9 Jan 2024, Uros Bizjak wrote: > > > > > On Tue, Jan 9, 2024 at 10:44?AM Richard Biener wrote: > > > > > > > > On Tue, 9 Jan 2024, Uros Bizjak wrote: > > > > > > > > > On

[PATCH] Optimize A < B ? A : B to MIN_EXPR.

> I wonder if you can amend the existing patterns instead by iterating > over cond/vec_cond.  There are quite some (look for uses of > minmax_from_comparison) that could be adapted to vectors. > > The ones matching the simple form you match are > > #if GIMPLE > /* A >= B ? A : B -> max (A, B) and f

[PATCH] rs6000: Fix ASAN linker errors for Power ELF V1 ABI [PR113284]

Bootstrap and regtest running on ppc64le-redhat-linux and powerpc64-linux-gnu. Ok for trunk when successful? Use ASM_OUTPUT_FUNCTION_LABEL () instead of ASM_OUTPUT_LABEL () in the Power ELF V1 ABI branch of rs6000_elf_declare_function_name () to ensure that the .LASANPC label is emitted. The o

Re: [PATCH] rs6000: Fix ASAN linker errors for Power ELF V1 ABI [PR113284]

On Tue, Jan 09, 2024 at 11:51:16AM +0100, Ilya Leoshkevich wrote: > Bootstrap and regtest running on ppc64le-redhat-linux and > powerpc64-linux-gnu. Ok for trunk when successful? > > > > Use ASM_OUTPUT_FUNCTION_LABEL () instead of ASM_OUTPUT_LABEL () in > the Power ELF V1 ABI branch of rs6000_e

[PATCH] rs6000: New pass for replacement of adjacent lxv with lxvp.

Hello All: This pass is registered before ira rtl pass. Bootstrapped and regtested for powerpc64-linux-gnu. No regressions for spec 2017 benchmarks and improvements for some of the FP and INT benchmarks. Vladimir: I did modify IRA and LRA register Allocators. Please review. Thanks & Regards Aj

RE: [PATCH]middle-end: check if target can do extract first for early breaks [PR113199]

> > - > > - gimple_seq_add_seq (&stmts, tem); > > - > > - scalar_res = gimple_build (&stmts, CFN_EXTRACT_LAST, scalar_type, > > -mask, vec_lhs_phi); > > + scalar_res = gimple_build (&stmts, CFN_VEC_EXTRACT, TREE_TYPE > (vectype), > > +

RE: [PATCH]middle-end: Fix dominators updates when peeling with multiple exits [PR113144]

> This makes it quadratic in the number of vectorized early exit loops > in a function. The vectorizer CFG manipulation operates in a local > enough bubble that programmatic updating of dominators should be > possible (after all we manage to produce correct SSA form!), the > proposed change gets u

[PATCH]Arm: Update early-break tests to accept thumb output too.

Hi All, The tests I recently added for early break fail in thumb mode because in thumb mode `cbz/cbnz` exist and so the cmp+branch is fused. This updates the testcases to accept either output. Tested on arm-none-linux-gnueabihf with -mthumb/-marm. Ok for master? Thanks, Tamar gcc/testsuite/Ch

RE: [PATCH]Arm: Update early-break tests to accept thumb output too.

> -Original Message- > From: Tamar Christina > Sent: Tuesday, January 9, 2024 12:02 PM > To: gcc-patches@gcc.gnu.org > Cc: nd ; Richard Earnshaw ; > ni...@redhat.com; Kyrylo Tkachov > Subject: [PATCH]Arm: Update early-break tests to accept thumb output too. > > Hi All, > > The tests I

RE: [PATCH]middle-end: check if target can do extract first for early breaks [PR113199]

On Tue, 9 Jan 2024, Tamar Christina wrote: > > > - > > > - gimple_seq_add_seq (&stmts, tem); > > > - > > > - scalar_res = gimple_build (&stmts, CFN_EXTRACT_LAST, scalar_type, > > > - mask, vec_lhs_phi); > > > + scalar_res = gimple_build (&stmts, CFN_VEC_EXTRACT,

RE: [PATCH]middle-end: Fix dominators updates when peeling with multiple exits [PR113144]

On Tue, 9 Jan 2024, Tamar Christina wrote: > > This makes it quadratic in the number of vectorized early exit loops > > in a function. The vectorizer CFG manipulation operates in a local > > enough bubble that programmatic updating of dominators should be > > possible (after all we manage to prod

[PATCH] tree-optimization/113026 - fix vector epilogue maximum iter bound

The late amendment with a limit based on VF was redundant and wrong for peeled early exits. The following moves the adjustment done when we don't have a skip edge down to the place where the already existing VF based max iter check is done and removes the amendment. Bootstrapped and tested on x86

Re: [r14-7003 Regression] FAIL: gfortran.dg/power_8.f90 -O3 -g execution test on Linux/x86_64

On Tue, 9 Jan 2024, haochen.jiang wrote: > On Linux/x86_64, > > b3cc5a1efead520bc977b4ba51f1328d01b3e516 is the first bad commit > commit b3cc5a1efead520bc977b4ba51f1328d01b3e516 > Author: Richard Biener > Date: Fri Dec 15 10:32:29 2023 +0100 > > tree-optimization/113026 - avoid vector ep

[PATCH][gcc-13] libstdc++: Add Filesystem TS and std::stacktrace symbols to libstdc++exp.a

I was talking to Matthias Klose about enabling libstdc++_libbacktrace.a for Ubuntu's gcc package and I realised that it would be preferable if the gcc-13 branch had those libbacktrace symbols in libstdc++exp.a. I already did that for trunk with r14-3812-gb96b554592c5cb and trunk no longer installs

Re: [wwwdocs] gcc-14/changes.html: OpenMP - improve wording

Hi Tobias, On Mon, Jan 08 2024, Tobias Burnus wrote: > The attached patch there was no patch attached to your message. Martin > does a tiny updated to the OpenMP features (AMD GCN > now also has an optimized memcpy_rect not only nvptx), but the main > change is some shifting around to make it

Re: [PATCH] Add -mevex512 into invoke.texi

On Tue, Jan 9, 2024 at 8:04 AM Haochen Jiang wrote: > > Hi all, > > In invoke.texi, -mevex512 is missing. This patch adds that. > > Ok for trunk? You add it to the "index" but not document its semantics? > Thx, > Haochen > > gcc/ChangeLog: > > * doc/invoke.texi: Add -mevex512. > --- > g

[committed] aarch64: Fix up GC of aarch64_simd_types [PR113270]

Hi! The r14-6524 changes created aarch64-builtins.h header and moved struct aarch64_simd_type_info definition in there. Unfortunately, the new header wasn't added to target_gtfiles, so the trees and const char * pointer elements in the aarch64_simd_types array aren't marked as GC roots anymore. T

RE: [PATCH]Arm: Update early-break tests to accept thumb output too.

> > 3f40b2a241953 100644 > > --- a/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c > > +++ b/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c > > @@ -16,8 +16,12 @@ int b[N] = {0}; > > ** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ > > ** vpmax.u32 d[0-9]+, d[0-9]+, d[0-9]+ > >

Re: [PATCH v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option

On Tue, Jan 9, 2024 at 8:17 AM Li, Pan2 wrote: > > The test case pr30957-1.c first comes from this commit about 19 years ago > which expect the -1.0 for testing. > > https://github.com/gcc-mirror/gcc/commit/290358f770d21d9204ea621f839ee8fba606a275 > > Then the below commit changes from -1.0 to +1

[COMMITTED] ada: Fix precondition in Interfaces.C.Strings

From: Joffrey Huguet The precondition of both Update procedures in Interfaces.C.Strings were incorrect. This patch fixes this. gcc/ada/ * libgnat/i-cstrin.ads (Update): Fix precondition. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/libgnat/i-cstrin.ads | 9 +---

[COMMITTED] ada: Error compiling Ada 2022 object renaming with no subtype mark

From: Steve Baird In some cases the compiler would crash or generate spurious errors compiling a legal object renaming declaration that lacks a subtype mark. In addition to fixing the immediate problem, change Atree.Copy_Slots so that attempts to modify either the Empty or the Error nodes (e.g.,

[COMMITTED] ada: Avoid xref on out params of TSS

From: Bob Duff For an actual passed as an 'in out' parameter of a type support subprogram such as deep finalize, do not count it as a read reference of the actual. Clearly these should not count. Furthermore, counting them causes different warnings in -gnatc mode compared to normal mode, because

[COMMITTED] ada: Fix uses of not Present

From: Piotr Trojanek Fix style violation reported by GNATcheck. gcc/ada/ * sem_aggr.adb (Resolve_Container_Aggregate): Use "No". * sem_ch8.adb (Find_Direct_Name): Likewise. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/sem_aggr.adb | 2 +- gcc/ada/sem_ch8.ad

[COMMITTED] ada: Fix bug in Sem_Util.Enclosing_Declaration

From: Steve Baird Fix Sem_Util.Enclosing_Declaration to not return an N_Subprogram_Specification node. Remove code in various places that was formerly needed to cope with this misbehavior. gcc/ada/ * sem_util.adb (Enclosing_Declaration): Instead of returning a subprogram specifi

[COMMITTED] ada: Remove unreachable code in Resolve_Extension_Aggregate

From: Eric Botcazou The only functions using the BIP protocol are now those returning a limited type: Is_Build_In_Place_Result_Type => Is_Inherently_Limited_Type. gcc/ada/ * sem_aggr.adb (Resolve_Extension_Aggregate): Remove the unreachable call to Transform_BIP_Assignment as we

[COMMITTED] ada: Cannot requeue to a procedure implemented by an entry

From: Javier Miranda Add missing support for RM 9.5.4(5.6/4): the target of a requeue statement may be a procedure when its name denotes a renaming of an entry. gcc/ada/ * sem_ch6.adb (Analyze_Subprogram_Specification): Do not replace the type of the formals with its correspondi

[COMMITTED] ada: Minor change replacing "not Present" tests with "No" tests

From: Gary Dismukes Fixing two places flagged by gnatcheck to use "No" instead of "not Present". gcc/ada/ * exp_aggr.adb (Expand_Container_Aggregate): Change "not Present" tests to tests using "No" (in two places). Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/a

[COMMITTED] ada: Excess elements created for indexed aggregates with iterator_specifications

From: Gary Dismukes In the case of an indexed aggregate of a container type with both Add_Unnamed and New_Indexed specified in the Aggregate aspect of the type (such as for the Vector type in Ada.Containers.Vectors), in cases where a component association is given by an iterator_specification, th

[COMMITTED] ada: Add __atomic_store_n binding to System.Atomic_Primitives

From: Eric Botcazou This is modeled on the existing binding for __atomic_load_n. gcc/ada/ * libgnat/s-atopri.ads (Atomic_Store): New generic procedure. (Atomic_Store_8): New instantiated procedure. (Atomic_Store_16): Likewise. (Atomic_Store_32): Likewise.

[COMMITTED] ada: Remove side effects depending on the context of subtype declaration

From: Piotr Trojanek In GNATprove mode the removal of side effects is only needed in certain syntactic contexts, which include subtype declarations. Now this removal is limited to genuine subtype declarations and not to itypes coming from expressions where side effects are not expected. gcc/ada/

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