You mean theadvector doesn't want the current RVV1.0 register overlap magic as
follows ?
The destination EEW is smaller than the source EEW and the overlap is in the
lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi
v0, v0, 3 is legal, but a destination of v1 is not
Hi!
My recent change to use m_data[save_data_cnt] instead of
m_data[save_data_cnt + 1] when inside of a loop (m_bb is non-NULL)
broke the following testcase. When we create a PHI node on the loop
using prepare_data_in_out, both m_data[save_data_cnt{, + 1}] are
computed and the fix was right, but
Hi!
On the following testcase earlier passes leave around an unreleased
SSA_NAME - non-GIMPLE_NOP SSA_NAME_DEF_STMT which isn't in any bb.
The following patch makes bitint lowering resistent against those,
the first hunk is where we'd for certain kinds of stmts try to ammend
them and the latter is
Following code will cause ICE on LoongArch target:
#include
extern void bar (__m128i, __m128i);
__m128i a;
void
foo ()
{
bar (a, a);
}
It is caused by missing constraint definition in mov_lsx. This
patch fixes the template and remove the unnecessary processing from
loongarch
Hi!
Large/huge _BitInt types are returned in memory and the bitint lowering
pass right now relies on that.
The gimplification etc. use aggregate_value_p to see if it should be
returned in memory or not and use
= _123;
return ;
rather than
return _123;
But expand_thunk used e.g. by IPA-ICF w
When investigaing failure of gcc.dg/vect/slp-reduc-sad.c, following
instruction block are being generated by vec_concatv32qi (which is
generated by vec_initv32qiv16qi) at entrance of foo() function:
vldx$vr3,$r5,$r6
vld $vr2,$r5,0
xvpermi.q $xr2,$xr3,0x20
causes the reversion
Hi!
As discussed in the PR, the following testcase is miscompiled on RISC-V
64-bit, because num_sign_bit_copies in one spot pretends the bits in
a paradoxical SUBREG beyond SUBREG_REG SImode are all sign bit copies:
5444 /* For paradoxical SUBREGs on machines where all register
opera
int n = 0;
auto f = [](this Self){
static_assert(__is_same (decltype(n), int));
decltype((n)) a; // { dg-error {is not captured} }
};
f();
Could you clarify if this error being removed was intentional. I do
recall that Patrick Palka wanted to remove this error in his patch, but
i
These two options are negative alias of -m[no-]strict-align.
This matches LLVM implmentation.
gcc/ChangeLog:
* config/riscv/riscv.opt: Add option alias.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-align-10.c: New test.
* gcc.target/riscv/predef-align-7.c: New test.
* gcc.target/riscv/pr
Hm, this is weird, as it really seems to depend on the
-march= So if there is really a difference
between those structs which make them incompatible on
some archs, we should not consider them to be
compatible in general.
struct g { int a[n]; int b; } *y;
{ struct g { int a[4]; int b; } *y2
Consider this following case:
foo:
ble a0,zero,.L11
lui a2,%hi(.LANCHOR0)
addisp,sp,-128
addia2,a2,%lo(.LANCHOR0)
mv a1,a0
vsetvli a6,zero,e32,m8,ta,ma
vid.v v8
vs8r.v v8,0(sp) ---> spill
.L
On Thu, Dec 21, 2023 at 11:38 AM Jason Merrill wrote:
>
> On 12/21/23 10:52, Patrick Palka wrote:
> > On Thu, Dec 21, 2023 at 8:29 AM Patrick Palka wrote:
> >>
> >> On Wed, 20 Dec 2023, Ken Matsui wrote:
> >>
> >>> This patch removes the testsuite_tr1.h dependency from g++.dg/ext/is_*.C
> >>> tes
Pushed to r14-6800.
在 2023/12/5 下午2:44, chenxiaolong 写道:
gcc/ChangeLog:
* doc/extend.texi:Add modifiers to the vector of asm in the doc.
* doc/md.texi:Refine the description of the modifier 'f' in the doc.
---
gcc/doc/extend.texi | 47 ++
This patch removes the testsuite_tr1.h dependency from g++.dg/ext/is_*.C
tests since the header is supposed to be used only by libstdc++, not
front-end. This also includes test code consistency fixes.
For the record this fixes the test failures reported at
https://gcc.gnu.org/pipermail/gcc-patche
> Am 22.12.2023 um 09:12 schrieb Jakub Jelinek :
>
> Hi!
>
> My recent change to use m_data[save_data_cnt] instead of
> m_data[save_data_cnt + 1] when inside of a loop (m_bb is non-NULL)
> broke the following testcase. When we create a PHI node on the loop
> using prepare_data_in_out, both m
> Am 22.12.2023 um 09:17 schrieb Jakub Jelinek :
>
> Hi!
>
> On the following testcase earlier passes leave around an unreleased
> SSA_NAME - non-GIMPLE_NOP SSA_NAME_DEF_STMT which isn't in any bb.
> The following patch makes bitint lowering resistent against those,
> the first hunk is where
> Am 22.12.2023 um 09:26 schrieb Jakub Jelinek :
>
> Hi!
>
> Large/huge _BitInt types are returned in memory and the bitint lowering
> pass right now relies on that.
> The gimplification etc. use aggregate_value_p to see if it should be
> returned in memory or not and use
> = _123;
> retur
This patch resolves the failure of pr43644-2.c in the testsuite, a code
quality test I added back in July, that started failing as the code GCC
generates for 128-bit values (and their parameter passing) has been in
flux. After a few attempts at tweaking pattern constraints in the hope
of convinci
This patch resolves the second part of PR target/112992, building upon
Hongtao Liu's solution to the first part.
The issue addressed by this patch is that when initializing vectors by
broadcasting integer constants, the compiler has the flexibility to
select the most appropriate vector mode to pe
Hi Juzhe,
What xtheadvector needs to handle is just that destination vector register
cannot overlap source vector register group for instructions like vmadc/vmsbc.
That is not what group_overlap means. We nned to add "&" to the registers in
the corresponding xtheadvector patterns while rvv 1.0 d
Yeah.
(define_insn "@pred_msbc"
[(set (match_operand: 0 "register_operand""=vr, vr, &vr")
(unspec:
[(minus:VI
(match_operand:VI 1 "register_operand" " 0, vr, vr")
(match_operand:VI 2 "register_operand" " vr, 0, vr"))
(match_operand: 3 "register_oper
> Bootstrapped/regtested on x86_64-linux and i686-linux (neither of which
> is WORD_REGISTER_OPERATIONS target), tested on the testcase using
> cross to riscv64-linux but don't have an easy access to a
> WORD_REGISTER_OPERATIONS target to bootstrap/regtest it there.
>
> Ok for trunk?
Yes, thanks
From: Daniil Frolov
PR 66487 is asking to provide sanitizer-like detection for C++ object
lifetime violations that are worked around with -fno-lifetime-dse or
-flifetime-dse=1 in Firefox, LLVM (PR 106943), OpenJade (PR 69534).
The discussion in the PR was centered around extending MSan, but MSan
v3: rebased to latest trunk
Cleanup memset implementation. Similar to memcpy/memmove, use an offset and
bytes throughout. Simplify the complex calculations when optimizing for size
by using a fixed limit.
Passes regress & bootstrap.
gcc/ChangeLog:
* config/aarch64/aarch64.h (MAX_SET_SI
Hi.
This patch adds missing builtins needed by optimizations.
Thanks for the review.
From 5ef20748a140d3384294a4218e6db7420cef692d Mon Sep 17 00:00:00 2001
From: Antoni Boucher
Date: Tue, 3 Jan 2023 15:04:41 -0500
Subject: [PATCH] libgccjit: Add missing builtins needed by optimizations
gcc/jit/Ch
Updated the fix in attachment.
Is it OK for trunk?
Tested on aarch64-unknown-linux-gnu and x86_64-pc-linux-gnu.
Thanks,
Di Zhao
> -Original Message-
> From: Di Zhao OS
> Sent: Sunday, December 17, 2023 8:31 PM
> To: Thomas Schwinge ; gcc-patches@gcc.gnu.org
> Cc: Richard Biener
> Subj
Hi.
This patch adds the support of the sizeof operator.
I was wondering if this new API entrypoint should take a location as a
parameter. What do you think?
Thanks for the review.
From e86e00efae450f04bc92ae6e4e61cf92c38d9b7d Mon Sep 17 00:00:00 2001
From: Antoni Boucher
Date: Tue, 19 Sep 2023 22:
> Am 22.12.2023 um 16:05 schrieb Di Zhao OS :
>
> Updated the fix in attachment.
>
> Is it OK for trunk?
Ok
> Tested on aarch64-unknown-linux-gnu and x86_64-pc-linux-gnu.
>
> Thanks,
> Di Zhao
>
>> -Original Message-
>> From: Di Zhao OS
>> Sent: Sunday, December 17, 2023 8:31 PM
On Thu, 21 Dec 2023, Martin Uecker wrote:
> This version now sets DECL_NONADDRESSABLE_P, DECL_PADDING_P
> and C_DECL_VARIABLE_SIZE and adds three new tests:
> c23-tag-alias-7.c, c23-tag-composite-10.c, and
> gnu23-tag-composite-5.c.
This version is OK.
--
Joseph S. Myers
jos...@codesourcery.
On 12/22/23 02:51, Juzhe-Zhong wrote:
Consider this following case:
foo:
ble a0,zero,.L11
lui a2,%hi(.LANCHOR0)
addisp,sp,-128
addia2,a2,%lo(.LANCHOR0)
mv a1,a0
vsetvli a6,zero,e32,m8,ta,ma
vid.v v8
On 12/22/23 01:07, juzhe.zh...@rivai.ai wrote:
You mean theadvector doesn't want the current RVV1.0 register overlap
magic as follows ?
*
The destination EEW is smaller than the source EEW and the overlap
is in the lowest-numbered part of the source register group (e.g.,
when
On 12/22/23 04:01, waffl3x wrote:
int n = 0;
auto f = [](this Self){
static_assert(__is_same (decltype(n), int));
decltype((n)) a; // { dg-error {is not captured} }
};
f();
Could you clarify if this error being removed was intentional. I do
recall that Patrick Palka wanted
RVV requires VSET?VL? instructions to dynamically configure VLEN at
runtime. There's a custom pass to do that which has a simple mode
which generates a VSETVL for each V insn and a lazy/optimal mode which
uses LCM dataflow to move VSETVL around, identify/delete the redundant
ones.
Currently simple
Some spiders are hitting bugzilla hard generating dependency trees
or graphs, downloading large attachements or requesting all bugs
in xml format. Disallow all that.
---
htdocs/robots.txt | 4
1 file changed, 4 insertions(+)
diff --git a/htdocs/robots.txt b/htdocs/robots.txt
index b9fc830d..
Consider this following case:
foo:
ble a0,zero,.L11
lui a2,%hi(.LANCHOR0)
addisp,sp,-128
addia2,a2,%lo(.LANCHOR0)
mv a1,a0
vsetvli a6,zero,e32,m8,ta,ma
vid.v v8
vs8r.v v8,0(sp) ---> spill
.L
Committed. Thanks Jeff.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-12-23 00:58
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng; kito.cheng; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Make PHI initial value occupy live V_REG in
dynamic LMUL cost model analysis
On 12/22/23 02:51, Juzhe-Zhong wr
LGTM!
Thanks!
在 2023/12/17 下午11:16, Xi Ruoyao 写道:
Remove a redundant sign extension.
gcc/ChangeLog:
* config/loongarch/loongarch.md (rotrsi3_extend): New
define_insn.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/rotrw.c: New test.
---
Bootstrapped and regtested o
在 2023/12/22 下午3:21, chenglulu 写道:
在 2023/12/22 下午3:09, Xi Ruoyao 写道:
On Fri, 2023-12-22 at 11:44 +0800, chenglulu wrote:
在 2023/12/21 下午8:00, chenglulu 写道:
Sorry, I've been busy with something else these two days. I don't
think there's anything wrong with the code,
but I need to test the
在 2023/12/23 上午10:26, chenglulu 写道:
在 2023/12/22 下午3:21, chenglulu 写道:
在 2023/12/22 下午3:09, Xi Ruoyao 写道:
On Fri, 2023-12-22 at 11:44 +0800, chenglulu wrote:
在 2023/12/21 下午8:00, chenglulu 写道:
Sorry, I've been busy with something else these two days. I don't
think there's anything wrong wi
Hi Juzhe,
Sorry but I'm not quite familiar with the group_overlap framework. Could you
take this pattern as an example to show how to disable an alternative in some
target?
Joshua
--
发件人：juzhe.zh...@rivai.ai
发送时间：2023年12月22日(星期五) 18
Hi,
This patch will cause the following tests to fail: +FAIL:
gcc.dg/vect/pr97081-2.c (internal compiler error: in extract_insn, at
recog.cc:2812) +FAIL: gcc.dg/vect/pr97081-2.c (test for excess errors)
+FAIL: gcc.dg/vect/pr97081-2.c -flto -ffat-lto-objects (internal
compiler error: in extrac
On Friday, December 22nd, 2023 at 10:26 AM, Jason Merrill
wrote:
>
>
> On 12/22/23 04:01, waffl3x wrote:
>
> > int n = 0;
> > auto f = [](this Self){
> > static_assert(__is_same (decltype(n), int));
> > decltype((n)) a; // { dg-error {is not captured} }
> > };
> > f();
> >
> > Could you clari
42 matches
Mail list logo
