Re: [PATCH] LoongArch: Use the movcf2gr instruction to implement cstore4

On Thu, 2023-12-14 at 15:44 +0800, Jiahao Xu wrote: > The implementation of this patch has some issues. When I compile 521.wrf with > -Ofast -mlasx -flto -muse-movcf2gr, it results in an ICE: Indeed, creating CCCmode pseudos without a complete movfcc implementation is buggy. This patch needs a

[PATCH] expmed: Get vec_extract element mode from insn_data, [PR112999]

Hi, this is a bit of a follow up of the latest expmed change. In extract_bit_field_1 we try to get a better vector mode before extracting from it. Better refers to the case when the requested target mode does not equal the inner mode of the vector to extract from and we have an equivalent tieabl

Re: [PATCH] i386: Remove RAO-INT from Grand Ridge

On Thu, Dec 14, 2023 at 10:55 AM Haochen Jiang wrote: > > Hi all, > > According to ISE050 published at the end of September, RAO-INT will not > be in Grand Ridge anymore. This patch aims to remove it. > > The documentation comes following: > > https://cdrdv2.intel.com/v1/dl/getContent/671368 > > R

Re: Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

Hi, Richard. I have a question about the decrement IV costing since I find the reduction case is generating inferior codegen. reduc_plus_int: mv a3,a0 ble a1,zero,.L7 addiw a5,a1,-1 li a4,2 bleu a5,a4,.L8 vsetivli zero,4,e32,m1,ta,ma srliw a4,a1,2 vmv.v.i v1,0 slli a4,a4,4 add a4,a4,a0 mv a5,a0

Re: Re: [PATCH 4/5] [ifcvt] optimize x=c ? (y op const_int) : y by RISC-V Zicond like insns

On 2023-12-11 13:38  Jeff Law wrote: > > > >On 12/5/23 01:12, Fei Gao wrote: >> op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT, AND] >> >> Co-authored-by: Xiao Zeng >> >> gcc/ChangeLog: >> >>  * ifcvt.cc (noce_cond_zero_shift_op_supported): check if OP is >>shift

Re: Re: [PATCH 5/5] [ifcvt] optimize extension for x=c ? (y op z) : y by RISC-V Zicond like insns

On 2023-12-11 13:46  Jeff Law wrote: > > > >On 12/5/23 01:12, Fei Gao wrote: >> SIGN_EXTEND, ZERO_EXTEND and SUBREG has been considered >> to support SImode in 64-bit machine. >> >> Co-authored-by: Xiao Zeng >> >> gcc/ChangeLog: >> >> * ifcvt.cc (noce_cond_zero_binary_op_supported): add support fo

Re: [PR target/110201] Fix operand types for various scalar crypto insns

On Tue, Jun 20, 2023 at 12:34 AM Jeff Law via Gcc-patches wrote: > > > A handful of the scalar crypto instructions are supposed to take a > constant integer argument 0..3 inclusive. A suitable constraint was > created and used for this purpose (D03), but the operand's predicate is > "register_ope

Re: [PATCH] RISC-V: fix scalar crypto pattern

On Thu, Dec 14, 2023 at 1:40 AM Jeff Law wrote: > On 12/13/23 02:03, Christoph Müllner wrote: > > On Wed, Dec 13, 2023 at 9:22 AM Liao Shihua wrote: > >> > >> In Scalar Crypto Built-In functions, some require immediate parameters, > >> But register_operand are incorrectly used in the pattern. > >

Re: [committed] testsuite: Fix up target-enter-data-1.c on 32-bit targets

On Thu, 14 Dec 2023 08:14:56 +0100 Jakub Jelinek wrote: > On Wed, Nov 29, 2023 at 11:43:05AM +, Julian Brown wrote: > > * c-c++-common/gomp/target-enter-data-1.c: Adjust scan > > output. > > struct bar { int num_vectors; double *vectors; }; > > is 16 bytes only on 64-bit targets, on 3

Re: [PATCH v4] A new copy propagation and PHI elimination pass

Successfully bootstrapped and regtested on x86_64-linux. Will push to master. Filip

Re: [PATCH] match.pd: Simplify (t * u) / v -> t * (u / v) [PR112994]

> Am 14.12.2023 um 08:35 schrieb Jakub Jelinek : > > Hi! > > The following testcase is optimized just on GENERIC (using > strict_overflow_p = false; > if (TREE_CODE (arg1) == INTEGER_CST > && (tem = extract_muldiv (op0, arg1, code, NULL_TREE, >

Re: [PATCH] match.pd: Simplify (t * u) / (t * v) [PR112994]

> Am 14.12.2023 um 08:37 schrieb Jakub Jelinek : > > Hi! > > On top of the previously posted patch, this simplifies say (x * 16) / (x * 4) > into 4. Unlike the previous pattern, this is something we didn't fold > previously on GENERIC, so I think it shouldn't be all wrapped with #if > GIMPLE

Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

Am 14.12.2023 um 09:28 schrieb juzhe.zh...@rivai.ai: Hi, Richard.I have a question about the decrement IV costing since I find the reduction case is generating inferior codegen.reduc_plus_int: mv a3,a0 ble a1,zero,.L7 addiw a5,a1,-1 li a4,2 bleu a5,a4,.L8 vsetivli zero,4,e32,m1,ta,ma srliw a4,a1,2

Re: Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

Thanks Richard. Let me clarify again to make sure I understand your comments correctly: Do you suggest not to model address cost here like other partial vectorization style (while_ult, avx512...etc). Then set COST = 1 since we only have SELECT_VL since beginning. At various cases we saw, COST=1

Re: [PATCH] RISC-V: fix scalar crypto pattern

Sorry, I was not aware of this patch. Since Jeff's patch was here first and also includes more tests, I propose to move forward with his patch (but I'm not a maintainer!). Therefore, I've reviewed Jeff's patch and replied to his email. FWIW: Jeff's patch can be found here: https://gcc.gnu.org/

[PATCH] LoongArch: Fix incorrect code generation for sad pattern

When I attempt to enable vect_usad_char effective target for LoongArch, some tests fail. These tests fail because the sad pattern generates bad code. This patch to fixed them, for sad patterns, use zero expansion instead of sign expansion for reduction. Currently, we are fixing failed vectorized t

Re: [PATCH] expmed: Get vec_extract element mode from insn_data, [PR112999]

Robin Dapp writes: > Hi, > > this is a bit of a follow up of the latest expmed change. > > In extract_bit_field_1 we try to get a better vector mode before > extracting from it. Better refers to the case when the requested target > mode does not equal the inner mode of the vector to extract from

[PATCH] Revert "RISC-V: Add avail interface into function_group_info"

This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc. Will refactor this part in the same way as aarch64 sve. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Revert changes.

RE: [PATCH v7] libgfortran: Replace mutex with rwlock

Hi Lipeng! On 2023-12-14T02:28:22+, "Zhu, Lipeng" wrote: > On 2023/12/14 4:52, Thomas Schwinge wrote: >> On 2023-12-12T02:05:26+, "Zhu, Lipeng" wrote: >> > On 2023/12/12 1:45, H.J. Lu wrote: >> >> On Sat, Dec 9, 2023 at 7:25 PM Zhu, Lipeng >> wrote: >> >> > On 2023/12/9 23:23, Jakub Jel

RE: [PATCH v7] libgfortran: Replace mutex with rwlock

Hi, Thomas Schwinge wrote:   On 2023-12-14T02:28:22+, "Zhu, Lipeng" wrote: On 2023/12/14 4:52, Thomas Schwinge wrote: >> I've just filed > Would

Re: [PATCH v7] libgfortran: Replace mutex with rwlock

On Thu, Dec 14, 2023 at 01:29:01PM +0100, Thomas Schwinge wrote: > > Sure, I will look into that. > > > > BTW, I didn’t have the PowerPC in hands, do you mind granting the access of > > your > > test environment to me to help reproduce the issue? > > That's unfortunately not possible: it's behind

Re: [PATCH] Revert "RISC-V: Add avail interface into function_group_info"

ok On Thu, Dec 14, 2023 at 8:08 PM Feng Wang wrote: > > This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc. > Will refactor this part in the same way as aarch64 sve. > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): >

[PATCH v2] LoongArch: Fix incorrect code generation for sad pattern

When I attempt to enable vect_usad_char effective target for LoongArch, slp-reduc-sad.c and vect-reduc-sad*.c tests fail. These tests fail because the sad pattern generates bad code. This patch to fixed them, for sad patterns, use zero expansion instead of sign expansion for reduction. Currentl

Re: Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

On Thu, 14 Dec 2023, juzhe.zh...@rivai.ai wrote: > Thanks Richard. > > Let me clarify again to make sure I understand your comments correctly: > > Do you suggest not to model address cost here like other partial > vectorization style (while_ult, avx512...etc). Then set COST = 1 since > we only

[committed] Revert "RISC-V: Add avail interface into function_group_info"

This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc. Will refactor this part in the same way as aarch64 sve. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Revert changes.

RE: [PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit code

On Wed, 13 Dec 2023, Tamar Christina wrote: > > > > else if (vect_use_mask_type_p (stmt_info)) > > > > { > > > > unsigned int precision = stmt_info->mask_precision; > > > > scalar_type = build_nonstandard_integer_type (precision, 1); > > > > vectype = get_mask_type_for_scal

In 'gcc/gimple-ssa-sccopy.cc', '#define INCLUDE_ALGORITHM' instead of '#include ' (was: [PATCH v4] A new copy propagation and PHI elimination pass)

Hi! On 2023-12-13T17:12:11+0100, Filip Kastl wrote: > --- /dev/null > +++ b/gcc/gimple-ssa-sccopy.cc > +#include Pushed to master branch commit 65e41f4fbfc539c5cc429c684176f8ea39f4b8f2 "In 'gcc/gimple-ssa-sccopy.cc', '#define INCLUDE_ALGORITHM' instead of '#include '", see attached. Grüße

Re: [PATCH] middle-end: Fix up constant handling in emit_conditional_move [PR111260]

On Wed, Dec 13, 2023 at 5:51 PM Andrew Pinski wrote: > > After r14-2667-gceae1400cf24f329393e96dd9720, we force a constant to a > register > if it is shared with one of the other operands. The problem is used the > comparison > mode for the register but that could be different from the operand m

[committed] Fix m68k testcase for c99

More fallout from the c99 conversion. The m68k specific test pr63347.c calls exit and abort without a prototype in scope. This patch turns them into __builtin calls avoiding the error. Bootstrapped and regression tested on m68k-linux-gnu, pushed to the trunk. Jeffcommit 679adb2396a911b599

[PATCH] Middle-end: Do not model address cost for SELECT_VL style vectorization

Follow Richard's suggestions, we should not model address cost in the loop vectorizer for select_vl or decrement IV since other style vectorization doesn't do that. To make cost model comparison apple to apple. This patch set COST from 2 to 1 which turns out have better codegen in various codegen

[PATCH] aarch64: Improve handling of accumulators in early-ra

Being very simplistic, early-ra just models an allocno's live range as a single interval. This doesn't work well for single-register accumulators that are updated multiple times in a loop, since in SSA form, each intermediate result will be a separate SSA name and will remain separate from the acc

Re: Re: [PATCH] Middle-end: Adjust decrement IV style partial vectorization COST model

Thanks a lot for the clarification. I send a patch to remove address memory cost: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640595.html for decremnt IV/SELECT_VL. And I have tested various cases that are all get better codegen in RVV. juzhe.zh...@rivai.ai From: Richard Biener

Re: [PATCH v3 5/5] aarch64: Add function multiversioning support

Andrew Carlotti writes: > This adds initial support for function multiversioning on aarch64 using > the target_version and target_clones attributes. This loosely follows > the Beta specification in the ACLE [1], although with some differences > that still need to be resolved (possibly as follow-u

[pushed] analyzer: cleanups [PR112655]

Avoid copying eedges in infinite_loop::infinite_loop. Use initializer lists in the various places reported in PR analyzer/112655 (apart from coord_test's ctor, which would require nontrivial refactoring). Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-6549-g

Re: [pushed 1/4] c++: copy location to AGGR_INIT_EXPR

On Wed, Dec 13, 2023 at 08:38:12PM -0500, Jason Merrill wrote: > On 12/13/23 19:00, Marek Polacek wrote: > > On Wed, Dec 13, 2023 at 11:47:37AM -0500, Jason Merrill wrote: > > > Tested x86_64-pc-linux-gnu, applying to trunk. > > > > > > -- 8< -- > > > > > > When building an AGGR_INIT_EXPR from a

Re: [PATCH v7 4/5] OpenMP/OpenACC: Unordered/non-constant component offset runtime diagnostic

On 19.08.23 00:47, Julian Brown wrote: This patch adds support for non-constant component offsets in "map" clauses for OpenMP (and the equivalants for OpenACC), which are not able to be sorted into order at compile time. Normally struct accesses in such clauses are gathered together and sorted i

Re: [PATCH] RISC-V: fix scalar crypto pattern

On 12/14/23 02:48, Christoph Müllner wrote: On Thu, Dec 14, 2023 at 1:40 AM Jeff Law wrote: On 12/13/23 02:03, Christoph Müllner wrote: On Wed, Dec 13, 2023 at 9:22 AM Liao Shihua wrote: In Scalar Crypto Built-In functions, some require immediate parameters, But register_operand are inco

Re: [PATCH v3 4/5] Add support for target_version attribute

Andrew Carlotti writes: > This patch adds support for the "target_version" attribute to the middle > end and the C++ frontend, which will be used to implement function > multiversioning in the aarch64 backend. > > On targets that don't use the "target" attribute for multiversioning, > there is no

[COMMITTED] Initial libgrust build patches

Hi, This patchset contains the initial changes to add the libgrust folder to gcc, which will later contain libraries used by our Rust frontend. This work was done by Pierre-Emmanuel Patry as part of his work on supporting procedural macros in our frontend. It was then tested by Thomas Schwinge, a

[PATCH 0/4] v3 of: Option handling: add documentation URLs

> Hi David, > > On Fri, Dec 08, 2023 at 06:35:56PM -0500, David Malcolm wrote: > > On Tue, 2023-11-21 at 23:43 +, Joseph Myers wrote: > > > On Tue, 21 Nov 2023, Tobias Burnus wrote: > > > > > > > On 21.11.23 14:57, David Malcolm wrote: > > > > > On Tue, 2023-11-21 at 02:09 +0100, Hans-Peter N

[PATCH 3/4; v2] opts: add logic to generate options-urls.cc

Changed in v2: - split out from the code that uses this - now handles lang-specific URLs, as well as generic URLs - the generated options-urls.cc now contains a function with a switch statement, rather than an array, to support lang-specific URLs: const char * get_opt_url_suffix (int option_in

[PATCH 4/4; v2] options: wire up options-urls.cc into gcc_urlifier

Changed in v2: - split out from the code that generates options-urls.cc - call the generated function, rather than use a generated array - pass around lang_mask gcc/ChangeLog: * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask param. (diagnostic_context::make_opt

[COMMITTED 1/4] libgrust: Add ChangeLog file

From: Pierre-Emmanuel Patry libgrust/ChangeLog: * ChangeLog: New file. Signed-off-by: Pierre-Emmanuel Patry --- libgrust/ChangeLog | 6 ++ 1 file changed, 6 insertions(+) create mode 100644 libgrust/ChangeLog diff --git a/libgrust/ChangeLog b/libgrust/ChangeLog new file mode 100

[PATCH 1/4; v3] options: add gcc/regenerate-opt-urls.py

Changed in v3: - Makefile.in: added OPT_URLS_HTML_DEPS and a comment Changed in v2: - added convenience targets to Makefile for regenerating the .opt.urls files, and for running unit tests for the generation code - parse gdc and gfortran documentation, and create LangUrlSuffix_{lang} directives

[COMMITTED 2/4] libgrust: Add entry for maintainers

From: Pierre-Emmanuel Patry ChangeLog: * MAINTAINERS: Add maintainers for libgrust. contrib/ChangeLog: * gcc-changelog/git_commit.py: Add libgrust. Co-authored-by: Arthur Cohen Signed-off-by: Pierre-Emmanuel Patry --- MAINTAINERS | 1 + contrib/gcc-c

[COMMITTED 4/4] build: Add libgrust as compilation modules

From: Pierre-Emmanuel Patry Define the libgrust directory as a host compilation module as well as for targets. Disable target libgrust if we're not building target libstdc++. ChangeLog: * Makefile.def: Add libgrust as host & target module. * configure.ac: Add libgrust to host to

[PATCH] tree-optimization/112793 - SLP of constant/external code-generated twice

The following makes the attempt at code-generating a constant/external SLP node twice well-formed as that can happen when partitioning BB vectorization attempts where we keep constants/externals unpartitioned. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimizati

Re: [committed] d: Merge upstream dmd, druntime 2bbf64907c, phobos b64bfbf91

Thomas Schwinge writes: > On 2023-12-11T11:13:28+0100, Iain Buclaw wrote: >> Excerpts from Iain Buclaw's message of Dezember 11, 2023 11:07 am: >>> This patch merges the D front-end and runtime library with upstream dmd >>> 2bbf64907c, and the standard library with phobos b64bfbf91. >>> >>> Sync

Re: [PATCH] Middle-end: Do not model address cost for SELECT_VL style vectorization

On Thu, 14 Dec 2023, Juzhe-Zhong wrote: > Follow Richard's suggestions, we should not model address cost in the loop > vectorizer for select_vl or decrement IV since other style vectorization > doesn't > do that. > > To make cost model comparison apple to apple. > This patch set COST from 2 to 1

Re: [PATCH v7] libgfortran: Replace mutex with rwlock

On 09/12/2023 15:39, Lipeng Zhu wrote: > This patch try to introduce the rwlock and split the read/write to > unit_root tree and unit_cache with rwlock instead of the mutex to > increase CPU efficiency. In the get_gfc_unit function, the percentage > to step into the insert_unit function is around 3

[PATCH] tree-optimization/113018 - ICE with BB reduction vectorization

When BB reduction vectorization picks up a chain with an ASM def in it and that's inside the vectorized region we fail to get its LHS. Instead of trying to get the correct def the following avoids vectorizing such def and instead keeps it as def to add in the epilog. Bootstrapped and tested on x8

Re: [PATCH] expmed: Get vec_extract element mode from insn_data, [PR112999]

> It looks like: > > FOR_EACH_MODE_FROM (new_mode, new_mode) > if (known_eq (GET_MODE_SIZE (new_mode), GET_MODE_SIZE (GET_MODE (op0))) > && known_eq (GET_MODE_UNIT_SIZE (new_mode), GET_MODE_SIZE (tmode)) > && targetm.vector_mode_supported_p (new_mode) > &&

Re: [PATCH] expmed: Get vec_extract element mode from insn_data, [PR112999]

Robin Dapp writes: >> It looks like: >> >> FOR_EACH_MODE_FROM (new_mode, new_mode) >> if (known_eq (GET_MODE_SIZE (new_mode), GET_MODE_SIZE (GET_MODE (op0))) >> && known_eq (GET_MODE_UNIT_SIZE (new_mode), GET_MODE_SIZE (tmode)) >> && targetm.vector_mode_supported_p (n

Re: [PATCH] libstdc++: Make __gnu_debug::vector usable in constant expressions [PR109536]

On Wed, 6 Dec 2023 at 14:30, Jonathan Wakely wrote: > > Any comments on this approach? Pushed to trunk now. > > -- >8 -- > > This makes constexpr std::vector (mostly) work in Debug Mode. All safe > iterator instrumentation and checking is disabled during constant > evaluation, because it requires

[PATCH] doc: Document AArch64-specific asm operand modifiers

Hi, As it stands, GCC doesn't document any public AArch64-specific operand modifiers for use in inline asm. This patch fixes that by documenting an initial set of public AArch64-specific operand modifiers. Tested with make html and checking the output looks OK in a browser. OK for trunk? Thank

Re: [PATCH v3] AArch64: Add inline memmove expansion

Sorry, only just realised that I've never replied to this :( Wilco Dijkstra writes: > Hi Richard, > >> + rtx load[max_ops], store[max_ops]; >> >> Please either add a comment explaining why 40 is guaranteed to be >> enough, or (my preference) use: >> >> auto_vec, ...> ops; > > I've changed to us

Re: [PATCH] doc: Document AArch64-specific asm operand modifiers

Alex Coplan writes: > Hi, > > As it stands, GCC doesn't document any public AArch64-specific operand > modifiers for use in inline asm. This patch fixes that by documenting > an initial set of public AArch64-specific operand modifiers. > > Tested with make html and checking the output looks OK in

RE: [PATCH] middle-end: Fix up constant handling in emit_conditional_move [PR111260]

> -Original Message- > From: Richard Biener > Sent: Thursday, December 14, 2023 5:23 AM > To: Andrew Pinski (QUIC) > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH] middle-end: Fix up constant handling in > emit_conditional_move [PR111260] > > On Wed, Dec 13, 2023 at 5:51 PM Andrew P

Re: [PATCH] c++: Implement P2582R1, CTAD from inherited constructors

On Wed, Dec 13, 2023 at 08:48:49PM -0500, Jason Merrill wrote: > On 11/27/23 10:58, Patrick Palka wrote: > > gcc/cp/ChangeLog: > > > > * cp-tree.h (type_targs_deducible_from): Adjust return type. > > * pt.cc (alias_ctad_tweaks): Handle C++23 inherited CTAD. > > (inherited_ctad_tweaks):

RE: [PATCH 17/21]AArch64: Add implementation for vector cbranch for Advanced SIMD

> I see you've changed it from: > > + rtx cc_reg = aarch64_gen_compare_reg (code, val, const0_rtx); > + rtx cmp_rtx = gen_rtx_fmt_ee (code, DImode, cc_reg, const0_rtx); > + emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[3])); > > to: > > + emit_jump_insn (gen_cbranchdi4 (operands[0]

[patch, fortran, committed] PR112873 F2023 degree trig functions

The following has been committed per discussion in the subject PR. commit 95b70545331764c85079a1d0e1e19b605bda1456 (HEAD -> master, origin/master, origin/HEAD) Author: Jerry DeLisle Date: Wed Dec 13 19:04:50 2023 -0800 fortran: Add degree based trig functions for F2023 PR f

RE: [PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit code

> -Original Message- > From: Richard Biener > Sent: Thursday, December 14, 2023 1:13 PM > To: Tamar Christina > Cc: Richard Sandiford ; gcc-patches@gcc.gnu.org; > nd ; j...@ventanamicro.com > Subject: RE: [PATCH 9/21]middle-end: implement vectorizable_early_exit for > codegen of exit code

Re: [PATCH 1/2] emit-rtl, lra: Move lra's emit_inc to emit-rtl.cc

On 12/13/23 16:00, Alex Coplan wrote: Hi, In PR112906 we ICE because we try to use force_reg to reload an auto-increment address, but force_reg can't do this. With the aim of fixing the PR by supporting reloading arbitrary addresses in pre-RA splitters, this patch generalizes lra-constraints.

[PATCH] c++: abi_tag attribute on templates [PR109715]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? Do we want to condition this on abi_check (19)? -- >8 -- As with other declaration attributes, we need to look through TEMPLATE_DECL when looking up the abi_tag attribute. PR c++/109715 gcc/cp/ChangeLog:

[PATCH] c++: section attribute on templates [PR70435, PR88061]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- The section attribute currently has no effect on templates because the call to set_decl_section_name only happens at parse time and not also at instantiation time. This patch fixes this by propagating the se

Re: [PATCH] c++: section attribute on templates [PR70435, PR88061]

On Thu, Dec 14, 2023 at 02:17:25PM -0500, Patrick Palka wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > trunk? LGTM. > -- >8 -- > > The section attribute currently has no effect on templates because the > call to set_decl_section_name only happens at parse ti

Re: [PATCH] RISC-V: fix scalar crypto pattern

On 12/14/23 02:48, Christoph Müllner wrote: On Thu, Dec 14, 2023 at 1:40 AM Jeff Law wrote: On 12/13/23 02:03, Christoph Müllner wrote: On Wed, Dec 13, 2023 at 9:22 AM Liao Shihua wrote: In Scalar Crypto Built-In functions, some require immediate parameters, But register_operand are inco

Re: [PATCH] RISC-V: fix scalar crypto pattern

On 12/14/23 04:12, Liao Shihua wrote: Sorry, I was not aware of this patch. Since Jeff's patch was here first and also includes more tests, I propose to move forward with his patch (but I'm not a maintainer!). Therefore, I've reviewed Jeff's patch and replied to his email. FWIW: Jeff's patch

Re: [PATCH 17/21]AArch64: Add implementation for vector cbranch for Advanced SIMD

Tamar Christina writes: >> I see you've changed it from: >> >> + rtx cc_reg = aarch64_gen_compare_reg (code, val, const0_rtx); >> + rtx cmp_rtx = gen_rtx_fmt_ee (code, DImode, cc_reg, const0_rtx); >> + emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[3])); >> >> to: >> >> + emit_jump

Re: [PATCH v2] aarch64: Fix +nopredres, +nols64 and +nomops

Andrew Carlotti writes: > On Sat, Dec 09, 2023 at 07:22:49PM +, Richard Sandiford wrote: >> Andrew Carlotti writes: >> > ... >> >> This is the only use of native_detect_p, so it'd be good to remove >> the field itself. > > Done > >> > ... >> > >> > @@ -447,6 +451,13 @@ host_detect_local_cp

[PATCH] hardened: use LD_PIE_SPEC only if defined

sol2.h may define LINK_PIE_SPEC and leave LD_PIE_SPEC undefined, but gcc.cc will only provide a LD_PIE_SPEC definition if LINK_PIE_SPEC is not defined, and then it uses LD_PIE_SPEC guarded by #ifdef HAVE_LD_PIE only. Add LD_PIE_SPEC to the guard. Regstrapped on x86_64-linux-gnu; also testing on

[PATCH] strub: avoid lto inlining

The strub builtins are not suited for cross-unit inlining, they should only be inlined by the builtin expanders, if at all. While testing on sparc64, it occurred to me that, if libgcc was built with LTO enabled, lto1 might inline them, and that would likely break things. So, make sure they're c

[PATCH] strub: use opt_for_fn during ipa

Instead of global optimization levels and flags, check per-function ones. Regstrapped on x86_64-linux-gnu, also testing on sparc-solaris2.11.3. Ok to install? (sorry, Richi, I dropped the ball and failed to fix this before the monster commit) for gcc/ChangeLog * ipa-strub.cc (gsi_in

Re: [PATCH] hardened: use LD_PIE_SPEC only if defined

On Thu, Dec 14, 2023 at 04:50:49PM -0300, Alexandre Oliva wrote: > > sol2.h may define LINK_PIE_SPEC and leave LD_PIE_SPEC undefined, but > gcc.cc will only provide a LD_PIE_SPEC definition if LINK_PIE_SPEC is > not defined, and then it uses LD_PIE_SPEC guarded by #ifdef HAVE_LD_PIE > only. Add L

[PATCH #1/2] strub: sparc: omit frame in strub_leave [PR112917]

If we allow __strub_leave to allocate a frame on sparc, it will overlap with a lot of the stack range we're supposed to scrub, because of the large fixed-size outgoing args and register save area. Unfortunately, setting up the PIC register seems to prevent the frame pointer from being omitted. S

Re: [PATCH] c++: abi_tag attribute on templates [PR109715]

On 12/14/23 14:17, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? Do we want to condition this on abi_check (19)? I think we do, sadly. -- >8 -- As with other declaration attributes, we need to look through TEMPLATE_DECL when looking up

Re: [PATCH] c++: section attribute on templates [PR70435, PR88061]

On 12/14/23 14:17, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? OK. -- >8 -- The section attribute currently has no effect on templates because the call to set_decl_section_name only happens at parse time and not also at instantiation t

Re: [PATCH 5/6] Allow poly_uint64 for group_size args to vector type query routines

Richard Biener writes: > The following changes the unsigned group_size argument to a poly_uint64 > one to avoid too much special-casing in callers for VLA vectors when > passing down the effective maximum desirable vector size to vector > type query routines. The intent is to be able to pass down

Re: [V4] [C PATCH 1/4] c23: tag compatibility rules for struct and unions

On Mon, 27 Nov 2023, Martin Uecker wrote: > Note that there is an additional change in parser_xref_tag > to address the issue regarding completeness in redefinition > which affects also structs / unions. The test c23-tag-6.c > was changed accordingly. > > > c23: tag compatibility rules for stru

RE: [PATCH v4] [tree-optimization/110279] Consider FMA in get_reassociation_width

> -Original Message- > From: Richard Biener > Sent: Wednesday, December 13, 2023 5:01 PM > To: Di Zhao OS > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH v4] [tree-optimization/110279] Consider FMA in > get_reassociation_width > > On Wed, Dec 13, 2023 at 9:14 AM Di Zhao OS > wrote:

Re: [V4] [PATCH 2/4] c23: tag compatibility rules for enums

On Mon, 27 Nov 2023, Martin Uecker wrote: > + enum B : short { M = 1 } *y2e = &x2;/* { dg-warning "incompatible" > } */ This probably now needs to be dg-error because -Wincompatible-pointer-types is now an error by default. OK with that changed as needed (you may also need such a chan

[PATCH v4] c++: fix ICE with sizeof in a template [PR112869]

On Wed, Dec 13, 2023 at 03:28:38PM -0500, Jason Merrill wrote: > On 12/12/23 17:48, Marek Polacek wrote: > > On Fri, Dec 08, 2023 at 11:09:15PM -0500, Jason Merrill wrote: > > > On 12/8/23 16:15, Marek Polacek wrote: > > > > On Fri, Dec 08, 2023 at 12:09:18PM -0500, Jason Merrill wrote: > > > > > O

Re: [PATCH] i386: Fix missed APX_NDD check for shift/rotate expanders [PR 112943]

The testcase fails on darwin: +FAIL: gcc.target/i386/pr112943.c (test for excess errors) because it does not support _Decimal64. /* { dg-do compile { target { ! ia32 } } } */ should be changed to: /* { dg-do compile { target { dfp && { ! ia32 } } } } */ Thanks, FX

[PATCH] c++: fix parsing with auto(x) at block scope [PR112482]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- This is sort of like r14-5514, but at block scope. Consider struct A { A(int, int); }; void g (int a) { A bar(auto(a), 42); // not a fn decl } where we emit error: 'auto' parameter not permitted in this context

Re: [PATCH v4] c++: fix ICE with sizeof in a template [PR112869]

On 12/14/23 16:01, Marek Polacek wrote: On Wed, Dec 13, 2023 at 03:28:38PM -0500, Jason Merrill wrote: On 12/12/23 17:48, Marek Polacek wrote: On Fri, Dec 08, 2023 at 11:09:15PM -0500, Jason Merrill wrote: On 12/8/23 16:15, Marek Polacek wrote: On Fri, Dec 08, 2023 at 12:09:18PM -0500, Jason

Update 'gcc.dg/vect/vect-simd-clone-*.c' GCN 'dg-warning's (was: [PATCH] aarch64: enable mixed-types for aarch64 simdclones)

Hi! On 2023-10-16T16:03:26+0100, "Andre Vieira (lists)" wrote: > --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c > +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c > @@ -12,8 +12,13 @@ int array[N]; > > #pragma omp declare simd simdlen(4) notinbranch > #pragma omp declare simd simdlen(4

Re: [PATCH] c++: fix parsing with auto(x) at block scope [PR112482]

On 12/14/23 16:02, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? OK. -- >8 -- This is sort of like r14-5514, but at block scope. Consider struct A { A(int, int); }; void g (int a) { A bar(auto(a), 42); // not a fn decl } where we emit

Re: [PATCH] c++: abi_tag attribute on templates [PR109715]

On Thu, 14 Dec 2023, Jason Merrill wrote: > On 12/14/23 14:17, Patrick Palka wrote: > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > > trunk? Do we want to condition this on abi_check (19)? > > I think we do, sadly. Sounds good, like so? Bootstrap and regtest in p

Re: [V4] [PATCH 3/4] c23: aliasing of compatible tagged types

On Mon, 27 Nov 2023, Martin Uecker wrote: > diff --git a/gcc/c/c-tree.h b/gcc/c/c-tree.h > index a5dd9a37944..ece5b6a5d26 100644 > --- a/gcc/c/c-tree.h > +++ b/gcc/c/c-tree.h > @@ -758,6 +758,7 @@ extern tree require_complete_type (location_t, tree); > extern bool same_translation_unit_p (const_t

Re: [PATCH] Fix tests for gomp

Hi! On 2023-12-13T12:09:14+0100, Jakub Jelinek wrote: > On Wed, Dec 13, 2023 at 11:03:50AM +, Andre Vieira (lists) wrote: >> Hmm I think I understand what you are saying, but I'm not sure I agree. >> So before I enabled simdclone testing for aarch64, this test had no target >> selectors.

[PATCH #2/2] strub: sparc64: unbias the stack address [PR112917]

The stack pointer is biased by 2047 bytes on sparc64, so the range it delimits is way off. Unbias the addresses returned by __builtin_stack_address (), so that the strub builtins, inlined or not, can function correctly. I've considered introducing a new target macro, but using STACK_POINTER_OFF

[PATCH] RISC-V: Add -fno-vect-cost-model to pr112773 testcase

The testcase for pr112773 started passing after r14-6472-g8501edba91e which was before the actual fix. This patch adds -fno-vect-cost-model which prevents the testcase from passing due to the vls change. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/pr112773.c: Add

[COMMITTED] middle-end: Fix up constant handling in emit_conditional_move [PR111260]

After r14-2667-gceae1400cf24f329393e96dd9720, we force a constant to a register if it is shared with one of the other operands. The problem is used the comparison mode for the register but that could be different from the operand mode. This causes some issues on some targets. To fix it, we need to

[pushed] testsuite: move more analyzer test cases to c-c++-common (3) [PR96395]

Move a further 268 tests from gcc.dg/analyzer to c-c++-common/analyzer. Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-6564-gae034b9106fbdd. gcc/testsuite/ChangeLog: PR analyzer/96395 * c-c++-common/analyzer/analyzer-decls.h: New header.

Re: [PATCH] RISC-V: Add -fno-vect-cost-model to pr112773 testcase

LGTM juzhe.zh...@rivai.ai From: Patrick O'Neill Date: 2023-12-15 05:32 To: gcc-patches CC: rdapp.gcc; juzhe.zhong; Patrick O'Neill Subject: [PATCH] RISC-V: Add -fno-vect-cost-model to pr112773 testcase The testcase for pr112773 started passing after r14-6472-g8501edba91e which was before the a

Re: [PATCH] c++: abi_tag attribute on templates [PR109715]

On 12/14/23 16:08, Patrick Palka wrote: On Thu, 14 Dec 2023, Jason Merrill wrote: On 12/14/23 14:17, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? Do we want to condition this on abi_check (19)? I think we do, sadly. Sounds good, like

[PATCH] lower-bitint: Fix .{ADD,SUB,MUL}_OVERFLOW with _BitInt large/huge INTEGER_CST arguments [PR113003]

Hi! As shown in the testcase, .{ADD,SUB,MUL}_OVERFLOW calls are another exception to the middle/large/huge _BitInt discovery through SSA_NAMEs next to stores of INTEGER_CSTs to memory and their conversions to floating point. The calls can have normal COMPLEX_TYPE with INTEGER_TYPE elts return type

[PATCH] bitint: Introduce abi_limb_mode

Hi! Given what I saw in the aarch64/arm psABIs for BITINT_TYPE, as I said earlier I'm afraid we need to differentiate between the limb mode/precision specified in the psABIs (what is used to decide how it is actually passed, aligned or what size it has) vs. what limb mode/precision should be used

[Committed] RISC-V: Adjust test

Since middle-end patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640595.html will change vectorization code. Adapt tests for ths patch. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Adapt test. --- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr11298

Re: [PATCH 1/2] libstdc++: Atomic wait/notify ABI stabilization

I need to look at this a bit more (and not on my phone, at lunch). Ultimately, C++26 expects to add predicate waits and returning a ‘tri-state’ result isn’t something that’s been considered or likely to be approved. On Mon, Dec 11, 2023 at 12:18 PM Jonathan Wakely wrote: > CCing Tom's current ad

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