RE: [PATCH v1 1/1] gcc: config: microblaze: fix cpu version check

>>> There is a microblaze cpu version 10.0 included in versal. If the >>> minor version is only a single digit, then the version comparison >>> will fail as version 10.0 will appear as 100 compared to version >>> 6.00 or 8.30 which will calculate to values 600 and 830. >>> The issue can be seen w

Re: [PATCH] match: Fix the `popcnt(a&b) + popcnt(a|b)` patthern for types [PR111913]

On Tue, Oct 24, 2023 at 1:04 AM Andrew Pinski wrote: > > So this pattern needs a little help on the gimple side of things to know what > the type popcount should be. For most builtins, the type is the same as the > input > but popcount and others are not. And when using it with another outer > e

Re: [PATCH] Support vec_cmpmn/vcondmn for v2hf/v4hf.

On Tue, Oct 24, 2023 at 7:44 AM Hongtao Liu wrote: > > On Tue, Oct 24, 2023 at 1:23 PM Hongtao Liu wrote: > > > > On Tue, Oct 24, 2023 at 10:53 AM Hongtao Liu wrote: > > > > > > On Mon, Oct 23, 2023 at 8:35 PM Richard Biener > > > wrote: > > > > > > > > On Mon, Oct 23, 2023 at 10:48 AM liuhongt

Re: [PATCHv2] Improve factor_out_conditional_operation for conversions and constants

On Tue, Oct 24, 2023 at 8:45 AM Andrew Pinski wrote: > > In the case of a NOP conversion (precisions of the 2 types are equal), > factoring out the conversion can be done even if int_fits_type_p returns > false and even when the conversion is defined by a statement inside the > conditional. Since

Re: [PATCH] libgcc: make heap-based trampolines conditional on libc presence

On Mon, Oct 23, 2023 at 6:41 PM Sergei Trofimovich wrote: > > On Mon, 23 Oct 2023 13:54:01 +0100 > Iain Sandoe wrote: > > > hi Sergei, > > > > > On 23 Oct 2023, at 13:43, Sergei Trofimovich wrote: > > > > > > From: Sergei Trofimovich > > > > > > To build `libc` for a target one needs to build `

Re: [PATCH v3] gcc: Introduce -fhardened

On Mon, Oct 23, 2023 at 9:26 PM Marek Polacek wrote: > > On Thu, Oct 19, 2023 at 02:24:11PM +0200, Richard Biener wrote: > > On Wed, Oct 11, 2023 at 10:48 PM Marek Polacek wrote: > > > > > > On Tue, Sep 19, 2023 at 10:58:19AM -0400, Marek Polacek wrote: > > > > On Mon, Sep 18, 2023 at 08:57:39AM

[PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]

Calling vget/vset intrinsic without receiving a return value will cause a crash. Because in this case e.target is null. This patch should be backported to releases/gcc-13. PR/target 111935 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: fix bug. gcc/testsuite/Chan

Re: [ARC PATCH] Improved SImode shifts and rotates on !TARGET_BARREL_SHIFTER.

Hi Roger, Your patch doesn't introduce new regressions. However, before pushing to the mainline you need to fix some issues: 1. Please fix the trailing spaces and blocks of 8 spaces which should be replaced with tabs. You can use check_GNU_style.py script to spot them. 2. Please use capital letter

Re: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]

Ok for trunk (You can commit it to the trunk now). For GCC-13, I'd like to wait for kito's comment. Thanks. juzhe.zh...@rivai.ai From: Li Xu Date: 2023-10-24 15:29 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong Subject: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935] Ca

Re: [PATCH v9 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces

Hello Bernhard: On 23/10/23 7:40 pm, Bernhard Reutner-Fischer wrote: > On Mon, 23 Oct 2023 12:16:18 +0530 > Ajit Agarwal wrote: > >> Hello All: >> >> Addressed below review comments in the version 11 of the patch. >> Please review and please let me know if its ok for trunk. > > s/satisified/sat

Re: [PATCH v9 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces

Hello Vineet: On 24/10/23 12:02 am, Vineet Gupta wrote: > > > On 10/22/23 23:46, Ajit Agarwal wrote: >> Hello All: >> >> Addressed below review comments in the version 11 of the patch. >> Please review and please let me know if its ok for trunk. >> >> Thanks & Regards >> Ajit > > Again you are

Re: [PATCH v3] gcc: Introduce -fhardened

Hi Marek, > On 23 Oct 2023, at 20:25, Marek Polacek wrote: > > On Thu, Oct 19, 2023 at 02:24:11PM +0200, Richard Biener wrote: >> On Wed, Oct 11, 2023 at 10:48 PM Marek Polacek wrote: >>> >>> On Tue, Sep 19, 2023 at 10:58:19AM -0400, Marek Polacek wrote: On Mon, Sep 18, 2023 at 08:57:39AM

Re: Re: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]

Committed to trunk. Thanks juzhe. -- Li Xu >Ok for trunk (You can commit it to the trunk now). > >For GCC-13,  I'd like to wait for kito's comment. > >Thanks. > > >juzhe.zh...@rivai.ai > >From: Li Xu >Date: 2023-10-24 15:29 >To: gcc-patches >

[PATCH] Ignore case of header line in dg-extract-results.py

On Thu, Oct 19, 2023 at 10:48:17AM -0600, Jeff Law wrote: > On 10/18/23 03:35, Thomas Schwinge wrote: > > > > Is this (case variants) maybe something that has changed in DejaGnu at > > some point in time? (I have not checked.) > No idea :-) > Yes, it changed around 2016. > > I suggest that we ad

RE: [PATCH-1v4, expand] Enable vector mode for compare_by_pieces [PR111449]

It seems that the mail got caught elsewhere and did not send into gcc-patches mailing thread. Resending that. Thx, Haochen -Original Message- From: Jiang, Haochen Sent: Tuesday, October 24, 2023 4:43 PM To: HAO CHEN GUI ; Richard Sandiford Cc: gcc-patches Subject: RE: [PATCH-1v4, expa

OpenMP/Fortran: Group handling of 'if' clause without and with modifier (was: [committed] Partial OpenMP 4.5 fortran support)

Hi! On 2016-11-10T12:41:59+0100, Jakub Jelinek wrote: > gcc/fortran/ > * gfortran.h [...] > (struct gfc_omp_clauses): Add [...] > [...] > [...] and if_exprs fields. Etc. OK to push (after testing) the attached "OpenMP/Fortran: Group handling of 'if' clause without and

RE: [PATCH-1v4, expand] Enable vector mode for compare_by_pieces [PR111449]

Hi Haochen Gui, It seems that the commit caused lots of test case fail on x86 platforms: https://gcc.gnu.org/pipermail/gcc-regression/2023-October/078379.html https://gcc.gnu.org/pipermail/gcc-regression/2023-October/078380.html https://gcc.gnu.org/pipermail/gcc-regression/2023-October/078381.htm

Re: OpenMP/Fortran: Group handling of 'if' clause without and with modifier

CC: fortran@ for completeness. On 24.10.23 10:55, Thomas Schwinge wrote: OK to push (after testing) the attached "OpenMP/Fortran: Group handling of 'if' clause without and with modifier"? That makes an upcoming change a bit lighter. LGTM. (The patch just moves some code up (in the same functi

[Patch] OpenMP/Fortran: Handle unlisted items in 'omp allocators' + exec. 'omp allocate'

This patch assumes that EXEC_OMP_ALLOCATE/EXEC_OMP_ALLOCATORS is/will be later handled as currently done in OG13, https://github.com/gcc-mirror/gcc/blob/devel/omp/gcc-13/gcc/fortran/trans-openmp.cc Depending how we want to handle it in mainline, the patch still could make sense - or parts shoul

[PATCH V13] ree: Improve ree pass using defined abi interfaces

Hello Vineet, Jeff and Bernhard: This version 13 of the patch uses abi interfaces to remove zero and sign extension elimination. Bootstrapped and regtested on powerpc-linux-gnu. In this version (version 13) of the patch following review comments are incorporated. a) Removal of hard code zero_e

Re: [PATCH-1v4, expand] Enable vector mode for compare_by_pieces [PR111449]

OK, I will take it. Thanks Gui Haochen 在 2023/10/24 16:49, Jiang, Haochen 写道: > It seems that the mail got caught elsewhere and did not send into gcc-patches > mailing thread. Resending that. > > Thx, > Haochen > > -Original Message- > From: Jiang, Haochen > Sent: Tuesday, October 24,

Re: [PATCH v3] gcc: Introduce -fhardened

hi Marek, > On 24 Oct 2023, at 08:44, Iain Sandoe wrote: > On 23 Oct 2023, at 20:25, Marek Polacek wrote: >> >> On Thu, Oct 19, 2023 at 02:24:11PM +0200, Richard Biener wrote: >>> On Wed, Oct 11, 2023 at 10:48 PM Marek Polacek wrote: On Tue, Sep 19, 2023 at 10:58:19AM -0400, Marek P

Re: [PATCH v9 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces

On 24/10/23 1:10 pm, Ajit Agarwal wrote: > Hello Vineet: > > On 24/10/23 12:02 am, Vineet Gupta wrote: >> >> >> On 10/22/23 23:46, Ajit Agarwal wrote: >>> Hello All: >>> >>> Addressed below review comments in the version 11 of the patch. >>> Please review and please let me know if its ok for tr

Re: PATCH v6 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces.

On 19/09/23 1:57 am, Vineet Gupta wrote: > Hi Ajit, > > On 9/17/23 22:59, Ajit Agarwal wrote: >> This new version of patch 6 use improve ree pass for rs6000 target using >> defined ABI interfaces. >> Bootstrapped and regtested on power64-linux-gnu. >> >> Review comments incorporated. >> >> Tha

Re: [PATCH] Fix PR ada/111813 (Inconsistent limit in Ada.Calendar.Formatting)

This change is OK, thank you. > The description of the second Value function (returning Duration) (ARM > 9.6.1(87) > doesn't place any limitation on the Elapsed_Time parameter's value, beyond > "Constraint_Error is raised if the string is not formatted as described for > Image, or > the funct

[PATCH] aarch64: Avoid bogus atomics match

The non-LSE pattern aarch64_atomic_exchange comes before the LSE pattern aarch64_atomic_exchange_lse. From a recog perspective, the only difference between the patterns is that the non-LSE one clobbers CC and needs a scratch. However, combine and RTL-SSA can both add clobbers to make a pattern ma

[pushed] aarch64: Define TARGET_INSN_COST

This patch adds a bare-bones TARGET_INSN_COST. See the comment in the patch for the rationale. This change is needed to avoid a regression with a later change. Tested on aarch64-linux-gnu & pushed. Richard gcc/ * config/aarch64/aarch64.cc (aarch64_insn_cost): New function. (TA

[pushed] i386: Fix unprotected REGNO in aeswidekl_operation

I hit an ICE in aeswidekl_operation while testing the late-combine pass on x86. The predicate tested REGNO without first testing REG_P. Tested on x86_64-linux-gnu & pushed as obvious. Richard gcc/ * config/i386/predicates.md (aeswidekl_operation): Protect REGNO check with REG_P

[PATCH] i386: Avoid paradoxical subreg dests in vector zero_extend

For the V2HI -> V2SI zero extension in: typedef unsigned short v2hi __attribute__((vector_size(4))); typedef unsigned int v2si __attribute__((vector_size(8))); v2si f (v2hi x) { return (v2si) {x[0], x[1]}; } ix86_expand_sse_extend would generate: (set (reg:V2HI 102) (const_vecto

[PATCH] i386: Fix undefined masks in vpopcnt tests

The files changed in this patch had tests for masked and unmasked popcnt. However, the mask inputs to the masked forms were undefined, and would be set to zero by init_regs. Any combine-like pass that ran after init_regs could then fold the masked forms into the unmasked ones. I saw this while t

[PATCH] recog/reload: Remove old UNARY_P operand support

reload and constrain_operands had some old code to look through unary operators. E.g. an operand could be (sign_extend (reg X)), and the constraints would match the reg rather than the sign_extend. This was previously used by the MIPS port. But relying on it was a recurring source of problems, s

[PATCH] recog: Fix propagation into ASM_OPERANDS

An inline asm with multiple output operands is represented as a parallel set in which the SET_SRCs are the same (shared) ASM_OPERANDS. insn_propgation didn't account for this, and instead propagated into each ASM_OPERANDS individually. This meant that it could apply a substitution X->Y to Y itself

Re: [PATCH] i386: Avoid paradoxical subreg dests in vector zero_extend

On Tue, Oct 24, 2023 at 12:08 PM Richard Sandiford wrote: > > For the V2HI -> V2SI zero extension in: > > typedef unsigned short v2hi __attribute__((vector_size(4))); > typedef unsigned int v2si __attribute__((vector_size(8))); > v2si f (v2hi x) { return (v2si) {x[0], x[1]}; } > > ix86_expan

[PING] [PATCH 1/3] [GCC] arm: vld1q_types_x2 ACLE intrinsics

Ping From: ezra.sito...@arm.com Sent: Friday, October 6, 2023 10:49 AM To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw; Kyrylo Tkachov Subject: [PATCH 1/3] [GCC] arm: vld1q_types_x2 ACLE intrinsics From: Ezra Sitorus This patch is part of a series of p

[PATCH 0/4] rtl-ssa: Some small, obvious fixes

This series contains some small fixes to RTL-SSA. Tested on aarch64-linux-gnu & x86_64-linux-gnu, pushed as obvious. Richard Sandiford (4): rtl-ssa: Fix null deref in first_any_insn_use rtl-ssa: Fix handling of deleted insns rtl-ssa: Don't insert after insns that can throw rtl-ssa: Avoid

[PATCH 1/4] rtl-ssa: Fix null deref in first_any_insn_use

first_any_insn_use implicitly (but contrary to its documentation) assumed that there was at least one use. gcc/ * rtl-ssa/member-fns.inl (first_any_insn_use): Handle null m_first_use. --- gcc/rtl-ssa/member-fns.inl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 4/4] rtl-ssa: Avoid creating duplicated phis

If make_uses_available was called twice for the same use, we could end up trying to create duplicate definitions for the same extended live range. gcc/ * rtl-ssa/blocks.cc (function_info::create_degenerate_phi): Check whether the requested phi already exists. --- gcc/rtl-ssa/block

[PATCH 3/4] rtl-ssa: Don't insert after insns that can throw

rtl_ssa::can_insert_after didn't handle insns that can throw. Fixing that avoids a regression with a later patch. gcc/ * rtl-ssa.h: Include cfgbuild.h. * rtl-ssa/movement.h (can_insert_after): Replace is_jump with the more comprehensive control_flow_insn_p. --- gcc/rtl-ssa

[PATCH 2/4] rtl-ssa: Fix handling of deleted insns

RTL-SSA queues up some invasive changes for later. But sometimes the insns involved in those changes can be deleted by later optimisations, making the queued change unnecessary. This patch checks for that case. gcc/ * rtl-ssa/changes.cc (function_info::perform_pending_updates): Check

Re: [PATCH 1/2] testsuite: Add and use thread_fence effective-target

Ping? Le lun. 2 oct. 2023, 10:24, Christophe Lyon a écrit : > ping? > > On Sun, 10 Sept 2023 at 21:31, Christophe Lyon > wrote: > >> Some targets like arm-eabi with newlib and default settings rely on >> __sync_synchronize() to ensure synchronization. Newlib does not >> implement it by default

Re: [PATCH] testsuite: Fix gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c

Ping? Le lun. 2 oct. 2023, 10:23, Christophe Lyon a écrit : > ping? maybe this counts as obvious? > > > On Thu, 14 Sept 2023 at 11:13, Christophe Lyon > wrote: > >> ping? >> >> On Fri, 8 Sept 2023 at 10:43, Christophe Lyon >> wrote: >> >>> The test was declaring 'int *carry;' and wrote to '*ca

[PATCH 1/6] rtl-ssa: Ensure global registers are live on exit

RTL-SSA mostly relies on DF for block-level register liveness information, including artificial uses and defs at the beginning and end of blocks. But one case was missing. DF does not add artificial uses of global registers to the beginning or end of a block. Instead it marks them as used within

[PATCH 0/6] rtl-ssa: Various fixes needed for the late-combine pass

Testing the late-combine pass showed a depressing number of bugs in areas of RTL-SSA that hadn't been used much until now. Most of them relate to doing things after RA. Tested on aarch64-linux-gnu & x86_64-linux-gnu. OK to install? Richard Richard Sandiford (6): rtl-ssa: Ensure global registe

[PATCH 3/6] rtl-ssa: Fix ICE when deleting memory clobbers

Sometimes an optimisation can remove a clobber of scratch registers or scratch memory. We then need to update the DU chains to reflect the removed clobber. For registers this isn't a problem. Clobbers of registers are just momentary blips in the register's lifetime. They act as a barrier for mo

[PATCH 6/6] rtl-ssa: Handle call clobbers in more places

In order to save (a lot of) memory, RTL-SSA avoids creating individual clobber records for every call-clobbered register. It instead maintains a list & splay tree of calls in an EBB, grouped by ABI. This patch takes these call clobbers into account in a couple more routines. I don't think this wi

[PATCH 4/6] rtl-ssa: Handle artifical uses of deleted defs

If an optimisation removes the last real use of a definition, there can still be artificial uses left. This patch removes those uses too. These artificial uses exist because RTL-SSA is only an SSA-like view of the existing RTL IL, rather than a native SSA representation. It effectively treats RTL

[PATCH 2/6] rtl-ssa: Create REG_UNUSED notes after all pending changes

Unlike REG_DEAD notes, REG_UNUSED notes need to be kept free of false positives by all passes. function_info::change_insns does this by removing all REG_UNUSED notes, and then using add_reg_unused_notes to add notes back (or create new ones) where appropriate. The problem was that it called add_r

Re: [PATCH v25 25/33] libstdc++: Optimize std::is_function compilation performance

On Tue, 24 Oct 2023 at 03:16, Ken Matsui wrote: > This patch optimizes the compilation performance of std::is_function > by dispatching to the new __is_function built-in trait. > > libstdc++-v3/ChangeLog: > > * include/std/type_traits (is_function): Use __is_function > built-in tr

Re: [PATCH] ifcvt/vect: Emit COND_ADD for conditional scalar reduction.

Richard Biener writes: > On Thu, 19 Oct 2023, Robin Dapp wrote: > >> Ugh, I didn't push yet because with a rebased trunk I am >> seeing different behavior for some riscv testcases. >> >> A reduction is not recognized because there is yet another >> "double use" occurrence in check_reduction_path.

Re: [PATCH] i386: Fix undefined masks in vpopcnt tests

On Tue, Oct 24, 2023 at 6:10 PM Richard Sandiford wrote: > > The files changed in this patch had tests for masked and unmasked > popcnt. However, the mask inputs to the masked forms were undefined, > and would be set to zero by init_regs. Any combine-like pass that > ran after init_regs could th

[PATCH GCC13 backport] Avoid compile time hog on vect_peel_nonlinear_iv_init for nonlinear induction vec_step_op_mul when iteration count is too big.

This is the backport patch for releases/gcc-13 branch, the original patch for main trunk is at [1]. The only difference between this backport patch and [1] is GCC13 doesn't support auto_mpz, So this patch manually use mpz_init/mpz_clear. [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-October

Re: [x86 PATCH] Fine tune STV register conversion costs for -Os.

On Mon, Oct 23, 2023 at 4:47 PM Roger Sayle wrote: > > > The eagle-eyed may have spotted that my recent testcases for DImode shifts > on x86_64 included -mno-stv in the dg-options. This is because the > Scalar-To-Vector (STV) pass currently transforms these shifts to use > SSE vector operations,

[PATCH] gcov-io.h: fix comment regarding length of records

The length of gcov records is stored as a signed 32-bit number of bytes. Ok? diff --git a/gcc/gcov-io.h b/gcc/gcov-io.h index bfe4439d02d..e6f33e32652 100644 --- a/gcc/gcov-io.h +++ b/gcc/gcov-io.h @@ -101,7 +101,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see Rec

[committed] arc: Remove mpy_dest_reg_operand predicate

The mpy_dest_reg_operand is just a wrapper for register_operand. Remove it. gcc/ * config/arc/arc.md (mulsi3_700): Update pattern. (mulsi3_v2): Likewise. * config/arc/predicates.md (mpy_dest_reg_operand): Remove it. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/a

Re: Re: [PATCH V5] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721]

Hi, Richard. Assertion failed at this IR: _427 = _425 & _426; _429 = present$0_16(D) != 0; _430 = _425 & _429; _409 = _430 | _445; _410 = _409 | _449; _411 = .LOOP_VECTORIZED (3, 6); if (_411 != 0) goto ; [100.00%] else goto ; [100.00%] [local count: 3280550]: [lo

Re: Re: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]

Ok for gcc 13 but just wait one more week to make sure everything is fine as gcc convention :) Li Xu 於 2023年10月24日 週二，15:49寫道： > Committed to trunk. Thanks juzhe. > > > -- > > > > Li Xu > > > > >Ok for trunk (You can commit it to the trunk now). > > > > > > > > > >For GCC-13, I'd lik

Re: [PATCH] testsuite: Fix gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c

On 08/09/2023 09:43, Christophe Lyon via Gcc-patches wrote: The test was declaring 'int *carry;' and wrote to '*carry' without initializing 'carry' first, leading to an attempt to write at address zero, and a crash. Fix by declaring 'int carry;' and passing '&carrry' instead of 'carry' as par

[RFC PATCH] Detecting lifetime-dse issues via Valgrind

From: Daniil Frolov PR 66487 is asking to provide sanitizer-like detection for C++ object lifetime violations that are worked around with -fno-lifetime-dse in Firefox, LLVM, OpenJade. The discussion in the PR was centered around extending MSan, but MSan was not ported to GCC (and requires rebuil

Re: [PATCH v1 1/1] gcc: config: microblaze: fix cpu version check

On 10/24/23 00:01, Frager, Neal wrote: There is a microblaze cpu version 10.0 included in versal. If the minor version is only a single digit, then the version comparison will fail as version 10.0 will appear as 100 compared to version 6.00 or 8.30 which will calculate to values 600 and 830. The

Re: [PING][PATCH 2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

Sorry for the slow review. I had a look at the arm bits too, to get some context for the target-independent bits. Stamatis Markianos-Wright via Gcc-patches writes: > [...] > diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h > index 77e76336e94..74186930f0b 100644 > --- a/gcc

Re: [PATCH] RISC-V: Add AVL propagation PASS for RVV auto-vectorization

> +using namespace rtl_ssa; > +using namespace riscv_vector; > + > +/* The AVL propagation instructions and corresponding preferred AVL. > + It will be updated during the analysis. */ > +static hash_map *avlprops; Maybe put into member data of pass_avlprop? > + > +const pass_data pass_data_avl

[PATCH] testsuite: Fix _BitInt in gcc.misc-tests/godump-1.c

Currently _BitInt is only supported on x86_64 which means that for other targets all tests fail with e.g. gcc.misc-tests/godump-1.c:237:1: sorry, unimplemented: '_BitInt(32)' is not supported on this target 237 | _BitInt(32) b32_v; | ^~~ Instead of requiring _BitInt support for godum

[PATCH] config, aarch64: Use a more compatible sed invocation.

Although this came up initially when working on the Darwin Arm64 port, it also breaks cross-compilers on platforms with non-GNU sed. Tested on x86_64-darwin X aarch64-linux-gnu, aarch64-darwin, aarch64-linux-gnu and x86_64-linux-gnu. OK for master? thanks, Iain --- 8< --- Currently, the sed com

Re: [PATCH] Fortran: Fix incompatible types between INTEGER(8) and TYPE(c_ptr)

Hi PA, hello all, First, I hesitate to review/approve a patch I am involved in; Thus, I would like if someone could have a second look. Regarding the patch itself: On 20.10.23 16:02, Paul-Antoine Arraswrote: Hi all, The attached patch fixes a bug that causes valid OpenMP declare variant dire

[PATCH] c++: error with bit-fields and scoped enums [PR111895]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- Here we issue a bogus error: invalid operands of types 'unsigned char:2' and 'int' to binary 'operator!=' when casting a bit-field of scoped enum type to bool. In build_static_cast_1, perform_direct_initialization_if_possible r

Re: [PATCH] c++: cp_stabilize_reference and non-dep exprs [PR111919]

On 10/23/23 19:49, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- After the removal of NON_DEPENDENT_EXPR, cp_stabilize_reference which used to just exit early for NON_DEPENDENT_EXPR is now more prone to passing a weird templated tr

[PATCH] c++: build_new_1 and non-dep array size [PR111929]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look like the right approach? -- >8 -- This PR is another instance of NON_DEPENDENT_EXPR having acted as an "analysis barrier" for middle-end routines, and now that it's gone we may end up passing weird templated trees (that have a gene

[PATCH V14 4/4] ree: Improve ree pass using defined abi interfaces

Hello Vineet, Jeff and Bernhard: This version 14 of the patch uses abi interfaces to remove zero and sign extension elimination. This fixes aarch64 regressions failures with aggressive CSE. Bootstrapped and regtested on powerpc-linux-gnu. In this version (version 14) of the patch following revi

Re: [PATCH 1/6] rtl-ssa: Ensure global registers are live on exit

On 10/24/23 04:50, Richard Sandiford wrote: RTL-SSA mostly relies on DF for block-level register liveness information, including artificial uses and defs at the beginning and end of blocks. But one case was missing. DF does not add artificial uses of global registers to the beginning or end

Re: [PATCH 2/6] rtl-ssa: Create REG_UNUSED notes after all pending changes

On 10/24/23 04:50, Richard Sandiford wrote: Unlike REG_DEAD notes, REG_UNUSED notes need to be kept free of false positives by all passes. function_info::change_insns does this by removing all REG_UNUSED notes, and then using add_reg_unused_notes to add notes back (or create new ones) where a

Re: [PATCH 3/6] rtl-ssa: Fix ICE when deleting memory clobbers

On 10/24/23 04:50, Richard Sandiford wrote: Sometimes an optimisation can remove a clobber of scratch registers or scratch memory. We then need to update the DU chains to reflect the removed clobber. For registers this isn't a problem. Clobbers of registers are just momentary blips in the r

Re: [PATCH 4/6] rtl-ssa: Handle artifical uses of deleted defs

On 10/24/23 04:50, Richard Sandiford wrote: If an optimisation removes the last real use of a definition, there can still be artificial uses left. This patch removes those uses too. These artificial uses exist because RTL-SSA is only an SSA-like view of the existing RTL IL, rather than a nat

[PATCH v2] AArch64: Improve immediate generation

v2: Use check-function-bodies in tests Further improve immediate generation by adding support for 2-instruction MOV/EOR bitmask immediates. This reduces the number of 3/4-instruction immediates in SPECCPU2017 by ~2%. Passes regress, OK for commit? gcc/ChangeLog: * config/aarch64/aarch64

Re: [PATCH 5/6] rtl-ssa: Calculate dominance frontiers for the exit block

On 10/24/23 04:50, Richard Sandiford wrote: The exit block can have multiple predecessors, for example if the function calls __builtin_eh_return. We might then need PHI nodes for values that are live on exit. RTL-SSA uses the normal dominance frontiers approach for calculating where PHI node

Re: [PATCH 6/6] rtl-ssa: Handle call clobbers in more places

On 10/24/23 04:50, Richard Sandiford wrote: In order to save (a lot of) memory, RTL-SSA avoids creating individual clobber records for every call-clobbered register. It instead maintains a list & splay tree of calls in an EBB, grouped by ABI. This patch takes these call clobbers into account

[PATCH 0/3] rtl-ssa: Various extensions for the late-combine pass

This series adds some RTL-SSA enhancements that are needed by the late-combine pass. Tested on aarch64-linux-gnu & x86_64-linux-gnu. OK to install? Richard Richard Sandiford (3): rtl-ssa: Use frequency-weighted insn costs rtl-ssa: Extend make_uses_available rtl-ssa: Add new helper functio

[PATCH 1/3] rtl-ssa: Use frequency-weighted insn costs

rtl_ssa::changes_are_worthwhile used the standard approach of summing up the individual costs of the old and new sequences to see which one is better overall. But when optimising for speed and changing instructions in multiple blocks, it seems better to weight the cost of each instruction by its e

[PATCH 2/3] rtl-ssa: Extend make_uses_available

The first in-tree use of RTL-SSA was fwprop, and one of the goals was to make the fwprop rewrite preserve the old behaviour as far as possible. The switch to RTL-SSA was supposed to be a pure infrastructure change. So RTL-SSA has various FIXMEs for things that were artifically limited to faciliat

[PATCH 3/3] rtl-ssa: Add new helper functions

This patch adds some RTL-SSA helper functions. They will be used by the upcoming late-combine pass. The patch contains the first non-template out-of-line function declared in movement.h, so it adds a movement.cc. I realise it seems a bit over-the-top to have a file with just one function, but it

Re: [PATCH] recog/reload: Remove old UNARY_P operand support

On 10/24/23 04:14, Richard Sandiford wrote: reload and constrain_operands had some old code to look through unary operators. E.g. an operand could be (sign_extend (reg X)), and the constraints would match the reg rather than the sign_extend. > This was previously used by the MIPS port. But r

Re: [PATCH] gcov-io.h: fix comment regarding length of records

On 10/24/23 06:41, Jose E. Marchesi wrote: The length of gcov records is stored as a signed 32-bit number of bytes. Ok? OK. jeff

Re: [PATCH] testsuite: Fix _BitInt in gcc.misc-tests/godump-1.c

On 10/24/23 09:26, Stefan Schulze Frielinghaus wrote: Currently _BitInt is only supported on x86_64 which means that for other targets all tests fail with e.g. gcc.misc-tests/godump-1.c:237:1: sorry, unimplemented: '_BitInt(32)' is not supported on this target 237 | _BitInt(32) b32_v;

Re: [PATCH V14 4/4] ree: Improve ree pass using defined abi interfaces

On 10/24/23 10:03, Ajit Agarwal wrote: Hello Vineet, Jeff and Bernhard: This version 14 of the patch uses abi interfaces to remove zero and sign extension elimination. This fixes aarch64 regressions failures with aggressive CSE. Once again, this information belong between the two "---" lin

Re: [PATCH 1/3] rtl-ssa: Use frequency-weighted insn costs

On 10/24/23 11:58, Richard Sandiford wrote: rtl_ssa::changes_are_worthwhile used the standard approach of summing up the individual costs of the old and new sequences to see which one is better overall. But when optimising for speed and changing instructions in multiple blocks, it seems bette

Re: [PATCH 2/3] rtl-ssa: Extend make_uses_available

On 10/24/23 11:58, Richard Sandiford wrote: The first in-tree use of RTL-SSA was fwprop, and one of the goals was to make the fwprop rewrite preserve the old behaviour as far as possible. The switch to RTL-SSA was supposed to be a pure infrastructure change. So RTL-SSA has various FIXMEs for

Re: [PATCH 3/3] rtl-ssa: Add new helper functions

On 10/24/23 11:58, Richard Sandiford wrote: This patch adds some RTL-SSA helper functions. They will be used by the upcoming late-combine pass. The patch contains the first non-template out-of-line function declared in movement.h, so it adds a movement.cc. I realise it seems a bit over-the-

[PATCH] Add a late-combine pass [PR106594]

This patch adds a combine pass that runs late in the pipeline. There are two instances: one between combine and split1, and one after postreload. The pass currently has a single objective: remove definitions by substituting into all uses. The pre-RA version tries to restrict itself to cases that

Re: [PATCH v3] gcc: Introduce -fhardened

On Tue, Oct 24, 2023 at 10:34:22AM +0100, Iain Sandoe wrote: > hi Marek, > > > On 24 Oct 2023, at 08:44, Iain Sandoe wrote: > > On 23 Oct 2023, at 20:25, Marek Polacek wrote: > >> > >> On Thu, Oct 19, 2023 at 02:24:11PM +0200, Richard Biener wrote: > >>> On Wed, Oct 11, 2023 at 10:48 PM Marek P

Re: [PATCH v3] gcc: Introduce -fhardened

On Tue, Oct 24, 2023 at 09:22:25AM +0200, Richard Biener wrote: > On Mon, Oct 23, 2023 at 9:26 PM Marek Polacek wrote: > > > > On Thu, Oct 19, 2023 at 02:24:11PM +0200, Richard Biener wrote: > > > On Wed, Oct 11, 2023 at 10:48 PM Marek Polacek wrote: > > > > > > > > On Tue, Sep 19, 2023 at 10:58:

Re: [PATCH] gcov-io.h: fix comment regarding length of records

> On 10/24/23 06:41, Jose E. Marchesi wrote: >> The length of gcov records is stored as a signed 32-bit number of >> bytes. >> Ok? > OK. Pushed. Thanks.

Re: [PATCH v3] gcc: Introduce -fhardened

> On 24 Oct 2023, at 20:03, Marek Polacek wrote: > > On Tue, Oct 24, 2023 at 10:34:22AM +0100, Iain Sandoe wrote: >> hi Marek, >> >>> On 24 Oct 2023, at 08:44, Iain Sandoe wrote: >>> On 23 Oct 2023, at 20:25, Marek Polacek wrote: On Thu, Oct 19, 2023 at 02:24:11PM +0200, Richard

[PATCH] Fortran/OpenMP: event handle in task detach cannot be a coarray [PR104131]

Dear all, the attached simple patch adds a forgotten check that an event handle cannot be a coarray. This case appears to have been overlooked in the original fix for this PR. I intend to commit as obvious within 24h unless there are comments. Thanks, Harald From 2b5ed32cacfe84dc4df74b4dccf16a

Re: [PATCH] ifcvt/vect: Emit COND_ADD for conditional scalar reduction.

Changed as suggested. The difference to v5 is thus: + if (cond_fn_p) + { + gcall *call = dyn_cast (use_stmt); + unsigned else_pos + = internal_fn_else_index (internal_fn (op.code)); + + for (unsigned int j = 0; j < gimple_call_nu

Re: [PATCH] Fortran/OpenMP: event handle in task detach cannot be a coarray [PR104131]

On 24 October 2023 21:25:01 CEST, Harald Anlauf wrote: >Dear all, > >the attached simple patch adds a forgotten check that an event handle >cannot be a coarray. This case appears to have been overlooked in the >original fix for this PR. > >I intend to commit as obvious within 24h unless there are

Re: [PATCH] libstdc++ Add cstdarg to freestanding

On Sun, 22 Oct 2023 at 21:06, Arsen Arsenović wrote: > > "Paul M. Bendixen" writes: > > > Updated patch, added the requested files, hopefully wrote the commit > better. > > LGTM. Jonathan? > Yup, looks good. I've pushed it to trunk with a tweaked changelog entry. I'll backport it to gcc-13 soo

Re: HELP: Will the reordering happen? Re: [V3][PATCH 0/3] New attribute "counted_by" to annotate bounds for C99 FAM(PR108896)

Hi, Sid, Really appreciate for your example and detailed explanation. Very helpful. I think that this example is an excellent example to show (almost) all the issues we need to consider. I slightly modified this example to make it to be compilable and run-able, as following: (but I still canno

Re: [PATCH v9 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces

On 24 October 2023 09:36:22 CEST, Ajit Agarwal wrote: >Hello Bernhard: > >On 23/10/23 7:40 pm, Bernhard Reutner-Fischer wrote: >> On Mon, 23 Oct 2023 12:16:18 +0530 >> Ajit Agarwal wrote: >> >>> Hello All: >>> >>> Addressed below review comments in the version 11 of the patch. >>> Please review

Re: HELP: Will the reordering happen? Re: [V3][PATCH 0/3] New attribute "counted_by" to annotate bounds for C99 FAM(PR108896)

Am Dienstag, dem 24.10.2023 um 20:30 + schrieb Qing Zhao: > Hi, Sid, > > Really appreciate for your example and detailed explanation. Very helpful. > I think that this example is an excellent example to show (almost) all the > issues we need to consider. > > I slightly modified this example

Re: [PATCH] Fortran/OpenMP: event handle in task detach cannot be a coarray [PR104131]

Dear all, Tobias argued in the PR that the testcase should actually be valid. Therefore withdrawing the patch. Sorry for expecting this to be a low-hanging fruit... Harald On 10/24/23 22:23, rep.dot@gmail.com wrote: On 24 October 2023 21:25:01 CEST, Harald Anlauf wrote: Dear all, the a

Re: [PATCH] c++: error with bit-fields and scoped enums [PR111895]

On 10/24/23 12:18, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- Here we issue a bogus error: invalid operands of types 'unsigned char:2' and 'int' to binary 'operator!=' when casting a bit-field of scoped enum type to bool. In build_static_cast_1, p

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