[PATCH][RFC] tree-optimization/92335 - Improve sinking heuristics for vectorization

The following delays sinking of loads within the same innermost loop when it was unconditional before. That's a not uncommon issue preventing vectorization when masked loads are not available. Bootstrapped and tested on x86_64-unknown-linux-gnu. I have a followup patch improving sinking that wit

[PATCH V2] VECT: Support CALL vectorization for COND_LEN_*

Hi, Richard and Richi. Base on the suggestions from Richard: https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625396.html This patch choose (1) approach that Richard provided, meaning: RVV implements cond_* optabs as expanders. RVV therefore supports both IFN_COND_ADD and IFN_COND_LEN_ADD.

[PATCH] RISC-V: Support CALL conditional autovec patterns

This patch is depending on middle-end support: https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625696.html Consider this following case: void foo (float * __restrict a, float * __restrict b, int * __restrict cond, int n) { for (int i = 0; i < n; i++) if (cond[i]) a[i] = b[i] + a[i

RE: [PATCH] RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u]

Committed, thanks Kito and Juzhe. Pan From: Kito Cheng Sent: Friday, July 28, 2023 2:46 PM To: 钟居哲 Cc: Li Xu ; gcc-patches ; palmer ; Li, Pan2 Subject: Re: [PATCH] RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u] I didn't checked with rvv intrinsic spec, but I assume this is found dur

[COMMITTED] ada: Improve defense against illegal code in check for infinite loops

From: Piotr Trojanek Fix crash occurring when attribute System'To_Address is used without a WITH clause for package System. gcc/ada/ * sem_warn.adb (Check_Infinite_Loop_Warning): Don't look at the type of actual parameter when it has no type at all, e.g. because the entire

[COMMITTED] ada: Allow calls to Number_Formals when no formals are present

From: Piotr Trojanek It is much simpler and safer for the routine Number_Formals to accept subprogram entities that have no formals. gcc/ada/ * einfo-utils.adb (Number_Formals): Change types in body. * einfo-utils.ads (Number_Formals): Change type in spec. * einfo.ads (N

[COMMITTED] ada: Small refactor

From: Viljar Indus gcc/ada/ * exp_util.adb (Find_Optional_Prim_Op): use "No" instead of "= Empty" Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/exp_util.adb | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/ada/exp_util.adb b/gcc/ada/exp_ut

[COMMITTED] ada: Add guard for detection of class-wide precondition subprograms

From: Piotr Trojanek When skipping check on subprograms built for class-wide preconditions we must deal with the current scope not being a subprogram, e.g. it could be a declare-block. gcc/ada/ * sem_res.adb (Resolve_Actuals): Add guard for the call to Class_Preconditions_Subpro

[COMMITTED] ada: Elide the copy in extended returns for nonlimited by-reference types

From: Eric Botcazou gcc/ada/ * gcc-interface/trans.cc (gnat_to_gnu): Restrict previous change to the case where the simple return statement has got no storage pool. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/gcc-interface/trans.cc | 7 --- 1 file chang

[COMMITTED] ada: Fix typo in comment of Ada.Exceptions.Save_Occurrence

From: Piotr Trojanek Minor typo in comment. gcc/ada/ * libgnat/a-except.ads (Save_Occurrence): Fix typo. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/libgnat/a-except.ads | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ada/libgnat/a-except.a

[COMMITTED] ada: Add missing SCO generation for quantified expressions in object decl

From: Léo Creuse This change corrects the Has_Decision predicate in par_sco.adb to properly consider predicates of quantified expressions as decisions. gcc/ada/ * par_sco.adb (Has_Decision): Consider that quantified expressions contain decisions. Tested on x86_64-pc-linux-gnu,

[COMMITTED] ada: Fix race condition in protected entry call

From: Ronan Desplanques This patch only affects the single-entry implementation of protected objects. Before this patch, there was a race condition where a task that called an entry could put itself to sleep right after another task had executed the entry as a proxy and signalled the not-yet-wai

[COMMITTED] ada: Emit enums rather than defines for various constants

From: Tom Tromey This patch changes xsnamest and gen_il-gen to emit various constants as enums rather than a sequence of preprocessor defines. This enables better debugging and somewhat better type safety. gcc/ada/ * fe.h (Convention): Now inline function. * gen_il-gen.adb (Put

[COMMITTED] ada: Add an assert in Posix Interrupt_Wait

From: Clément Chigot All functions but Interrupt_Wait in s-inmaop__posix are checking the result of their syscalls with an assert. However, any return code of sigwait different than 0 means that something went wrong for it. >From sigwait man: > RETURN VALUE > On success, sigwait() returns 0

[COMMITTED] ada: Leave detection of missing return in functions to GNATprove

From: Piotr Trojanek GNAT has a heuristic to warn about missing return statements in functions. This warning was escalated to errors when operating in GNATprove mode and SPARK_Mode was On. However, this heuristic was imprecise and caused spurious errors. Also, it was applied after the Push_Scope/

[COMMITTED] ada: Fix unsupported dispatching constructor call

From: Javier Miranda Add dummy build-in-place parameters when a BIP function does not require the BIP parameters but it is a dispatching operation that inherited them. gcc/ada/ * einfo-utils.adb (Underlying_Type): Protect recursion call against non-available attribute Etype.

[COMMITTED] ada: Fix memory explosion on aggregate of nested packed array type

From: Eric Botcazou It occurs at compile time on an aggregate of a 2-dimensional packed array type whose component type is itself a packed array, because the compiler is trying to pack the intermediate aggregate and ends up rewriting a bunch of subcomponents. This optimization was originally dev

[COMMITTED] ada: Add support for binding to a specific network interface controller.

From: Pascal Obry gcc/ada/ * s-oscons-tmplt.c: Add support for SO_BINDTODEVICE constant. * libgnat/g-socket.ads (Set_Socket_Option): Handle SO_BINDTODEVICE option. (Get_Socket_Option): Handle SO_BINDTODEVICE option. * libgnat/g-socket.adb: Likewise. (Get_

Loop-split improvements, part 2

Hi, this patch fixes profile update in the first case of loop splitting. The pass still gives up on very basic testcases: __attribute__ ((noinline,noipa)) void test1 (int n) { if (n <= 0 || n > 10) return; for (int i = 0; i <= n; i++) { if (i < n) do_something ();

Re: [PATCH] Optimize vec_splats of vec_extract for V2DI/V2DF (PR target/99293)

Hi Mike, on 2023/7/11 03:50, Michael Meissner wrote: > This patch optimizes cases like: > > vector double v1, v2; > /* ... */ > v2 = vec_splats (vec_extract (v1, 0); /* or */ > v2 = vec_splats (vec_extract (v1, 1); > > Previously: > > vector long long > sp

Re: [PATCH 0/5] GCC _BitInt support [PR102989]

On Thu, Jul 27, 2023 at 06:41:44PM +, Joseph Myers wrote: > On Thu, 27 Jul 2023, Jakub Jelinek via Gcc-patches wrote: > > > - _BitInt(N) bit-fields aren't supported yet (the patch rejects them); I'd > > like > > to enable those incrementally, but don't really see details on how such > > b

Re: [PATCH, rs6000] Skip redundant vector extract if the element is first element of dword0 [PR110429]

Hi Haochen, on 2023/7/5 11:22, HAO CHEN GUI wrote: > Hi, > This patch skips redundant vector extract insn to be generated when > the extracted element is the first element of dword0 and the destination "The first element" is confusing, it's easy to be misunderstood as element 0, but in fact the

Re: [PATCH v8] RISC-V: Support CALL for RVV floating-point dynamic rounding

Hi Pan, thanks for your patience and your work. Apart from my general doubt whether mode-changing intrinsics are a good idea, I don't have other remarks that need fixing. What I mentioned before: - Handling of asms wouldn't be a huge change. It can be done in a follow-up patch of course but

New template for 'gcc' made available

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Re: [PATCH] AArch64: Do not increase the vect reduction latency by multiplying count [PR110625]

Hi Richard, I've updated the patch and tested on aarch64. Is it OK? --- The new costs should only count reduction latency by multiplying count for single_defuse_cycle. For other situations, this will increase the reduction latency a lot and miss vectorization opportunities. Tested on aarch64-

[PATCH] gcse: Extract reg pressure handling into separate file.

Hi, this patch extracts the hoist-pressure handling from gcse and puts it into a separate file so it can be used by other passes in the future. No functional change and I also abstained from c++ifying the code. The naming with the regpressure_ prefix might be a bit clunky for now and I'm open to a

Re: [PATCH v2] c-family: Implement pragma_lex () for preprocess-only mode

On Thu, Jul 27, 2023 at 06:18:33PM -0700, Jason Merrill wrote: > On 7/27/23 18:59, Lewis Hyatt wrote: > > In order to support processing #pragma in preprocess-only mode (-E or > > -save-temps for gcc/g++), we need a way to obtain the #pragma tokens from > > libcpp. In full compilation modes, this i

[PATCH] gimple-fold: Handle _BitInt in __builtin_clear_padding [PR102989]

Hi! The comments about _Atomic _BitInt made me figure out I forgot (although earlier was planning to do that) to implement __builtin_clear_padding support for _BitInt. The following patch (incremental to the _BitInt series) does that. 2023-07-28 Jakub Jelinek PR c/102989 * gi

Re: _BitInt vs. _Atomic

On Thu, Jul 27, 2023 at 07:06:03PM +, Joseph Myers wrote: > I think there should be tests for _Atomic _BitInt types. Hopefully atomic > compound assignment just works via the logic for compare-and-exchange > loops, but does e.g. atomic_fetch_add work with _Atomic _BitInt types? So, there ar

[PATCH v2] RISC-V: convert the mulh with 0 to mov 0 to the reg.

From: Yanzhang Wang This patch will optimize the below mulh example, vint32m1_t shortcut_for_riscv_vmulh_case_0(vint32m1_t v1, size_t vl) { return __riscv_vmulh_vx_i32m1(v1, 0, vl); } from mulh pattern vsetvli zero, a2, e32, m1, ta, ma vmulh.vx v24, v24, zero vs1r.vv24, 0(a0) to belo

[patch] libgomp: cuda.h and omp_target_memcpy_rect cleanup (was: [patch] OpenMP: Call cuMemcpy2D/cuMemcpy3D for nvptx for omp_target_memcpy_rect)

Hi Thomas, thanks for proof reading and the suggestions! – Do have comments to the attached patch? * * * Crossref: For further optimizations, see also https://gcc.gnu.org/PR101581 — [OpenMP] omp_target_memcpy – support inter-device memcpy https://gcc.gnu.org/PR110813 — [OpenMP] omp_target_memc

Re: [PATCH] gcc-ar: Handle response files properly [PR77576]

ping On Fri, 14 Jul 2023 at 09:05, Costas Argyris wrote: > Pinging to try and get this bug in gcc-ar fixed. > > Note that the patch posted as an attachment in > > https://gcc.gnu.org/pipermail/gcc-patches/2023-July/623400.html > > is exactly the same as the patch embedded in > > https://gcc.gnu.

Re: [PATCH v2] RISC-V: convert the mulh with 0 to mov 0 to the reg.

於 2023年7月28日 週五 19:50 寫道： > From: Yanzhang Wang > > This patch will optimize the below mulh example, > > vint32m1_t shortcut_for_riscv_vmulh_case_0(vint32m1_t v1, size_t vl) { > return __riscv_vmulh_vx_i32m1(v1, 0, vl); > } > > from mulh pattern > > vsetvli zero, a2, e32, m1, ta, ma > vmulh.

RE: [PATCH v2] RISC-V: convert the mulh with 0 to mov 0 to the reg.

This is a draft patch. I would like to explain it's hard to make the simplify generic and ask for some help. There're 2 categories we need to optimize. - The op in optab such as div / 1. - The unspec operation such as mulh * 0, (vadc+vmadc) + 0. Especially for the unspec operation, I found we ne

New French PO file for 'gcc' (version 13.2.0)

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New Ukrainian PO file for 'gcc' (version 13.2.0)

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Re: [PATCH v2] RISC-V: convert the mulh with 0 to mov 0 to the reg.

> This is a draft patch. I would like to explain it's hard to make the > simplify generic and ask for some help. > > There're 2 categories we need to optimize. > > - The op in optab such as div / 1. > - The unspec operation such as mulh * 0, (vadc+vmadc) + 0. > > Especially for the unspec operat

RE: [PATCH v8] RISC-V: Support CALL for RVV floating-point dynamic rounding

Great! Thanks Robin for so many useful comments, as well as the thought-provoking discussion with different insights. I believe such kind of interactively discussion will empower all of us, and leading us to do the right things. Back to this PATCH, I try to only do one thing at a time and I tota

Re: Loop-split improvements, part 2

On Fri, Jul 28, 2023 at 9:58 AM Jan Hubicka via Gcc-patches wrote: > > Hi, > this patch fixes profile update in the first case of loop splitting. > The pass still gives up on very basic testcases: > > __attribute__ ((noinline,noipa)) > void test1 (int n) > { > if (n <= 0 || n > 10) > ret

New Croatian PO file for 'gcc' (version 13.2.0)

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Re: Loop-split improvements, part 2

> On Fri, Jul 28, 2023 at 9:58 AM Jan Hubicka via Gcc-patches > wrote: > > > > Hi, > > this patch fixes profile update in the first case of loop splitting. > > The pass still gives up on very basic testcases: > > > > __attribute__ ((noinline,noipa)) > > void test1 (int n) > > { > > if (n <= 0 ||

Loop-split improvements, part 3

Hi, This patch extends tree-ssa-loop-split to understand test of the form if (i==0) and if (i!=0) which triggers only during the first iteration. Naturally we should also be able to trigger last iteration or split into 3 cases if the test indeed can fire in the middle of the loop. Last iteratio

Re: [RFC] [v2] Extend fold_vec_perm to handle VLA vectors

On Tue, 25 Jul 2023 at 18:25, Richard Sandiford wrote: > > Hi, > > Thanks for the rework and sorry for the slow review. Hi Richard, Thanks for the suggestions! Please find my responses inline below. > > Prathamesh Kulkarni writes: > > Hi Richard, > > This is reworking of patch to extend fold_vec

[PATCH 1/4] openmp: Fix loop transformation tests

libgomp/ChangeLog: * testsuite/libgomp.fortran/loop-transforms/tile-2.f90: Add reduction clause. * testsuite/libgomp.fortran/loop-transforms/unroll-1.f90: Initialize var. * testsuite/libgomp.fortran/loop-transforms/unroll-simd-1.f90: Add reduction and initializat

[PATCH 0/4] openmp: loop transformation fixes

Hi, the following patches contain some fixes from the devel/omp/gcc-13 branch to the patches that implement the OpenMP 5.1. loop transformation directives which I have posted in March 2023. Frederik Frederik Harwath (4): openmp: Fix loop transformation tests openmp: Fix initialization for '

[PATCH 4/4] openmp: Fix number of iterations computation for "omp unroll full"

gcc/ChangeLog: * omp-transform-loops.cc (gomp_for_number_of_iterations): Always compute "final - init" and do not take absolute value. Identify non-iterating and infinite loops for constant init, final, step values for better diagnostic messages, consistent

[PATCH 3/4] openmp: Fix diagnostic message for "omp unroll"

gcc/ChangeLog: * omp-transform-loops.cc (print_optimized_unroll_partial_msg): Output "omp unroll partial" instead of "omp unroll auto". (optimize_transformation_clauses): Likewise. libgomp/ChangeLog: * testsuite/libgomp.fortran/loop-transforms/unroll-6.f90: Adjust

[PATCH 2/4] openmp: Fix initialization for 'unroll full'

The index variable initialization for the 'omp unroll' directive with 'full' clause got lost and the testsuite did not catch it. Add the initialization and add -Wall to some tests to detect uninitialized variable uses and other potential problems in the code generation. gcc/ChangeLog: *

Re: Loop-split improvements, part 3

On Fri, Jul 28, 2023 at 2:57 PM Jan Hubicka via Gcc-patches wrote: > > Hi, > This patch extends tree-ssa-loop-split to understand test of the form > if (i==0) > and > if (i!=0) > which triggers only during the first iteration. Naturally we should > also be able to trigger last iteration or spli

Re: Loop-split improvements, part 3

> On Fri, Jul 28, 2023 at 2:57 PM Jan Hubicka via Gcc-patches > wrote: > > > > Hi, > > This patch extends tree-ssa-loop-split to understand test of the form > > if (i==0) > > and > > if (i!=0) > > which triggers only during the first iteration. Naturally we should > > also be able to trigger la

Re: _BitInt vs. _Atomic

> On Thu, Jul 27, 2023 at 07:06:03PM +, Joseph Myers wrote: > > I think there should be tests for _Atomic _BitInt types. Hopefully atomic > > compound assignment just works via the logic for compare-and-exchange > > loops, but does e.g. atomic_fetch_add work with _Atomic _BitInt types? >

Re: _BitInt vs. _Atomic

Am Freitag, dem 28.07.2023 um 16:03 +0200 schrieb Martin Uecker: > > > On Thu, Jul 27, 2023 at 07:06:03PM +, Joseph Myers wrote: > > > I think there should be tests for _Atomic _BitInt types. Hopefully > > > atomic > > > compound assignment just works via the logic for compare-and-exchange

Re: _BitInt vs. _Atomic

On Fri, Jul 28, 2023 at 04:03:39PM +0200, Martin Uecker wrote: > > On Thu, Jul 27, 2023 at 07:06:03PM +, Joseph Myers wrote: > > > I think there should be tests for _Atomic _BitInt types. Hopefully > > > atomic > > > compound assignment just works via the logic for compare-and-exchange > >

Re: _BitInt vs. _Atomic

Am Freitag, dem 28.07.2023 um 16:26 +0200 schrieb Jakub Jelinek: > On Fri, Jul 28, 2023 at 04:03:39PM +0200, Martin Uecker wrote: > > > On Thu, Jul 27, 2023 at 07:06:03PM +, Joseph Myers wrote: > > > > I think there should be tests for _Atomic _BitInt types. Hopefully > > > > atomic > > > >

[PATCH] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

GCC maintainers: The following patch cleans up the definition for the __builtin_altivec_vcmpnet. The current implementation implies that the built-in is only supported on Power 9 since it is defined under the Power 9 stanza. However the built-in has no ISA restrictions as stated in the Power Vec

Re: [PATCH 0/5] Recognize Zicond extension

On 7/28/23 00:34, Xiao Zeng wrote: Does that work for you? I'm going to look at 3/5 today pretty closely.  Exposing zicond to movcc is something we had implemented inside Ventana and I want to compare/contrast your work with ours. What a coincidence! Zicond is a direct descendant of xvent

Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

On 7/25/23 11:55, Andreas Schwab wrote: On Jul 19 2023, Xiao Zeng wrote: diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 38d8eb2fcf5..7e6b24bd232 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, mac

Re: _BitInt vs. _Atomic

On Fri, Jul 28, 2023 at 04:53:30PM +0200, Martin Uecker wrote: > > The thing is that user doesn't have much control over those > > padding bits, so whether _Atomic operations on long double (when it is 80 > > bit and stores from hw actually store 10 bytes rather than 12 or 16), or > > _BitInt(37) o

Re: [PATCH] c++: devirtualization of array destruction [PR110057]

On 7/26/23 20:06, Ng YongXiang wrote: Hi Jason, I've made the following changes. 1. Add pr83054-2.C 2. Move the devirt tests to tree-ssa. 3. Remove dg do run for devirt tests 4. Add // PR c++/110057 5. Generate commit message with git gcc-commit-mklog 6. Check commit format with git gcc-verify

Re: [PATCH v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks.

On 7/27/23 06:02, Robin Dapp wrote: LGTM, I just found this patch still on the list, I mostly tested with qemu, so I don't think that is a problem before, but I realize it's a problem when we run on a real board that does not support those extensions. I think we can skip this one as I needed

Re: _BitInt vs. _Atomic

Am Freitag, dem 28.07.2023 um 17:10 +0200 schrieb Jakub Jelinek: > On Fri, Jul 28, 2023 at 04:53:30PM +0200, Martin Uecker wrote: > > > The thing is that user doesn't have much control over those > > > padding bits, so whether _Atomic operations on long double (when it is 80 > > > bit and stores fr

[RFC WIP PATCH] _BitInt bit-field support [PR102989]

On Fri, Jul 28, 2023 at 11:05:42AM +0200, Jakub Jelinek via Gcc-patches wrote: > On Thu, Jul 27, 2023 at 06:41:44PM +, Joseph Myers wrote: > > On Thu, 27 Jul 2023, Jakub Jelinek via Gcc-patches wrote: > > > > > - _BitInt(N) bit-fields aren't supported yet (the patch rejects them); > > > I'd l

[Committed] RISC-V: Specify -mabi in rv64 autovec testcase

On rv32 targets, this patch fixes: FAIL: gcc.target/riscv/rvv/autovec/madd-split2-1.c -O3 -ftree-vectorize (test for excess errors) cc1: error: ABI requires '-march=rv32' gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/madd-split2-1.c: Add -mabi=lp64d to dg-options. Sig

Re: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative

Thanks! Here's the comitted patch: https://inbox.sourceware.org/gcc-patches/20230728163758.377962-1-patr...@rivosinc.com/T/#u On 7/27/23 15:11, juzhe.zhong wrote: LGTM.Thanks. You can go ahead commit it. Replied Message FromPatrick O'Neill Date07/2

Re: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative

No worries! I'm glad it was an easy fix ;) On 7/27/23 19:55, Demin Han wrote: Sorry for not consider rv32 config. The fix is OK. If convenient, please commit it. On 2023/7/28 4:46, Patrick O'Neill wrote: The newly added testcase fails on rv32 targets with this message: FAIL: gcc.target/riscv/r

Re: [PATCH] AArch64: Do not increase the vect reduction latency by multiplying count [PR110625]

Sorry for the slow response. Hao Liu OS writes: >> Ah, thanks. In that case, Hao, I think we can avoid the ICE by changing: >> >> if ((kind == scalar_stmt || kind == vector_stmt || kind == vec_to_scalar) >> && vect_is_reduction (stmt_info)) >> >> to: >> >> if ((kind == scalar_stmt || k

New German PO file for 'gcc' (version 13.2.0)

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Re: [PATCH 0/5] GCC _BitInt support [PR102989]

On Fri, 28 Jul 2023, Jakub Jelinek via Gcc-patches wrote: > I had a brief look at libbid and am totally unimpressed. > Seems we don't implement {,unsigned} __int128 <-> _Decimal{32,64,128} > conversions at all (we emit calls to __bid_* functions which don't exist), That's bug 65833. > the librar

Re: [PATCH] Fortran: do not pass hidden character length for TYPE(*) dummy [PR110825]

On Thu, Jul 27, 2023 at 09:39:53PM +0200, Harald Anlauf via Fortran wrote: > Dear all, > > when passing a character actual argument to an assumed-type dummy > (TYPE(*)), we should not pass the character length for that argument, > as otherwise other hidden arguments that are passed as part of the

Re: _BitInt vs. _Atomic

On Fri, 28 Jul 2023, Jakub Jelinek via Gcc-patches wrote: > The C++ way of dealing with this is using __builtin_clear_padding, > done on atomic stores/updates of the atomic memory (padding is cleared > if any on the value to be stored, or on the expected and desired values). > > I don't know enou

Re: [RFC WIP PATCH] _BitInt bit-field support [PR102989]

On Fri, 28 Jul 2023, Jakub Jelinek via Gcc-patches wrote: > But I ran into a compiler divergence on _Generic with bit-field expressions. > My understanding is that _Generic controlling expression undergoes array > to pointer and function to pointer conversions, but not integral promotions > (other

[COMMITTED] bpf: disable tail call optimization in BPF targets

clang disables tail call optimizations in BPF targets. Do the same in GCC. gcc/ChangeLog: * config/bpf/bpf.cc (bpf_option_override): Disable tail-call optimizations in BPF target. --- gcc/config/bpf/bpf.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/config/bpf/bpf

[PATCH v2] SARIF and -ftime-report's output [PR109361]

On Fri, 2023-07-28 at 08:00 +0200, Richard Biener wrote: > On Fri, Jul 28, 2023 at 12:23 AM David Malcolm via Gcc-patches > wrote: > > > > On Tue, 2023-04-11 at 08:43 +, Richard Biener wrote: > > > On Tue, 4 Apr 2023, David Malcolm wrote: > > > > > > > Richi, Jakub: I can probably self-appro

Re: [PATCH RESEND] c: add -Wmissing-variable-declarations [PR65213]

On Tue, 18 Jul 2023, Hamza Mahfooz wrote: > Resolves: > PR c/65213 - Extend -Wmissing-declarations to variables [i.e. add > -Wmissing-variable-declarations] > > gcc/c-family/ChangeLog: > > PR c/65213 > * c.opt (-Wmissing-variable-declarations): New option. > > gcc/c/ChangeLog: > >

[COMMITTED] PR tree-optimization/110205 -Fix some warnings

This patch simply fixes the code up a little to remove potential warnings. Bootstrapped on x86_64-pc-linux-gnu with no regressions. Pushed. Andrew From 7905c071c35070fff3397b1e24f140c128c08e64 Mon Sep 17 00:00:00 2001 From: Andrew MacLeod Date: Mon, 10 Jul 2023 13:58:22 -0400 Subject: [PATCH 1

[COMMITTED] Add a merge_range to ssa_cache and use it.

This adds some tweaks to the ssa-range cache. 1)   Adds a new merge_range which works like set_range, except if there is already a value, the two values are merged via intersection and stored.   THis avpoids having to check if there is a value, load it, intersect it then store that in the clie

[COMMITTED] Remove value_query, push into sub&fold class.

When we first introduced range_query, we provided a base class for constants rather than range queries.  Then inherioted from that and modified the value queries for a range-specific engine. .   At the time, we figured there would be other consumers of the value_query class. When all the dust

Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

On 7/19/23 04:11, Xiao Zeng wrote: + else if (TARGET_ZICOND + && (code == EQ || code == NE) + && GET_MODE_CLASS (mode) == MODE_INT) +{ + need_eq_ne_p = true; + /* 0 + imm */ + if (GET_CODE (cons) == CONST_INT && cons == const0_rtx + && GET_COD

Re: [PATCH] gcc-ar: Handle response files properly [PR77576]

This patch is OK. -- Joseph S. Myers jos...@codesourcery.com

Re: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative

On 7/28/23 10:42, Patrick O'Neill wrote: No worries! I'm glad it was an easy fix ;) Note there's an effort underway via RISE to have some official RISC-V continuous testing for the compiler tools in place in the very near future (before Sept 1). We're starting with a limited POC, so my thi

Re: [PATCH v3 0/4] diagnostics: libcpp: Overhaul locations for _Pragma tokens

On Fri, 2023-07-21 at 19:08 -0400, Lewis Hyatt wrote: > Hello- > > This is an update to the v2 patch series last sent in January: > https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609473.html > > While I did not receive any feedback on the v2 patches yet, they did > need some > rebasing on

Re: [PATCH v3 1/4] diagnostics: libcpp: Add LC_GEN linemaps to support in-memory buffers

On Fri, 2023-07-21 at 19:08 -0400, Lewis Hyatt wrote: > Add a new linemap reason LC_GEN which enables encoding the location > of data > that was generated during compilation and does not appear in any > source file. > There could be many use cases, such as, for instance, referring to > the content

Re: [PATCH v2] RISC-V: convert the mulh with 0 to mov 0 to the reg.

On 7/28/23 06:31, Robin Dapp via Gcc-patches wrote: This is a draft patch. I would like to explain it's hard to make the simplify generic and ask for some help. There're 2 categories we need to optimize. - The op in optab such as div / 1. - The unspec operation such as mulh * 0, (vadc+vmadc)

[r14-2834 Regression] FAIL: gcc.target/i386/pr87007-5.c scan-assembler-times vxorps[^\n\r]*xmm[0-9] 1 on Linux/x86_64

On Linux/x86_64, b9d7140c80bd3c7355b8291bb46f0895dcd8c3cb is the first bad commit commit b9d7140c80bd3c7355b8291bb46f0895dcd8c3cb Author: Jan Hubicka Date: Fri Jul 28 09:16:09 2023 +0200 loop-split improvements, part 1 caused FAIL: gcc.target/i386/pr87007-4.c scan-assembler-times vxorps[

Re: [PATCH v2] c-family: Implement pragma_lex () for preprocess-only mode

On 7/28/23 07:14, Lewis Hyatt wrote: On Thu, Jul 27, 2023 at 06:18:33PM -0700, Jason Merrill wrote: On 7/27/23 18:59, Lewis Hyatt wrote: In order to support processing #pragma in preprocess-only mode (-E or -save-temps for gcc/g++), we need a way to obtain the #pragma tokens from libcpp. In ful

Fix profile update after loop versioning in vectorizer

Hi, Vectorizer while loop versioning produces a versioned loop guarded with two conditionals of the form if (cond1) goto scalar_loop else goto next_bb next_bb: if (cond2) godo scalar_loop else goto vector_loop It wants the combined test to be prob (whch is set to likely) a