On 9 June 2023 19:18:45 CEST, Mike Stump via Gcc-patches
wrote:
> simulation ports. Maybe a 20-100x speedup? If you want to go this way I'd
> say do it in python at the bottom as it would be nice to switch over to
> python in the next 5-20 years and away from tcl.
Yes, i guess we have all pon
PR analyzer/110112 notes that -fanalyzer is extremely slow on a source
file with large read-only static arrays, repeatedly building the
same compound_svalue representing the full initializer, and repeatedly
building svalues representing parts of the the full initialiazer.
This patch adds caches fo
Ok. Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-06-09 23:09
To: 钟居哲; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc; pan2.li
Subject: Re: [PATCH V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS
On 6/9/23 08:58, 钟居哲 wrote:
>>> I'd probably adjust the name a
From: Juzhe-Zhong
Address comments from Jeff.
This patch is to rework Phase 5 && Phase 6 of VSETVL PASS since Phase 5 &&
Phase 6
are quite messy and cause some bugs discovered by my downstream
auto-vectorization
test-generator.
Before this patch.
Phase 5 is cleanup_insns is the function remo
On 5/29/23 04:51, Jin Ma wrote:
Unrecog insns (such as CLOBBER, USE) does not represent real instructions,
but in the
process of pipeline optimization, they will wait for transmission in ready list
like
other insns, without considering resource conflicts and cycles. This results in
a
mul
+ (VNx16QI "TARGET_MIN_VLEN <= 128")
+ (VNx32QI "TARGET_MIN_VLEN <= 256")
+ (VNx64QI "TARGET_MIN_VLEN >= 64 && TARGET_MIN_VLEN <= 512")
+ (VNx128QI "TARGET_MIN_VLEN >= 128 && TARGET_MIN_VLEN <= 1024")
This not correct, we always use VNx16QI as LMUL = m1 for min_vlen >= 128.
Requirement of TARG
On Fri, Jun 9, 2023 at 10:54 AM Patrick Palka wrote:
>
> On Sun, 2 Apr 2023, Ken Matsui via Gcc-patches wrote:
>
> > This patch gets std::is_function to dispatch to new built-in trait
> > __is_function.
>
> For std::is_function and other predicate-like type traits, I think we also
> want to make t
Committed with bootstrap and regression test passed, thanks all.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Richard Sandiford via Gcc-patches
Sent: Saturday, June 10, 2023 1:44 AM
To: juzhe.zh...@rivai.ai
Cc: rguenther ; gcc-patches
Subject: Re: [PATCH V6] VECT: Add SELECT_V
From: Pan Li
This patch would like to add more tests for RVV FP16 vreinterpret, aka
vfloat16*_t <==> v{u}int16*_t.
There we allow FP16 vreinterpret in ZVFHMIN consider we have vle FP16 already.
It doesn't break anything in SPEC as there is no such vreinterpret insn.
>From the user's perspective
With all the operators unified under range_operator, I can now start
moving them into a unified table rather than have them spread around in
various type tables.
This patch creates a range_table for the unified operations, and has
checks to ensure that if the operator comes from the unified ta
Unify the NE_EXPR opcode
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
From cb409a3b3367109944ff332899ec401dc60f678c Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Fri, 9 Jun 2023 13:25:49 -0400
Subject: [PATCH 03/31] Unify NE_EXPR range operator
Move the decla
Unify the LT_EXPR opcode
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
From f7c1366a89edf1ffdd9c495cff544358f2ff395e Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Fri, 9 Jun 2023 13:29:15 -0400
Subject: [PATCH 04/31] Unify LT_EXPR range operator
Move the decla
Unify the EQ_EXPR opcode
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
From 684959c5c058c2368e65c4c308a2cb3e3912782e Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Fri, 9 Jun 2023 13:18:39 -0400
Subject: [PATCH 02/31] Unify EQ_EXPR range operator
Move the decla
This unifies the identity operation, which is used by SSA_NAME,
PAREN_EXPR, OBJ_TYPE_REF and REAL_CST.
REAL_CST is using it incorrectly, but preserves current functionality.
There will not be an SSA_NAME in the op1 position, so there is no point
in having an op1_range routine. That will be c
THis patch move the CONST operator into the mixed header. It also sets
REAL_CST to use this instead, as it has no op1_range routines.
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
From 35a580f09eaceda5b0dd370b1e39fe05ba0a154f Mon Sep 17 00:00:00 2001
From: Andrew M
Unify GE_EXPR the range operator
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
From 364b936b8d82e86c73b2b964d4c8a2c16dcbedf8 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Fri, 9 Jun 2023 13:33:33 -0400
Subject: [PATCH 07/31] Unify GE_EXPR range operator
Move t
Unify the LE_EXPR opcode.
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
From 9de70a61ca83d50c35f73eafaaa7276d8f0ad211 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Fri, 9 Jun 2023 13:30:56 -0400
Subject: [PATCH 05/31] Unify LE_EXPR range operator
Move the decl
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
From ee46a15733524103a9eda433df5dc44cdc055d73 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Fri, 9 Jun 2023 13:39:54 -0400
Subject: [PATCH 10/31] Unify operator_cast range operator
Move the declaration of the class
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
Unify GT_EXPR the range operator
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
From e5a4bb7c12d00926e0c7bbf0c77dd1be8f23a39a Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Fri, 9 Jun 2023 13:32:25 -0400
Subject: [PATCH 06/31] Unify GT_EXPR range operator
Move
From: Juzhe-Zhong
Consider this following example:
void vec_add(int32_t *restrict c, int32_t *restrict a, int32_t *restrict b,
int N) {
for (long i = 0; i < N; i++) {
c[i] = a[i] + b[i];
}
}
After this patch:
vec_add:
ble a3,zero,.L5
.L3:
vsetvli a5,a3,e3
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
From cc4eaf6f1e1958f920007d4cc7cafb635b5dda64 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod
Date: Fri, 9 Jun 2023 13:41:28 -0400
Subject: [PATCH 11/31] Unify PLUS_EXPR range operator
Move the declaration of the class to t
This is the final shared integer/float opcode.
This patch also removes the floating point table and all references to it.
Bootstrap on x86_64-pc-linux-gnu and pass all regressions. Pushed.
Andrew
LGTM :)
On Sat, Jun 10, 2023 at 7:59 AM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to add more tests for RVV FP16 vreinterpret, aka
>
> vfloat16*_t <==> v{u}int16*_t.
>
> There we allow FP16 vreinterpret in ZVFHMIN consider we have vle FP16 already.
> It doesn't bre
LGTM, thanks for this
On Sat, Jun 10, 2023 at 8:42 AM wrote:
>
> From: Juzhe-Zhong
>
> Consider this following example:
> void vec_add(int32_t *restrict c, int32_t *restrict a, int32_t *restrict b,
> int N) {
> for (long i = 0; i < N; i++) {
> c[i] = a[i] + b[i];
> }
> }
Committed, thanks Kito.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Saturday, June 10, 2023 11:03 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; pal...@rivosinc.com;
rdapp@gmail.com; jeffreya...@gmail.com
S
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Saturday, June 10, 2023 11:03 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; rdapp@gmail.com;
jeffreya...@gmail.com; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Add test cases for RVV FP1
Thank you for your consideration. (Or is that phrase only used negatively?)
> From: Jonathan Wakely
> Date: Fri, 9 Jun 2023 21:40:15 +0100
> test01, test02, test03 and test04 should run almost instantly. On my system
> they take about 5 microseconds each. So I don't think splitting those up
> w
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