[PATCH] Var-Tracking: Leverage pointer_mux for decl_or_value

From: Pan Li The decl_or_value is defined as void * before this PATCH. It will take care of both the tree_node and rtx_def. Unfortunately, given a void pointer cannot tell the input is tree_node or rtx_def. Then we have some implicit structure layout requirement similar as below. Or we will touc

RE: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit

Filed the PATCH with var-tracking only as below, please help to review. Thanks! https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617973.html Pan -Original Message- From: Gcc-patches On Behalf Of Li, Pan2 via Gcc-patches Sent: Wednesday, May 10, 2023 1:09 PM To: Richard Biener ; Richa

Re: [PATCH] libffi: fix handling of homogeneous float128 structs [PR109447]

On Mai 09 2023, Peter Bergner via Gcc-patches wrote: > On 5/9/23 3:50 PM, Andreas Schwab wrote: >> On Mai 09 2023, Peter Bergner via Gcc-patches wrote: >> >>> It's almost as if the top level build machinery >>> adds a LD_LIBRARY_PATH=... >> >> See how the toplevel Makefile sets LD_LIBRARY_PATH (

Re: [PATCH 2/2] aarch64: Improve register allocation for lane instructions

Richard Biener writes: > On Wed, May 10, 2023 at 12:05 AM Richard Sandiford via Gcc-patches > wrote: >> >> Andrew Pinski writes: >> > On Tue, May 9, 2023 at 11:02 AM Richard Sandiford via Gcc-patches >> > wrote: >> >> >> >> REG_ALLOC_ORDER is much less important than it used to be, but it >> >

Testsuite: Add 'torture-init-done', and use it to conditionalize implicit 'torture-init' (was: Testsuite: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS' usage (was: Let each

Hi Christophe! On 2023-05-09T21:14:07+0200, Christophe Lyon wrote: > On Tue, 9 May 2023 at 17:17, Christophe Lyon > wrote: >> On Tue, 9 May 2023 at 11:00, Thomas Schwinge >> wrote: >>> On 2023-05-09T09:32:55+0200, Christophe Lyon >>> wrote: >>> > On Wed, 3 May 2023 at 13:47, Richard Biener via

Re: [PATCH] Var-Tracking: Leverage pointer_mux for decl_or_value

On Wed, 10 May 2023, pan2...@intel.com wrote: > From: Pan Li > > The decl_or_value is defined as void * before this PATCH. It will take > care of both the tree_node and rtx_def. Unfortunately, given a void > pointer cannot tell the input is tree_node or rtx_def. > > Then we have some implicit s

Re: [PATCH] Var-Tracking: Leverage pointer_mux for decl_or_value

Richard Biener writes: > On Wed, 10 May 2023, pan2...@intel.com wrote: > >> From: Pan Li >> >> The decl_or_value is defined as void * before this PATCH. It will take >> care of both the tree_node and rtx_def. Unfortunately, given a void >> pointer cannot tell the input is tree_node or rtx_def. >

Re: [PATCH] Var-Tracking: Leverage pointer_mux for decl_or_value

On Wed, May 10, 2023 at 03:17:58PM +0800, Pan Li via Gcc-patches wrote: > gcc/ChangeLog: > > * var-tracking.cc (DECL_OR_VALUE_OR_DEFAULT): New macro for > clean code. ChangeLog formatting shouldn't have spaces after the initial tab. Furthermore, the entry doesn't describe what chang

Re: Re: [PATCH V2] RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT

Thanks, although I still have concern about that we should consider check on movmisalign with STRICT_ALIGNMENT, but I am ok with this for now, we can always fix that if got future issues. committed to trunk On Tue, May 9, 2023 at 11:22 PM 钟居哲 wrote: > > No, I don't think so. Some testcases the r

Re: [PATCH] RISC-V: Fix dead loop for user vsetvli intrinsic avl checking [PR109773]

Thanks, pushed to trunk. On Tue, May 9, 2023 at 10:20 AM wrote: > > From: Juzhe-Zhong > > This patch is fix dead loop in vsetvl intrinsic avl checking. > > vsetvli->get_def () has vsetvli->get_def () has vsetvli. > Then it will keep looping in the vsetvli avl checking which is a dead loop. >

Re: [PATCH] Fixes and workarounds for warnings during autoprofiledbootstrap build

Hello, On Wed, May 10 2023, Eugene Rozenfeld via Gcc-patches wrote: > autoprofiledbootstrap build produces new warnings since inlining decisions > are different from other builds. This patch contains fixes and workarounds > for those warnings. > > Tested on x86_64-pc-linux-gnu. > > gcc/ChangeLog:

Re: [PATCH] _Hashtable implementation cleanup

On Wed, 10 May 2023 at 05:59, François Dumont via Libstdc++ < libstd...@gcc.gnu.org> wrote: > Hi > > Rather than providing a series of patches for _Hashtable I prefer to > submit them one by one. It will maximize the chances to have some of > them in gcc 14. > > I'm starting with this simple patch

Re: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0.

Committed, thanks for catching this issue :) On Wed, May 10, 2023 at 12:08 PM juzhe.zh...@rivai.ai wrote: > > LGTM. Let's wait for kito's feedback. > Thanks :) > > > > juzhe.zh...@rivai.ai > > From: Li Xu > Date: 2023-05-10 12:02 > To: gcc-patches > CC: kito.cheng; palmer; juzhe.zhong; Li Xu > Su

Re: [PATCH] vect: Missed opportunity to use [SU]ABD

Oluwatamilore Adebayo writes: > From 0b5f469171c340ef61a48a31877d495bb77bd35f Mon Sep 17 00:00:00 2001 > From: oluade01 > Date: Fri, 14 Apr 2023 10:24:43 +0100 > Subject: [PATCH 1/4] Missed opportunity to use [SU]ABD > > This adds a recognition pattern for the non-widening > absolute difference (

[PATCH] x86: Add a new option -mdaz-ftz to enable FTZ and DAZ flags in MXCSR.

> The quoted patch shows -shared in context and you didn't post a > backport version > to look at. But yes, we shouldn't change -shared behavior on a > branch, even less so make it > inconsistent between targets. Here's the patch. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for

Re: [PATCH] xtensa: Make full transition to LRA

Hi Suwa-san, On Mon, May 8, 2023 at 6:38 AM Takayuki 'January June' Suwa wrote: > > gcc/ChangeLog: > > * config/xtensa/constraints.md (R, T, U): > Change define_constraint to define_memory_constraint. > * config/xtensa/xtensa.cc > (xtensa_lra_p, TARGET_LRA_P): Remo

Re: [PATCH 3/3] Remove widen_plus/minus_expr tree codes

On 03/05/2023 13:29, Richard Biener wrote: On Fri, 28 Apr 2023, Andre Vieira (lists) wrote: This is a rebase of Joel's previous patch. This patch removes the old widen plus/minus tree codes which have been replaced by internal functions. I guess that's obvious then. I wonder what we do t

Re: [PATCH] i386: Honour -mdirect-extern-access when calling __fentry__

On Tue, May 9, 2023 at 10:58 AM Ard Biesheuvel wrote: > > The small and medium PIC code models generate profiling calls that > always load the address of __fentry__() via the GOT, even if > -mdirect-extern-access is in effect. > > This deviates from the behavior with respect to other external > re

Re: Re: [PATCH 1/2] [RISC-V] disable shrink-wrap-separate if zcmp enabled.

On 2023-05-08 17:20  Kito Cheng wrote: > >-msave-restore is a different story; it's only enabled when the user >requests, but `-march` describes the capability of the target >architecture, not specify the preference of performance or size, which >should be determined by -O1~-O3/-Ofast or -Os/-Oz.

Re: Re: [PATCH 2/2] [RISC-V] support cm.push cm.pop cm.popret in zcmp

On 2023-05-08 10:48  Kito Cheng wrote: > >diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md >new file mode 100644 >index 000..1c2f390269e >--- /dev/null >+++ b/gcc/config/riscv/zc.md >@@ -0,0 +1,55 @@ >... >+(define_insn "gpr_multi_pop" >+  [(unspec_volatile [(match_operand 0 "c

[PATCH][committed] aarch64: PR target/99195 annotate simple narrowing patterns for vec-concat-zero

Hi all, This patch cleans up some almost-duplicate patterns for the XTN, SQXTN, UQXTN instructions. Using the attributes we can remove the BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN cases, as well as the intrinsic expanders that select between the two. Tests are also added. Thankfully the diffstat

[PATCH][committed] aarch64: Simplify QSHRN expanders and patterns

Hi all, This patch deletes the explicit BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN patterns for the QSHRN instructions in favour of annotating a single one with . This allows simplification of the expander too. Tests are added to ensure that we still optimise away the concat-with-zero use case. Bo

[PATCH] ipa-prop: Fix ipa_get_callee_param_type for calls with argument type mismatches

Hi! The PR contains a testcase where the Fortran FE creates FUNCTION_TYPE which doesn't really match the passed in arguments (FUNCTION_TYPE has 5 arguments, call has 6). Now, I think that is a Fortran FE bug that should be fixed there, but I think with function pointers one can create something s

Re: [PATCH] vect: Missed opportunity to use [SU]ABD

On Wed, May 10, 2023 at 11:01 AM Richard Sandiford wrote: > > Oluwatamilore Adebayo writes: > > From 0b5f469171c340ef61a48a31877d495bb77bd35f Mon Sep 17 00:00:00 2001 > > From: oluade01 > > Date: Fri, 14 Apr 2023 10:24:43 +0100 > > Subject: [PATCH 1/4] Missed opportunity to use [SU]ABD > > > > T

Re: [PATCH] vect: Missed opportunity to use [SU]ABD

On Wed, May 10, 2023 at 11:49 AM Richard Biener wrote: > > On Wed, May 10, 2023 at 11:01 AM Richard Sandiford > wrote: > > > > Oluwatamilore Adebayo writes: > > > From 0b5f469171c340ef61a48a31877d495bb77bd35f Mon Sep 17 00:00:00 2001 > > > From: oluade01 > > > Date: Fri, 14 Apr 2023 10:24:43 +0

Re: [PATCH] ipa-prop: Fix ipa_get_callee_param_type for calls with argument type mismatches

On Wed, 10 May 2023, Jakub Jelinek wrote: > Hi! > > The PR contains a testcase where the Fortran FE creates FUNCTION_TYPE > which doesn't really match the passed in arguments (FUNCTION_TYPE has > 5 arguments, call has 6). Now, I think that is a Fortran FE bug that > should be fixed there, but I

Re: [PATCH] i386: Allow -mlarge-data-threshold with -mcmodel=large

On Fri, Apr 28, 2023 at 2:47 AM Fangrui Song wrote: > > When using -mcmodel=medium, large data is placed into .l* sections. GNU ld > places .l* sections into separate output sections. If small and medium > code model object files are mixed, the .l* sections won't cause > relocation overflow pres

[PATCH] fix radix sort on 32bit platforms [PR109670]

The radix sort uses two buffers, a1 for input and a2 for output. After every digit the role of the two buffers is swapped. When terminating the sort early the code made sure the output was in a2. However, when we run out of bits, as can happen on 32bit platforms, the sorted result was in a1, was

[PATCH][committed] aarch64: PR target/99195 annotate simple saturating add/sub patterns for vec-concat-zero

Hi all, Moving onto the saturating instructions, this one goes through the simple add/sub ones. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. Pushing to trunk. Thanks, Kyrill gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_q)

[PATCH][committed] aarch64: PR target/99195 annotate simple permutation patterns for vec-concat-zero

Hi all, Another straightforward patch annotating patterns for the zip1, zip2, uzp1, uzp2, rev* instructions, plus tests. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. Pushing to trunk. Thanks, Kyrill gcc/ChangeLog: PR target/99195 * config/aarch64/a

[PATCH][committed] aarch64: Simplify sqmovun expander

Hi all, This patch is a no-op as it removes the explicit vec-concat-zero patterns in favour of vczle/vczbe. This allows us to delete the explicit expander too. Tests are added to ensure the optimisation required still triggers. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-no

[RFC] libstdc++: Do not use pthread_mutex_clocklock with ThreadSanitizer

This patch would avoid TSan false positives when using timed waiting functions on mutexes and condvars, but as noted below, it changes the semantics. I'm not sure whether we want this workaround in place until tsan gets fixed. On one hand, there's no guarantee that those functions use the right c

Re: [RFC] libstdc++: Do not use pthread_mutex_clocklock with ThreadSanitizer

On Wed, 10 May 2023 at 12:20, Jonathan Wakely via Libstdc++ < libstd...@gcc.gnu.org> wrote: > This patch would avoid TSan false positives when using timed waiting > functions on mutexes and condvars, but as noted below, it changes the > semantics. > > I'm not sure whether we want this workaround i

[committed] Fix a couple constraints on the H8 in preparation for LRA conversion

So this is the 2nd patch on the way to LRA for the H8. LRA is more sensitive to getting define_constraint vs define_memory_constraint vs define_special_memory_constraint correct. than reload. The H8 port has the "Q" constraint, which is used to indicate memory addresses that can be used unde

[PATCH v2] Var-Tracking: Typedef pointer_mux as decl_or_value

From: Pan Li The decl_or_value is defined as void * before this PATCH. It will take care of both the tree_node and rtx_def. Unfortunately, given a void pointer cannot tell the input is tree_node or rtx_def. Then we have some implicit structure layout requirement similar as below. Or we will touc

RE: [PATCH] Var-Tracking: Leverage pointer_mux for decl_or_value

Thanks all for comments. Looks like pay too much attention for the NULL check but it is covered by pointer_mux already. Update PATCH v2 as below, please help to review continuously. https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618007.html Pan -Original Message- From: Jakub Jelin

Re: [PATCH v2] Var-Tracking: Typedef pointer_mux as decl_or_value

On Wed, May 10, 2023 at 07:57:05PM +0800, pan2...@intel.com wrote: > --- a/gcc/var-tracking.cc > +++ b/gcc/var-tracking.cc > @@ -116,9 +116,14 @@ > #include "fibonacci_heap.h" > #include "print-rtl.h" > #include "function-abi.h" > +#include "mux-utils.h" > > typedef fibonacci_heap bb_heap_t;

Re: [PATCH v2] Var-Tracking: Typedef pointer_mux as decl_or_value

Jakub Jelinek writes: > On Wed, May 10, 2023 at 07:57:05PM +0800, pan2...@intel.com wrote: >> --- a/gcc/var-tracking.cc >> +++ b/gcc/var-tracking.cc >> @@ -116,9 +116,14 @@ >> #include "fibonacci_heap.h" >> #include "print-rtl.h" >> #include "function-abi.h" >> +#include "mux-utils.h" >> >>

[PATCH] RISC-V: Add basic vec_init support for RVV auto-vectorizaiton

From: Juzhe-Zhong This is patching is adding basic vec_init support for RVV auto-vectorization. Testing is on-going. This patch makes vec_init support common init vector handling (using vslide1down to insert element) which can handle any cases of initialization vec but it's not optimal for case

Re: Question on patch -fprofile-partial-training

> Honza, > > Main motivation for this was profiling programs that contain specific > > code paths for different CPUs (such as graphics library in Firefox or Linux > > kernel). In the situation training machine differs from the machine > > program is run later, we end up optimizing for size all code

Re: [PATCH] vect: Missed opportunity to use [SU]ABD

When using inputs of 0x7fff and 0x8000 the result yielded is -1. When using inputs of -1 and 0x7fff the results yielded is 0x8000. Tami From: Richard Biener Sent: Wednesday, May 10, 2023 10:49 AM To: Oluwatamilore Adebayo ; gcc-patches@gcc.gnu.org ; richard.guent

[PATCH 01/20] arm: [MVE intrinsics] factorize vcmp

Factorize vcmp so that they use the same pattern. 2022-10-25 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_CMP_M, MVE_CMP_M_F, MVE_CMP_M_N) (MVE_CMP_M_N_F, mve_cmp_op1): New. (isu): Add VCMP* (supf): Likewise. * config/arm/mve.md (mve_vcmpq

[PATCH 11/20] arm: [MVE intrinsics] rework vaddvq

Implement vaddvq using the new MVE builtins framework. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vaddvq): New. * config/arm/arm-mve-builtins-base.def (vaddvq): New. * config/arm/arm-mve-builtins-base.h (vaddvq): New. * config

[PATCH 09/20] arm: [MVE intrinsics] factorize vaddvq

Factorize vaddvq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon gcc/ * config/arm/iterators.md (mve_insn): Add vaddv. * config/arm/mve.md (@mve_vaddvq_): Rename into ... (@mve_q_): ... this. (mve_vaddvq_p_): Rename into ...

[PATCH 06/20] arm: [MVE intrinsics] factorize vdupq

Factorize vdup builtins so that they use parameterized names. 2022-10-25 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_FP_M_N_VDUPQ_ONLY) (MVE_FP_N_VDUPQ_ONLY): New. (mve_insn): Add vdupq. * config/arm/mve.md (mve_vdupq_n_f): Rename into ...

[PATCH 04/20] arm: [MVE intrinsics] factorize vrev16q vrev32q vrev64q

Factorize vrev16q vrev32q vrev64q so that they use generic builtin names. 2022-10-25 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_V8HF, MVE_V16QI) (MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY) (MVE_FP_M_VREV32Q_ONLY): New iterators.

[PATCH 20/20] arm: [MVE intrinsics] rework vmovlbq vmovltq

Implement vmovlbq, vmovltq using the new MVE builtins framework. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vmovlbq, vmovltq): New. * config/arm/arm-mve-builtins-base.def (vmovlbq, vmovltq): New. * config/arm/arm-mve-builtins-base.h (

[PATCH 15/20] arm: [MVE intrinsics] add unary_acc shape

This patch adds the unary_acc shape description. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_acc): New. * config/arm/arm-mve-builtins-shapes.h (unary_acc): New. --- gcc/config/arm/arm-mve-builtins-shapes.cc | 28 ++

[PATCH 07/20] arm: [MVE intrinsics] add unary_n shape

This patch adds the unary_n shape description. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_n): New. * config/arm/arm-mve-builtins-shapes.h (unary_n): New. --- gcc/config/arm/arm-mve-builtins-shapes.cc | 53 +++ gcc

[PATCH 14/20] arm: [MVE intrinsics] rework vaddvaq

Implement vaddvaq using the new MVE builtins framework. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vaddvaq): New. * config/arm/arm-mve-builtins-base.def (vaddvaq): New. * config/arm/arm-mve-builtins-base.h (vaddvaq): New. * co

[PATCH 10/20] arm: [MVE intrinsics] add unary_int32 shape

This patch adds the unary_int32 shape description. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_int32): New. * config/arm/arm-mve-builtins-shapes.h (unary_int32): New. --- gcc/config/arm/arm-mve-builtins-shapes.cc | 27

[PATCH 16/20] arm: [MVE intrinsics] factorize vaddlvq

Factorize vaddlvq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon gcc/ * config/arm/iterators.md (mve_insn): Add vaddlv. * config/arm/mve.md (mve_vaddlvq_v4si): Rename into ... (@mve_q_v4si): ... this. (mve_vaddlvq_p_v4si): Rena

[PATCH 02/20] arm: [MVE intrinsics] add cmp shape

This patch adds the cmp shape description. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-shapes.cc (cmp): New. * config/arm/arm-mve-builtins-shapes.h (cmp): New. --- gcc/config/arm/arm-mve-builtins-shapes.cc | 27 +++ gcc/config/arm/

[PATCH 18/20] arm: [MVE intrinsics] factorize vmovlbq vmovltq

Factorize vmovlbq, vmovltq builtins so that they use the same parameterized names. 2022-10-25 Christophe Lyon gcc/ * config/arm/iterators.md (mve_insn): Add vmovlb, vmovlt. (VMOVLBQ, VMOVLTQ): Merge into ... (VMOVLxQ): ... this. (VMOVLTQ_M, VMOVLBQ_M): M

[PATCH 19/20] arm: [MVE intrinsics] add unary_widen shape

This patch adds the unary_widen shape description. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_widen): New. * config/arm/arm-mve-builtins-shapes.h (unary_widen): New. --- gcc/config/arm/arm-mve-builtins-shapes.cc | 46

[PATCH 17/20] arm: [MVE intrinsics] rework vaddlvq

Implement vaddlvq using the new MVE builtins framework. Since we kept v4si hardcoded in the builtin name, we need to special-case it in unspec_mve_function_exact_insn_pred_p. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vaddlvq): New. * config

[PATCH 08/20] arm: [MVE intrinsics] rework vdupq

Implement vdupq using the new MVE builtins framework. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N): New. (vdupq): New. * config/arm/arm-mve-builtins-base.def (vdupq): New. * config/arm/arm-mve-builtins-base.h: (

[PATCH 13/20] arm: [MVE intrinsics] add unary_int32_acc shape

This patch adds the unary_int32_acc shape description. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_int32_acc): New. * config/arm/arm-mve-builtins-shapes.h (unary_int32_acc): New. --- gcc/config/arm/arm-mve-builtins-shapes.cc | 34

[PATCH 12/20] arm: [MVE intrinsics] factorize vaddvaq

Factorize vaddvaq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon gcc/ * config/arm/iterators.md (mve_insn): Add vaddva. * config/arm/mve.md (mve_vaddvaq_): Rename into ... (@mve_q_): ... this. (mve_vaddvaq_p_): Rename into ...

[PATCH 05/20] arm: [MVE intrinsics] rework vrev16q vrev32q vrev64q

Implement vrev16q, vrev32q, vrev64q using the new MVE builtins framework. 2022-10-25 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vrev16q, vrev32q, vrev64q): New. * config/arm/arm-mve-builtins-base.def (vrev16q, vrev32q) (vrev64q): New.

Re: Testsuite: Add 'torture-init-done', and use it to conditionalize implicit 'torture-init' (was: Testsuite: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS' usage (was: Let e

Hi Thomas, On Wed, 10 May 2023 at 09:52, Thomas Schwinge wrote: > Hi Christophe! > > On 2023-05-09T21:14:07+0200, Christophe Lyon > wrote: > > On Tue, 9 May 2023 at 17:17, Christophe Lyon > > > wrote: > >> On Tue, 9 May 2023 at 11:00, Thomas Schwinge > >> wrote: > >>> On 2023-05-09T09:32:55+

[PATCH] Avoid g++.dg/torture/pr106922.C FAIL with the pre-C++11 ABI

The following forces the g++.dg/torture/pr106922.C testcase to use the C++11 libstdc++ ABI and checks if that was successful. Does this look OK? Thanks, Richard. * g++.dg/uninit-pr106722-2.C: Force _GLIBCXX_USE_CXX11_ABI to 1. --- gcc/testsuite/g++.dg/torture/pr106922.C | 9 + 1

RE: [PATCH v2] Var-Tracking: Typedef pointer_mux as decl_or_value

I see, will try to get rid of dv_as_opaque everywhere. Thank you all! Pan -Original Message- From: Richard Sandiford Sent: Wednesday, May 10, 2023 8:53 PM To: Jakub Jelinek Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang ; jeffreya.

[PATCH take #3] match.pd: Simplify popcount/parity of bswap/rotate.

This is the latest iteration of my patch from August 2020 https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552391.html incorporating feedback and suggestions from reviewers. This patch to match.pd optimizes away bit permutation operations, specifically bswap and rotate, in calls to popcount

RE: [PATCH 15/20] arm: [MVE intrinsics] add unary_acc shape

> -Original Message- > From: Christophe Lyon > Sent: Wednesday, May 10, 2023 2:31 PM > To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ; > Richard Earnshaw ; Richard Sandiford > > Cc: Christophe Lyon > Subject: [PATCH 15/20] arm: [MVE intrinsics] add unary_acc shape > > This patch adds t

[pushed 1/2] c++: always check consteval address

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- The restriction on the "permitted result of a constant expression" to not refer to an immediate function applies regardless of context. The previous code tried to only check in cases where we wouldn't get the check in cp_fold_r, but with th

[pushed 2/2] c++: be stricter about constinit [CWG2543]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- DR 2543 clarifies that constinit variables should follow the language, and diagnose non-constant initializers (according to [expr.const]) even if they can actually initialize the variables statically. DR 2543 gcc/cp/ChangeLog:

[PATCH v3] Var-Tracking: Typedef pointer_mux as decl_or_value

From: Pan Li The decl_or_value is defined as void * before this PATCH. It will take care of both the tree_node and rtx_def. Unfortunately, given a void pointer cannot tell the input is tree_node or rtx_def. Then we have some implicit structure layout requirement similar as below. Or we will touc

[PATCH] riscv: Add vectorized binops and insn_expander helpers.

Hi, this patch adds basic binary integer operations support. It is based on Michael Collison's work and makes use of the existing helpers in riscv-c.cc. It introduces emit_nonvlmax_binop which, in turn, uses emit_pred_binop. Setting the destination as well as the mask and the length is factored

[PATCH] riscv: Split off shift patterns for autovectorization.

Hi, this patch splits off the shift patterns of the binop patterns. This is necessary as the scalar shifts require a Pmode operand as shift count. To this end, a new iterator any_int_binop_no_shift is introduced. At a later point when the binops are split up further in commutative and non-commut

[PATCH] riscv: Add autovectorization tests for binary integer

Hi, this patchs adds scan as well as execution tests for vectorized binary integer operations. It is based on Michael Collison's work and also includes scalar variants. The tests are not fully comprehensive as the vector type promotions (vec_unpack, extend etc.) are not implemented yet. Also, v

[PATCH] riscv: Clarify vlmax and length handling.

Hi, this patch tries to improve the wrappers that emit either vlmax or non-vlmax operations. Now, emit_len_op can be used to emit a regular operation. Depending on whether a length != NULL is passed either no VLMAX flags are set or we emit a vsetvli and set VLMAX flags. The patch also adds some

Re: [PATCH] vect: Missed opportunity to use [SU]ABD

Richard Biener writes: > On Wed, May 10, 2023 at 11:49 AM Richard Biener > wrote: >> >> On Wed, May 10, 2023 at 11:01 AM Richard Sandiford >> wrote: >> > >> > Oluwatamilore Adebayo writes: >> > > From 0b5f469171c340ef61a48a31877d495bb77bd35f Mon Sep 17 00:00:00 2001 >> > > From: oluade01 >> >

[PATCH] c++: converted lambda as template argument [PR83258, ...]

r8-1253-g3d2e25a240c711 removed the template argument linkage requirement in convert_nontype_argument for C++17, but we need to also remove the one in convert_nontype_argument_function for sake of the first and third test case which we incorrectly reject (in C++17/20 mode). And in invalid_tparm_re

[PATCH V5, 0/2] PR target/105325: Fix constraint issue with power10 fusion

I have posted 4 previous versions of this patch (April 26th, March 28th, March 24th, and March 21st). In this patch, rather than just add changes to the existing code in genfusion.pl, I rewrote the function completely. There are two patches within this patch set: * The first patch rewrites t

Re: [PATCH V5, 1/2] PR target/105325: Rewrite genfusion.pl's gen_ld_cmpi_p10 function.

This patch rewrites the gen_ld_cmpi_p10 function in genfusion.pl to be clearer. The resulting fusion.md file that this patch generates is exactly the same output that the previous version of genfusion.pl generated. The next patch in this series will fix PR target/105325 (provide correct predicates

[PATCH V5, 2/2] PR target/105325: Fix memory constraints for power10 fusion.

This patch applies stricter predicates and constraints for LD and LWA instructions with power10 fusion. These instructions are DS-form instructions, which means that the bottom 2 bits of the address must be 0. In the past, we did not use the stricter predicates and constraints, and if the user us

Re: [PATCH] riscv: Add vectorized binops and insn_expander helpers.

Thanks Robin. A couple comments here: + machine_mode op2mode = Pmode; + if (inner == E_QImode || inner == E_HImode || inner == E_SImode) + op2mode = inner; Remove it. + change it into + e.add_input_operand (src2, op2mode == VOIDmode ? GET_MODE (src2) : op2mode); Very confusing here

Re: [PATCH take #3] match.pd: Simplify popcount/parity of bswap/rotate.

Hi Roger! On 10 May 2023 16:46:10 CEST, Roger Sayle wrote: Just a nit: +/* { dg-final { scan-tree-dump-times "bswap" 0 "optimized" } } */ Can you please use scan-tree-dump-not instead? thanks,

RISC-V: Remove masking third operand of rotate instructions

Rotate instructions do not need to mask the third operand. For example RV64 the following code: unsigned long foo1(unsigned long rs1, unsigned long rs2) { long shamt = rs2 & (64 - 1); return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (64 - 1))); } Compiles to: foo1: andia1,a1,6

Re: [PATCH v3] Var-Tracking: Typedef pointer_mux as decl_or_value

Thanks, mostly looks good to me. Some minor comments below. pan2...@intel.com writes: > From: Pan Li > > The decl_or_value is defined as void * before this PATCH. It will take > care of both the tree_node and rtx_def. Unfortunately, given a void > pointer cannot tell the input is tree_node or rt

[committed] MAINTAINERS: Add myself to write after approval

From: Pan Li Signed-off-by: Pan Li ChangeLog: * MAINTAINERS: Add myself. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8b609411a30..4b846c6b288 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -520,6 +520,7 @@ Marc Lehmann

Re: [PATCH] c++: converted lambda as template argument [PR83258, ...]

On 5/10/23 11:36, Patrick Palka wrote: r8-1253-g3d2e25a240c711 removed the template argument linkage requirement in convert_nontype_argument for C++17, but we need to also remove the one in convert_nontype_argument_function for sake of the first and third test case which we incorrectly reject (in

Re: [PATCH V4] VECT: Add decrement IV iteration loop control by variable amount support

In addition to Jeff's comments: juzhe.zh...@rivai.ai writes: > [...] > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index cc4a93a8763..99cf0cdbdca 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -4974,6 +4974,40 @@ for (i = 1; i < operand3; i++) >operand0[i] = operand0[i - 1] &

[PATCH v2] Fortran: Narrow return types [PR78798]

From: Bernhard Reutner-Fischer gcc/fortran/ChangeLog: PR fortran/78798 * array.cc (compare_bounds): Use narrower return type. (gfc_compare_array_spec): Likewise. (is_constant_element): Likewise. (gfc_constant_ac): Likewise. * check.cc (dim_rank_che

[PATCH 1/2] Fortran: dump-parse-tree attribs: fix unbalanced braces [PR109624]

From: Bernhard Reutner-Fischer gcc/fortran/ChangeLog: PR fortran/109624 * dump-parse-tree.cc (debug): New function for gfc_namespace. (gfc_debug_code): Delete forward declaration. (show_attr): Make sure to print balanced braces. --- (gdb) call debug(gfc_current_n

[PATCH 2/2] Fortran: dump-parse-tree: Mark debug functions with DEBUG_FUNCTION

From: Bernhard Reutner-Fischer gcc/fortran/ChangeLog: * dump-parse-tree.cc (gfc_debug_expr): Remove forward declaration. (debug): Add DEBUG_FUNCTION. (show_code_node): Remove erroneous whitespace. --- Regression tested on x86_64-linux, OK for trunk? --- gcc/fortran/dump

RE: [PATCH 01/20] arm: [MVE intrinsics] factorize vcmp

> -Original Message- > From: Christophe Lyon > Sent: Wednesday, May 10, 2023 2:30 PM > To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ; > Richard Earnshaw ; Richard Sandiford > > Cc: Christophe Lyon > Subject: [PATCH 01/20] arm: [MVE intrinsics] factorize vcmp > > Factorize vcmp so that

[PATCH] Add another new testcase

="execute.exp=20230510-1.c" gcc/testsuite/ChangeLog: * gcc.c-torture/execute/20230510-1.c: New test. --- .../gcc.c-torture/execute/20230510-1.c| 34 +++ 1 file changed, 34 insertions(+) create mode 100644 gcc/testsuite/gcc.c-torture/execute/20230510-1.c

Re: [PATCH] riscv: Add vectorized binops and insn_expander helpers.

> +  machine_mode op2mode = Pmode; > +  if (inner == E_QImode || inner == E_HImode || inner == E_SImode) > + op2mode = inner; This I added in order to match the scalar variants like [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr") (if_then_else:VI_QHS

[PATCH] rs6000: Fix __builtin_vec_xst_trunc definition

GCC maintainers: The following patch fixes errors in the arguments in the __builtin_altivec_tr_stxvrhx, __builtin_altivec_tr_stxvrwx builtin definitions. Note, these builtins are used by the overloaded __builtin_vec_xst_trunc builtin. The patch adds a new overloaded builtin definition for __bu

Re: [PATCH] c++: converted lambda as template argument [PR83258, ...]

On Wed, 10 May 2023, Jason Merrill wrote: > On 5/10/23 11:36, Patrick Palka wrote: > > r8-1253-g3d2e25a240c711 removed the template argument linkage requirement > > in convert_nontype_argument for C++17, but we need to also remove the one > > in convert_nontype_argument_function for sake of the fi

Re: [PATCH] riscv: Clarify vlmax and length handling.

On Wed, 10 May 2023 08:24:40 PDT (-0700), rdapp@gmail.com wrote: Hi, this patch tries to improve the wrappers that emit either vlmax or non-vlmax operations. Now, emit_len_op can be used to emit a regular operation. Depending on whether a length != NULL is passed either no VLMAX flags are

Re: [PATCH] riscv: Clarify vlmax and length handling.

It's somewhat common for mail clients to treat "--" as a signature deliminator, it's "---" that git uses as a comment deliminator. It's in my muscle memory somehow. Always did it that way because I didn't want the same delimiter as in the git part of the message. Time to change that habit I s

Re: [PATCH] riscv: Clarify vlmax and length handling.

On Wed, 10 May 2023 11:50:32 PDT (-0700), rdapp@gmail.com wrote: It's somewhat common for mail clients to treat "--" as a signature deliminator, it's "---" that git uses as a comment deliminator. It's in my muscle memory somehow. Always did it that way because I didn't want the same delimi

Re: [PATCH 1/2] Fortran: dump-parse-tree attribs: fix unbalanced braces [PR109624]

[re-adding the lists, i hope you don't mind] On Wed, 10 May 2023 18:52:54 +0200 Thomas Koenig wrote: > Hi Bernhard, > > both patches look good to me. Pushed as r14-664-g39f7c0963a9c00 and r14-665-gbdc10c2bfaceb3 Thanks! > > No user impact, so they should have the lowest possible impact :-) >

Re: [PATCH] riscv: Split off shift patterns for autovectorization.

On Wed, 10 May 2023 08:24:50 PDT (-0700), rdapp@gmail.com wrote: > Hi, > > this patch splits off the shift patterns of the binop patterns. > This is necessary as the scalar shifts require a Pmode operand > as shift count. To this end, a new iterator any_int_binop_no_shift > is introduced. At

Re: [vxworks] [testsuite] [aarch64] use builtin in pred-not-gen-4.c

Alexandre Oliva via Gcc-patches writes: > On vxworks, isunordered is defined as a macro that ultimately calls a > _Fpcomp function, that GCC doesn't recognize as a builtin, so it > can't optimize accordingly. > > Use __builtin_isunordered instead to get the desired code for the > test. > > Regstra

Re: [PATCH] riscv: Add autovectorization tests for binary integer

On Wed, 10 May 2023 08:24:57 PDT (-0700), rdapp@gmail.com wrote: > Hi, > > this patchs adds scan as well as execution tests for vectorized > binary integer operations. It is based on Michael Collison's work > and also includes scalar variants. The tests are not fully comprehensive > as the ve

[x86_64 PATCH] Use [(const_int 0)] idiom consistently in i386.md

Hi Uros, This cleans up the use of [(clobber (const_int 0))] in the i386 backend. My apologies I must have copied this idiom from one of the other targets: aarch64.md, arm.md, thumb1.md, avr.md, or sparc.md. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check,

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