[PATCH] aarch64: Add -mveclibabi=sleefgnu

This adds support for the -mveclibabi option to the AArch64 backend of GCC by implementing the builtin_vectorized_function target hook for AArch64. The SLEEF Vectorized Math Library's GNUABI interface is used, and NEON/Advanced SIMD as well as SVE are supported. This was tested on the gcc testsuit

Re: [PATCH] aarch64: Add -mveclibabi=sleefgnu

On Fri, Apr 14, 2023 at 12:03 AM Lou Knauer via Gcc-patches wrote: > > This adds support for the -mveclibabi option to the AArch64 backend of GCC by > implementing the builtin_vectorized_function target hook for AArch64. > The SLEEF Vectorized Math Library's GNUABI interface is used, and > NEON/Ad

Re: [PATCH] RISC-V: Update multilib-generator to handle V

Wait, take second round review: > * All extensions were being prefixed with an underscore, which leads to > some odd combinations like "rv32gc_v", this just adds underscores to > the multi-letter extensions. > * The input base ISAs were being canonicalized, which resulted in some > odd multi

[PATCH] testsuite: update builtins-5-p9-runnable.c for BE

Hi, As PR108809 mentioned, vec_xl_len_r and vec_xst_len_r are tested in gcc.target/powerpc/builtins-5-p9-runnable.c. The vector operand of these two bifs are different from the view of v16_int8 between BE and LE, even it is same from the view of 128bits(uint128/V1TI). The test case gcc.target/p

Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for auto-vectorization

on 2023/4/14 14:39, juzhe.zh...@rivai.ai wrote: >>> Yeah, MIN_EXPR is enough for IBM ports, but with seeing the special >>> semantic of vsetvli on >>> "vl = ceil(AVL / 2) for VLMAX < AVL < 2*VLMAX", I'm not sure if it's a good >>>idea for RV, it seems >>> to put the burden to RV backend.  For one

Re: [PATCH] testsuite: update builtins-5-p9-runnable.c for BE

On 2023-04-14 15:30, Jiufu Guo wrote: Hi, As PR108809 mentioned, vec_xl_len_r and vec_xst_len_r are tested in gcc.target/powerpc/builtins-5-p9-runnable.c. The vector operand of these two bifs are different from the view of v16_int8 between BE and LE, even it is same from the view of 128bits(uint

Re: [Patch, fortran] PR109451 - ICE in gfc_conv_expr_descriptor with ASSOCIATE and substrings

Hi Harald, The fix was trivial. An updated patch and testcase are attached. Thanks Paul Fortran: Fix some deferred character problems in associate [PR109451] 2023-04-14 Paul Thomas gcc/fortran PR fortran/109451 * trans-array.cc (gfc_conv_expr_descriptor): Guard expression character length

PATCH] tree-ssa-sink: Add heuristics for code sinking

Hello All: This patch add heuristics for code sinking opportunities. Bootstrapped and regtested for powerpc64-linux-gnu. Thanks & Regards Ajit tree-ssa-sink: Add heuristics for code sinking. Add following code sinking heuristics: 1. from code block dominates the call.

Re: [r13-7135 Regression] FAIL: gcc.dg/vect/vect-simd-clone-18f.c scan-tree-dump-times vect "[\\n\\r] [^\\n]* = foo\\.simdclone" 2 on Linux/x86_64

Resending this to everyone (sorry for the double send Richard). On 14/04/2023 09:15, Andre Vieira (lists) wrote: > > > On 14/04/2023 07:55, Richard Biener wrote: >> On Thu, Apr 13, 2023 at 4:25 PM Andre Vieira (lists) >> wrote: >>> >>> >>> >>> On 13/04/2023 15:00, Richard Biener wrote: On T

Re: PATCH] tree-ssa-sink: Add heuristics for code sinking

On Fri, Apr 14, 2023 at 10:42 AM Ajit Agarwal via Gcc-patches wrote: > > Hello All: > > This patch add heuristics for code sinking opportunities. > Bootstrapped and regtested for powerpc64-linux-gnu. > > Thanks & Regards > Ajit > > tree-ssa-sink: Add heuristics for code sinking. > >

Re: [PATCH] testsuite: update builtins-5-p9-runnable.c for BE

Hi Jeff, on 2023/4/14 16:01, guojiufu wrote: > On 2023-04-14 15:30, Jiufu Guo wrote: >> Hi, >> >> As PR108809 mentioned, vec_xl_len_r and vec_xst_len_r are tested >> in gcc.target/powerpc/builtins-5-p9-runnable.c. >> The vector operand of these two bifs are different from the view >> of v16_int8 b

Re: [r13-7135 Regression] FAIL: gcc.dg/vect/vect-simd-clone-18f.c scan-tree-dump-times vect "[\\n\\r] [^\\n]* = foo\\.simdclone" 2 on Linux/x86_64

On Fri, Apr 14, 2023 at 10:43 AM Andre Vieira (lists) wrote: > > Resending this to everyone (sorry for the double send Richard). > > On 14/04/2023 09:15, Andre Vieira (lists) wrote: > > > > > > On 14/04/2023 07:55, Richard Biener wrote: > >> On Thu, Apr 13, 2023 at 4:25 PM Andre Vieira (lists)

Re: [r13-7135 Regression] FAIL: gcc.dg/vect/vect-simd-clone-18f.c scan-tree-dump-times vect "[\\n\\r] [^\\n]* = foo\\.simdclone" 2 on Linux/x86_64

On Fri, Apr 14, 2023 at 11:09 AM Richard Biener wrote: > > On Fri, Apr 14, 2023 at 10:43 AM Andre Vieira (lists) > wrote: > > > > Resending this to everyone (sorry for the double send Richard). > > > > On 14/04/2023 09:15, Andre Vieira (lists) wrote: > > > > > > > > > On 14/04/2023 07:55, Rich

RE: [PATCH] aarch64: disable LDP via tuning structure for -mcpu=ampere1

Hi Philipp, > -Original Message- > From: Philipp Tomsich > Sent: Friday, April 14, 2023 12:22 AM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Philipp Tomsich > ; Di Zhao > Subject: [PATCH] aarch64: disable LDP via tuning structure for - > mcpu=ampere1 > > AmpereOne (-mcpu=ampere

Re: [PATCH] aarch64: disable LDP via tuning structure for -mcpu=ampere1

Kyrylo, On Fri, 14 Apr 2023 at 11:21, Kyrylo Tkachov wrote: > > Hi Philipp, > > > -Original Message- > > From: Philipp Tomsich > > Sent: Friday, April 14, 2023 12:22 AM > > To: gcc-patches@gcc.gnu.org > > Cc: Kyrylo Tkachov ; Philipp Tomsich > > ; Di Zhao > > Subject: [PATCH] aarch64: d

RE: [PATCH] aarch64: Add -mveclibabi=sleefgnu

> -Original Message- > From: Andrew Pinski > Sent: Friday, April 14, 2023 09:08 > To: Lou Knauer > Cc: gcc-patches@gcc.gnu.org; Etienne Renault > Subject: Re: [PATCH] aarch64: Add -mveclibabi=sleefgnu > > On Fri, Apr 14, 2023 at 12:03 AM Lou Knauer via Gcc-patches > wrote: > > > > This

Re: [r13-7135 Regression] FAIL: gcc.dg/vect/vect-simd-clone-18f.c scan-tree-dump-times vect "[\\n\\r] [^\\n]* = foo\\.simdclone" 2 on Linux/x86_64

On 14/04/2023 10:09, Richard Biener wrote: On Fri, Apr 14, 2023 at 10:43 AM Andre Vieira (lists) wrote: Resending this to everyone (sorry for the double send Richard). On 14/04/2023 09:15, Andre Vieira (lists) wrote: > > > On 14/04/2023 07:55, Richard Biener wrote: >> On Thu, Apr 1

[PATCH] Fix vect-simd-clone testcase dump scanning

This replaces i686*-*-* && { ! lp64 } with the appropriate { i?86-*-* x86_64-*-* } && { ! lp64 } for the testcases and also amends the e variants checking last variant for avx. I've used avx in the dump scanning, not avx_runtime, since the dumps get produced when one would not execute but only comp

[PATCH] tree-optimization/109502 - vector conversion between mask and non-mask

The following fixes a check that should have rejected vectorizing a conversion between a mask and non-mask type. Those should be done via pattern statements. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/109502 * tree-vect-stmts.cc (vectorizabl

Re: [PATCH] libstdc++: Implement ranges::fold_* from P2322R6

On Fri, 14 Apr 2023 at 05:01, Patrick Palka via Libstdc++ wrote: > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk? OK, looks good, thanks. > > libstdc++-v3/ChangeLog: > > * include/bits/ranges_algo.h: Include for C++23. > (__cpp_lib_fold): Define for C++23. >

Re: [PATCH 1/2] libstdc++: Move down definitions of ranges::cbegin/cend/cetc

On Fri, 14 Apr 2023 at 05:02, Patrick Palka via Libstdc++ wrote: > > This moves down the definitions of the const range access CPOs to after > the definition of input_range in preparation for implementing P2287R4 > which redefines these CPOs in a way that indirectly uses input_range. > > tested on

Re: [PATCH] Fix vect-simd-clone testcase dump scanning

On Fri, Apr 14, 2023 at 11:42:55AM +0200, Richard Biener via Gcc-patches wrote: > This replaces i686*-*-* && { ! lp64 } with the appropriate > { i?86-*-* x86_64-*-* } && { ! lp64 } for the testcases and > also amends the e variants checking last variant for avx. > I've used avx in the dump scanning

Re: [PATCH] aarch64: disable LDP via tuning structure for -mcpu=ampere1

For phase 1, we plan to replace this with a feature to allow finer-grained control over when to use LDP or STP (i.e., control these independently) with the following scopes and policies: - scopes are: { sched-fusion, mem, pro/epilogue, peephole } - policies are: { default (from tuning), always, n

Re: [PATCH 2/2] libstdc++: Implement P2278R4 "cbegin should always return a constant iterator"

On Fri, 14 Apr 2023 at 07:03, Patrick Palka via Libstdc++ wrote: > > This also implements the approved follow-up LWG issues 3765, 3766, 3769, > 3770, 3811, 3850, 3853, 3862 and 3872. > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk? Hooray! THANK YOU! No comments on the patch itsel

Re: PATCH] tree-ssa-sink: Add heuristics for code sinking

Hello Richard: On 14/04/23 2:29 pm, Richard Biener wrote: > On Fri, Apr 14, 2023 at 10:42 AM Ajit Agarwal via Gcc-patches > wrote: >> >> Hello All: >> >> This patch add heuristics for code sinking opportunities. >> Bootstrapped and regtested for powerpc64-linux-gnu. >> >> Thanks & Regards >> Ajit

Re: [PATCH 2/2] libstdc++: Implement P2278R4 "cbegin should always return a constant iterator"

On 14/04/23 00:00 -0400, Patrick Palka wrote: This also implements the approved follow-up LWG issues 3765, 3766, 3769, 3770, 3811, 3850, 3853, 3862 and 3872. Tested on x86_64-pc-linux-gnu, does this look OK for trunk? libstdc++-v3/ChangeLog: * include/bits/ranges_base.h (const_iterator

Re: [PATCH] Fix vect-simd-clone testcase dump scanning

On Fri, 14 Apr 2023, Jakub Jelinek wrote: > On Fri, Apr 14, 2023 at 11:42:55AM +0200, Richard Biener via Gcc-patches > wrote: > > This replaces i686*-*-* && { ! lp64 } with the appropriate > > { i?86-*-* x86_64-*-* } && { ! lp64 } for the testcases and > > also amends the e variants checking last

Re: [PATCH] Fix vect-simd-clone testcase dump scanning

On Fri, Apr 14, 2023 at 10:15:06AM +, Richard Biener wrote: > Oops. Indeed target_avx checks whether it can compile sth with > -O2 -mavx rather than verifying avx is present. I've seen scan > failures with -m32/-march=cascadelake on a zen2 host. I'm not exactly > sure why. That is strange.

Re: [PATCH] aarch64: disable LDP via tuning structure for -mcpu=ampere1

On Fri, 14 Apr 2023 at 11:31, Philipp Tomsich wrote: > Kyrylo, > > On Fri, 14 Apr 2023 at 11:21, Kyrylo Tkachov > wrote: > > > > Hi Philipp, > > > > > -Original Message- > > > From: Philipp Tomsich > > > Sent: Friday, April 14, 2023 12:22 AM > > > To: gcc-patches@gcc.gnu.org > > > Cc: K

Re: [PATCH] aarch64: Add -mveclibabi=sleefgnu

I have (outdated) RFC's here: https://gcc.gnu.org/pipermail/gcc-patches/2023-March/613593.html I am working on this patch series for stage 1. The list of features I am working on are: * SVE support for #pragma omp declare simd * Support for simdclone usage in autovec from #pragma omp declare v

Re: [PATCH] Fix vect-simd-clone testcase dump scanning

On the other thread I commented that inbranch simdclones are failing for AVX512F because it sets the mask_mode, for which inbranch hasn't been implemented, and so it is rejected. On 14/04/2023 11:25, Jakub Jelinek via Gcc-patches wrote: On Fri, Apr 14, 2023 at 10:15:06AM +, Richard Biener

[committed] libstdc++: Improve diagnostics for invalid std::format calls

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- Add a static_assert and a comment so that calling std::format for unformattable argument types will now show: /home/jwakely/gcc/13/include/c++/13.0.1/format:3563:22: error: static assertion failed: std::formatter must be specialized for each f

Re: [PATCH] Fix vect-simd-clone testcase dump scanning

On Fri, Apr 14, 2023 at 11:59:02AM +0100, Andre Vieira (lists) wrote: > On the other thread I commented that inbranch simdclones are failing for > AVX512F because it sets the mask_mode, for which inbranch hasn't been > implemented, and so it is rejected. But then we can as well use -mno-avx512f in

RE: [PATCH] aarch64: disable LDP via tuning structure for -mcpu=ampere1

Hi Philipp, From: Philipp Tomsich Sent: Friday, April 14, 2023 11:26 AM To: Kyrylo Tkachov Cc: gcc-patches@gcc.gnu.org; Di Zhao Subject: Re: [PATCH] aarch64: disable LDP via tuning structure for -mcpu=ampere1 On Fri, 14 Apr 2023 at 11:31, Philipp Tomsich w

Re: [PATCH] aarch64: disable LDP via tuning structure for -mcpu=ampere1

On Fri, 14 Apr 2023 at 13:02, Kyrylo Tkachov wrote: > Hi Philipp, > > From: Philipp Tomsich > Sent: Friday, April 14, 2023 11:26 AM > To: Kyrylo Tkachov > Cc: gcc-patches@gcc.gnu.org; Di Zhao > Subject: Re: [PATCH] aarch64: disable LDP via tuning structure for > -mcpu=ampere1 > > > > On Fri, 1

[PATCH] vect-simd-clone testcase adjustments

The following reverts the s/avx_runtime/avx/ changes I've done, they were wrong. Pushed. * gcc.dg/vect/vect-simd-clone-16e.c: Revert back to checking avx_runtime in dump scanning. * gcc.dg/vect/vect-simd-clone-17e.c: Likewise. * gcc.dg/vect/vect-simd-clone-18e.c: L

Re: [r13-7135 Regression] FAIL: gcc.dg/vect/vect-simd-clone-18f.c scan-tree-dump-times vect "[\\n\\r] [^\\n]* = foo\\.simdclone" 2 on Linux/x86_64

On Fri, Apr 14, 2023 at 11:42 AM Andre Vieira (lists) wrote: > > > > On 14/04/2023 10:09, Richard Biener wrote: > > On Fri, Apr 14, 2023 at 10:43 AM Andre Vieira (lists) > > wrote: > >> > >> Resending this to everyone (sorry for the double send Richard). > >> > >> On 14/04/2023 09:15, Andre Vieir

Re: PATCH] tree-ssa-sink: Add heuristics for code sinking

On Fri, Apr 14, 2023 at 12:08 PM Ajit Agarwal wrote: > > Hello Richard: > > On 14/04/23 2:29 pm, Richard Biener wrote: > > On Fri, Apr 14, 2023 at 10:42 AM Ajit Agarwal via Gcc-patches > > wrote: > >> > >> Hello All: > >> > >> This patch add heuristics for code sinking opportunities. > >> Bootstr

Re: [PATCH] gcov: add info about "calls" to JSON output format

> On 4/11/23 11:23, Richard Biener wrote: > > On Thu, Apr 6, 2023 at 3:58 PM Martin Liška wrote: > >> > >> Patch can bootstrap on x86_64-linux-gnu and survives regression tests. > >> > >> Ready to be installed after stage1 opens? > > > > Did we release a compiler with version 1? If not we might

Re: libgm2: Adjust 'autogen.sh' to 'ACLOCAL_AMFLAGS', and simplify

Thomas Schwinge writes: > Hi! > > On 2022-12-06T14:47:26+, Gaius Mulley via Gcc-patches > wrote: >> This patch set consists of the libgm2 makefile, autoconf sources >> necessary to build the libm2pim, libm2iso, libm2min, libm2cor >> and libm2log. > > Notice: > >> --- /dev/null 2022-08-24 16

Re: [r13-7135 Regression] FAIL: gcc.dg/vect/vect-simd-clone-18f.c scan-tree-dump-times vect "[\\n\\r] [^\\n]* = foo\\.simdclone" 2 on Linux/x86_64

On 14/04/2023 12:47, Richard Biener wrote: On Fri, Apr 14, 2023 at 11:42 AM Andre Vieira (lists) wrote: Ah, but then vect_get_smallest_scalar_type should simply ignore that pointer in MASK_CALL. It should only look at the arguments relevant for vectorization. So diff --git a/gcc/tree-

Re: [PATCH] Fix vect-simd-clone testcase dump scanning

SGTM On 14/04/2023 12:00, Jakub Jelinek wrote: On Fri, Apr 14, 2023 at 11:59:02AM +0100, Andre Vieira (lists) wrote: On the other thread I commented that inbranch simdclones are failing for AVX512F because it sets the mask_mode, for which inbranch hasn't been implemented, and so it is rejected.

Re: [PATCH v2 #1/2] enable adjustment of return_pc debug attrs

On Mar 23, 2023, Alexandre Oliva wrote: > This patch introduces infrastructure for targets to add an offset to > the label issued after the call_insn to set the call_return_pc > attribute. This will be used on rs6000, that sometimes issues another > instruction after the call proper as part of a

Re: [PATCH 2/2] libstdc++: Implement P2278R4 "cbegin should always return a constant iterator"

On Fri, 14 Apr 2023, Jonathan Wakely wrote: > On 14/04/23 00:00 -0400, Patrick Palka wrote: > > This also implements the approved follow-up LWG issues 3765, 3766, 3769, > > 3770, 3811, 3850, 3853, 3862 and 3872. > > > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk? > > > > libstdc+

RE: [PATCH] aarch64: Add -mveclibabi=sleefgnu

Hello Andre, Thank you for your nice reply. I can see that your patches, combined with upcoming AArch64 support in libmvec, will nullify the need for my patch. I will definitely test your patches and look forward to seeing them evolve, I will rebase and apply them myself. Thank you very much! K

Re: Blockchain solutions

Hello, I am writing to follow up on my email. /*Can we get on a call on *//*Monday (17th April)*//*or Tuesday (18th April) so we can discuss Blockchain Solution requirements you may have? */ Please suggest a day and time to connect and also share the best number to reach you. Thank you Sha

Re: [PATCH] aarch64: Add -mveclibabi=sleefgnu

No problem Lou and testing will be appreciated. I strongly recommend against rebasing the version that is on the mailing list now, the conflicts with Andrew's patches aren't simple to resolve ;) I'll do my best to get you revised versions next week :) On 14/04/2023 16:07, Lou Knauer wrote: H

Re: [Patch, fortran] PR109451 - ICE in gfc_conv_expr_descriptor with ASSOCIATE and substrings

Hi Paul, On 4/14/23 10:18, Paul Richard Thomas via Gcc-patches wrote: Hi Harald, The fix was trivial. An updated patch and testcase are attached. great, this works, and I couldn't break it again this time ... Looks good! Thanks, Harald Thanks Paul Fortran: Fix some deferred character pro

[PATCH v4 00/10] RISCV: Implement ISA Manual Table A.6 Mappings

This patchset aims to make the RISCV atomics implementation stronger than the recommended mapping present in table A.6 of the ISA manual. https://github.com/riscv/riscv-isa-manual/blob/c7cf84547b3aefacab5463add1734c1602b67a49/src/memory.tex#L1083-L1157 The current mapping in GCC is not internal

[PATCH v4 01/10] RISCV: Eliminate SYNC memory models

Remove references to MEMMODEL_SYNC_* models by converting via memmodel_base(). 2023-04-14 Patrick O'Neill * riscv.cc: Remove MEMMODEL_SYNC_* cases and sanitize memmodel input with memmodel_base Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 11 +++ 1 fi

[PATCH v4 02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST

Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * atomic.c: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- libgcc/config/riscv/at

[PATCH v4 03/10] RISCV: Enforce atomic compare_exchange SEQ_CST

This patch enforces SEQ_CST for atomic compare_exchange ops. Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * sync.md: Change FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl pai

[PATCH v4 04/10] RISCV: Add AMO release bits

This patch sets the relevant .rl bits on amo operations. 2023-04-14 Patrick O'Neill * riscv.cc (riscv_print_operand): change behavior of %A to include release bits. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 7 ++- 1 file changed, 6 insertions(+), 1 del

[PATCH v4 09/10] RISCV: Weaken atomic loads

This change brings atomic loads in line with table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * sync.md (atomic_load): Implement atomic load mapping. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Add this patch --- gcc/config/riscv/sync.md | 27 ++-

[PATCH v4 10/10] RISCV: Table A.6 conformance tests

These tests cover basic cases to ensure the atomic mappings follow the strengthened Table A.6 mappings that are compatible with Table A.7. 2023-04-14 Patrick O'Neill * amo-table-a-6-amo-add-1.c: New test. * amo-table-a-6-amo-add-2.c: Likewise. * amo-table-a-6-amo-add-3.c:

[PATCH v4 05/10] RISCV: Strengthen atomic stores

This change makes atomic stores strictly stronger than table A.6 of the ISA manual. This mapping makes the overall patchset compatible with table A.7 as well. 2023-04-14 Patrick O'Neill PR target/89835 * sync.md (atomic_store): Use simple store instruction in combination

[PATCH v4 06/10] RISCV: Eliminate AMO op fences

Atomic operations with the appropriate bits set already enfore release semantics. Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * riscv.cc (riscv_memmodel_needs_amo_acquire): Change func

[PATCH v4 07/10] RISCV: Weaken compare_exchange LR/SC pairs

Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs as needed. Atomic compare and exchange ops provide success and failure memory models. C++17 and later place no restrictions on the relative strength of each model, so ensure we cover both by using a model that enforces the ord

[PATCH v4 08/10] RISCV: Weaken mem_thread_fence

This change brings atomic fences in line with table A.6 of the ISA manual. Relax mem_thread_fence according to the memmodel given. 2023-04-14 Patrick O'Neill * sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill --- v3

Disable X86_TUNE_AVX256_MOVE_BY_PIECES and STORE_BY_PIECES for znver1-3

Hi, I have enabled SSE moves for znver1-3 since they are performance win on this machine too (we avoid using loops or string operations which are more costy). However as discussed in the PR log, this triggers bug in IRA and it was decided it is better to not backport the fix. Bootstrapped/regteste

[PATCH v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a

AmpereOne (-mcpu=ampere1) breaks LDP instructions into two uops. Given the chance that this causes instructions to slip into the next decoding cycle and the additional overheads when handling cacheline-crossing LDP instructions, we disable the generation of LDP isntructions through the tuning struc

[Ada] Fix PR bootstrap/109510

This is the build failure of the Ada runtime for Aarch64 targets. The Aarch64 back-end now asserts that the main variant of scalar types has TYPE_USER_ALIGN cleared, and that's not the case for scalar types declared with a confirming alignment clause in Ada. Tested on Aarch64/Linux by Richard

[no subject]

Dear all, the compile-time simplification of intrinsic SET_EXPONENT was broken since the early days of gfortran for argument X < 1 (including negative X) and for I < 0. I identified and fixed several issues in the implementation. The testcase explores argument space comparing compile-time and ru

[PATCH] Fortran: fix compile-time simplification of SET_EXPONENT [PR109511]

[Now with subject added...] Dear all, the compile-time simplification of intrinsic SET_EXPONENT was broken since the early days of gfortran for argument X < 1 (including negative X) and for I < 0. I identified and fixed several issues in the implementation. The testcase explores argument space

Re: [PATCH] tree-optimization/109304 - properly handle instrumented aliases

> On Tue, 4 Apr 2023, Jan Hubicka wrote: > > > > On Tue, 28 Mar 2023, Richard Biener wrote: > > > > > > > When adjusting calls to reflect instrumentation we failed to handle > > > > calls to aliases since they appear to have no body. Instead resort > > > > to symtab node availability. The patch

[PATCH] c: Fix up error-recovery on functions initialized as variables [PR109412]

Hi! The change to allow empty initializers in C broke error-recovery on the following testcase. We are emitting function %qD is initialized like a variable error early; if the initializer is non-empty, we just emit another error that the initializer is invalid. Previously if it was empty, we'd e

[PATCH] c: Fix up error-recovery on non-empty VLA initializers [PR109409]

Hi! On the following testcase we ICE, because after we emit the variable-sized object may not be initialized except with an empty initializer error we don't really reset the initializer to error_mark_node and then at -Wformat checking time we ICE on seeing STRING_CST initializer for a VLA. The fo

Re: [PATCH] update_web_docs_git: Add updated Texinfo to PATH

On Tue, 11 Apr 2023, Arsen Arsenović wrote: > Ah! Good idea. What do you think of the following? Did you intentionally not implement the following part of my suggestion if [ x${MAKEINFO}x = xx ]; then : that is, allowing to override from the command-line (or crontab)? And why the colon

Re: [PATCH] Fortran: fix compile-time simplification of SET_EXPONENT [PR109511]

On Fri, Apr 14, 2023 at 08:59:24PM +0200, Harald Anlauf via Fortran wrote: > > the compile-time simplification of intrinsic SET_EXPONENT was > broken since the early days of gfortran for argument X < 1 > (including negative X) and for I < 0. I identified and fixed > several issues in the implemen

[PATCH 1/2] libstdc++: Convert _RangeAdaptorClosure into a CRTP class [PR108827]

Using the CRTP idiom for this base class avoids bloating the size of a pipeline when adding distinct empty range adaptor closure objects to it, as detailed in section 4.1 of P2387R3. But it means we can no longer define its operator| overloads as hidden friends, since each instantiation of _RangeA

[PATCH 2/2] libstdc++: Implement range_adaptor_closure from P2387R3 [PR108827]

Tested on x86_64-pc-linux-gnu, does this look OK for trunk? PR libstdc++/108827 libstdc++-v3/ChangeLog: * include/bits/ranges_cmp.h (__cpp_lib_ranges): Bump value for C++23. * include/std/ranges (range_adaptor_closure): Define for C++23. * include/std/vers

Re: [PATCH] Fortran: fix compile-time simplification of SET_EXPONENT [PR109511]

On Fri, Apr 14, 2023 at 12:33:18PM -0700, Steve Kargl via Fortran wrote: > >If X is an IEEE NaN, the result is the same NaN. > A better testcase as gfortran will quiet a NaN on assignment. program foo integer i equivalence(i,y) i = int(z'7FC0BEEF',4) ! Add payload to NaN. print

Re: [PATCH] Fortran: fix compile-time simplification of SET_EXPONENT [PR109511]

Hi Steve, On 4/14/23 21:33, Steve Kargl via Gcc-patches wrote: On Fri, Apr 14, 2023 at 08:59:24PM +0200, Harald Anlauf via Fortran wrote: the compile-time simplification of intrinsic SET_EXPONENT was broken since the early days of gfortran for argument X < 1 (including negative X) and for I <

For GCC, newlib combined tree, newlib build-tree testing, use standard search paths

Hi! OK to push to newlib main branch the attached "For GCC, newlib combined tree, newlib build-tree testing, use standard search paths" -- or is something else wrong here, or should this be done differently? (I mean, I'm confused why this doesn't just work; I'm certainly not the first person to b

Re: [PATCH v2] ree: Improve ree pass for rs6000 target.

On 4/6/23 04:49, Ajit Agarwal wrote: Hello All: Eliminate unnecessary redundant extension within basic and across basic blocks. For rs6000 target we see redundant zero and sign extension and done to improve ree pass to eliminate such redundant zero and sign extension. Bootstrapped and regt

Re: [PATCH] update_web_docs_git: Add updated Texinfo to PATH

Gerald Pfeifer writes: > On Tue, 11 Apr 2023, Arsen Arsenović wrote: >> Ah! Good idea. What do you think of the following? > > Did you intentionally not implement the following part of my suggestion > >if [ x${MAKEINFO}x = xx ]; then >: > > that is, allowing to override from the comman

Re: [PATCH] Fortran: fix compile-time simplification of SET_EXPONENT [PR109511]

On Fri, Apr 14, 2023 at 09:49:22PM +0200, Harald Anlauf wrote: > > On 4/14/23 21:33, Steve Kargl via Gcc-patches wrote: > > I was wondering about the difference between set_exponent() > > and scale(), and found that set_exponent() talks about IEEE > > values while scale() doesn't. I'm wondering i

Re: [PATCH] In the ready lists of pipeline, put unrecog insns (such as CLOBBER, USE) at the latest to issue.

On 3/27/23 11:01, Richard Sandiford wrote: Jin Ma via Gcc-patches writes: Unrecog insns (such as CLOBBER, USE) does not represent real instructions, but in the process of pipeline optimization, they will wait for transmission in ready list like other insns, without considering resource

[pushed] wwwdocs: codingconventions: Recommend "file name" over "filename"

This is based on an exchange with Sandra and Joseph back in, umm, April 2018. Pushed for now. Gerald --- This aligns with the C and C++ standards as well as the GNU Coding Standards, though POSIX uses "filename" as a component of "pathname". --- htdocs/codingconventions.html | 5 + 1 file

[PATCH RFA] -Wdangling-pointer: fix MEM_REF handling [PR109514]

Tested x86_64-pc-linux-gnu, ok for trunk? -- 8< -- Here we hit the MEM_REF case, with its arg an ADDR_EXPR, but had no handling for that and wrongly assumed it would be a reference to a local variable. This patch overhauls the logic for deciding whether the target is something to warn about so th

Re: [PATCH RFA] -Wdangling-pointer: fix MEM_REF handling [PR109514]

On 4/14/23 17:42, Jason Merrill via Gcc-patches wrote: Tested x86_64-pc-linux-gnu, ok for trunk? -- 8< -- Here we hit the MEM_REF case, with its arg an ADDR_EXPR, but had no handling for that and wrongly assumed it would be a reference to a local variable. This patch overhauls the logic for

New Croatian PO file for 'gcc' (version 13.1-b20230409)

Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'gcc' has been submitted by the Croatian team of translators. The file is available at: https://translationproject.org/latest/gcc/hr.po (This file, 'gcc-13.1-b20230409.hr.po

Re: [PATCH RFA] -Wdangling-pointer: fix MEM_REF handling [PR109514]

On 4/14/23 21:22, Jeff Law wrote: On 4/14/23 17:42, Jason Merrill via Gcc-patches wrote: Tested x86_64-pc-linux-gnu, ok for trunk? -- 8< -- Here we hit the MEM_REF case, with its arg an ADDR_EXPR, but had no handling for that and wrongly assumed it would be a reference to a local variable.

New Croatian PO file for 'gcc' (version 13.1-b20230409)

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Re: [PATCH] [PR99708] [rs6000] don't expect __ibm128 with 64-bit long double

On Apr 7, 2023, "Kewen.Lin" wrote: > This new version causes unresolved record on my side, it's due to the > compilation failed to produce executable. Yeah, it does that, I didn't realize that was undesirable. > So I think we need to make the file be compiled well, how about something > like:

Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit

On Thu, 13 Apr 2023, Richard Biener via Gcc-patches wrote: > On Thu, 13 Apr 2023, Richard Sandiford wrote: > > > ??? writes: > > > Yeah, like kito said. > > > Turns out the tuple type model in ARM SVE is the optimal solution for RVV. > > > And we like ARM SVE style implmentation. > > > > > > And

New Croatian PO file for 'gcc' (version 13.1-b20230409)

Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'gcc' has been submitted by the Croatian team of translators. The file is available at: https://translationproject.org/latest/gcc/hr.po (This file, 'gcc-13.1-b20230409.hr.po