From: Yanzhang Wang
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
PR 109104
gcc/ChangeLog:
* config/riscv/riscv-protos.h (GCC_RISCV_PROTOS_H):
(emit_hard_
Hi All,
Please find attached the patch to fix the dg directives and remove a lot of
trailing white space.
Unless there are any objections, I will commit as obvious over the weekend.
Cheers
Paul
Fortran: Fix dg directives and remove trailing whitespaces in testsuite
2023-04-07 Paul Thomas
Dear All,
Please find attached a slightly updated version of the patch with a
consolidated testcase. The three additional testcases are nothing to do
with associate and test fixes of character related bugs.
OK for mainline?
Cheers
Paul
Fortran: Fix some of the bugs in associate [PR87477]
2023-
Generally LGTM, just one more comment :)
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..aad046240ee 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -724,4 +735,54 @@ gen_avl_for_scalar_move (rtx avl)
> }
> }
>
gcc/ChangeLog:
* doc/extend.texi: Add section for LoongArch Base Built-in functions.
---
gcc/doc/extend.texi | 129
1 file changed, 129 insertions(+)
---
v1 -> v2:
(1) Does not use i8, u8, i16, u16 etc.
(2) Add the description informati
Hi Paul,
On 4/7/23 09:02, Paul Richard Thomas via Gcc-patches wrote:
Hi All,
Please find attached the patch to fix the dg directives and remove a lot of
trailing white space.
Unless there are any objections, I will commit as obvious over the weekend.
this is OK.
Thanks for the patch!
Haral
Hi Paul,
I don't see the new testcases. Is this an issue on my side,
or did you forget to attach them?
Thanks,
Harald
On 4/7/23 09:07, Paul Richard Thomas via Gcc-patches wrote:
Dear All,
Please find attached a slightly updated version of the patch with a
consolidated testcase. The three add
Hi Alexandre,
on 2023/4/7 09:48, Alexandre Oliva wrote:
> On Apr 6, 2023, "Kewen.Lin" wrote:
>
>> The reason why personally I preferred to fix it with xfail is that:
>
> Got it. I'm convinced, and I agree.
>
> I tried an xfail in the initial dg-do, but that is no good for a compile
> error,
Hi Alexandre,
on 2023/4/7 12:37, Alexandre Oliva wrote:
> On Apr 6, 2023, "Kewen.Lin" wrote:
>
>> on 2023/4/6 13:20, Alexandre Oliva wrote:
>>> I confirm I observe the problem with gcc-12 targeting ppc64-vx7r2,
>>> containing the backported patch, and that the loop is vectorized,
>>> failing th
Hi!
On Fri, Apr 07, 2023 at 02:32:04AM -0400, Michael Meissner wrote:
> On Thu, Apr 06, 2023 at 03:37:59PM -0500, Segher Boessenkool wrote:
> > > This patch eliminates the generation of the Altivec fmaddfp and fnmsubfp
> > > instructions as alternatives in the VSX instruction insn support, and in
From: Yanzhang Wang
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
PR 109104
gcc/ChangeLog:
* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
* confi
duuuh! Please find them attached.
Thanks
Paul
On Fri, 7 Apr 2023 at 10:41, Harald Anlauf wrote:
> Hi Paul,
>
> I don't see the new testcases. Is this an issue on my side,
> or did you forget to attach them?
>
> Thanks,
> Harald
>
> On 4/7/23 09:07, Paul Richard Thomas via Gcc-patches wrote:
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input values. This patch disables
their generation since the equivalent div/mul/sub sequence does not suffer
the same problem.
Boo
Hi!
On Fri, Apr 07, 2023 at 02:34:01AM -0400, Michael Meissner wrote:
> As we discussed in a private chat room, I modified the code to generate
> vmaddfp
> and vnmsubfp if -Ofast (-ffast-math) is used.
As I said, that is no good.
> This allows the compiler to
> eliminate the extra move if the u
Hi Paul,
On 4/7/23 15:53, Paul Richard Thomas via Gcc-patches wrote:
duuuh! Please find them attached.
the patch LGTM. Thanks!
However, I have comments on the new testcase associate_60.f90:
subroutine pr93813 is missing an allocation of x, e.g.:
allocate (t :: x)
otherwise it would be
This libgo patch removes a test ordering dependency in the mime
package. This is a backport of https://go.dev/cl/421442 from the
upstream repo. This fixes https://go.dev/issue/51648. Bootstrapped
and ran mime tests on x86_64-pc-linux-gnu. Committed to mainline.
Ian
f22c12d7361d22d47cce73d342ed
Hi Harald,
Well done on noticing the memory leak :-) I have a fix for it that I was
going to post separately. Actually, it is a trivial one liner, which I
could include with the patch.
@@ -2554,23 +2559,25 @@ gfc_conv_string_length (gfc_charlen * cl, gfc_expr
* expr, stmtblock_t * pblock)
e
PS Quite right about the allocation in PR93813 - consider it to be included.
Cheers and thanks
Paul
On Fri, 7 Apr 2023 at 22:35, Paul Richard Thomas <
paul.richard.tho...@gmail.com> wrote:
> Hi Harald,
>
> Well done on noticing the memory leak :-) I have a fix for it that I was
> going to post
This patch adds the cost and scheduling models for Neoverse N1, based on the
information from the "Arm Neoverse N1 Software Optimization Guide”.
--
Evandro Menezes ◊ evan...@yahoo.com
[PATCH] aarch64: Add the cost and scheduling models for Neoverse N1
gcc/ChangeLog:
* config/aarch64/a
Ping for this patch.
On Thu, Mar 23, 2023 at 4:06 AM Ken Matsui wrote:
>
> In the type_traits header, both integral_constant and __bool_constant
> are used. This patch unifies those usages into __bool_constant.
>
> libstdc++-v3/ChangeLog:
>
> * include/std/type_traits: Use __bool_constant
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