> I would like to revise this patch to be more conservative (only applying to
> Darwin 8 and 9).
This is OK, thanks (and Happy New Year!)
> > On 24 Dec 2022, at 19:00, Iain Sandoe via Gcc-patches
> > wrote:
> >
> > Tested on i686, x86-64 darwin, x86_64-linux (with a 32b multilib).
> > OK for
On 25.11.22 03:13, Sandra Loosemore wrote:
This patch is a followup to my not-yet-reviewed patch
[PATCH v4] OpenMP: Generate SIMD clones for functions with "declare
target"
That patch got reviewed and went into mainline on Nov 15, 2022 as
https://gcc.gnu.org/r13-4309-g309e2d95e3b930c6f15c8a5346
tested on x86_64-linux-gnu, x86_64,aarch64-darwin21,
OK for trunk?
thanks,
Iain
--- 8< ---
This was unimplemented so far.
gcc/ChangeLog:
* common.opt: Add -static-libgm2.
* config/darwin.h (LINK_SPEC): Handle static-libgm2.
gcc/m2/ChangeLog:
* gm2spec.cc (lang_specific
PING PING
Cupertino Miranda writes:
> Cupertino Miranda via Gcc-patches writes:
>
>> gentle ping
>>
>> Cupertino Miranda writes:
>>
>>> Hi Jeff,
>>>
>>> First of all thanks for your quick review.
>>> Apologies for the delay replying, the message got lost in my inbox.
>>>
On 12/2/22 10:52,
PING PING
Cupertino Miranda writes:
> Cupertino Miranda via Gcc-patches writes:
>
>> gentle ping
>>
>> Cupertino Miranda writes:
>>
On 12/2/22 10:52, Cupertino Miranda via Gcc-patches wrote:
> This commit is a follow up of bugzilla #107181.
> The commit /a0aafbc/ changed the defaul
This patch modifies the way that ix86_expand_int_movcc generates RTL,
to allow the condition mask to be shared/reused between multiple
conditional move sequences. Such redundancy is common when RTL
if-conversion transforms non-trivial basic blocks.
As a motivating example, consider the new test
Hello,
Ping https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606450.html
Thanks,
Lorenzo Salvadore
> From f8e2c2ee89a7d8741bb65163d1f1c20edcd546ac Mon Sep 17 00:00:00 2001
> From: Lorenzo Salvadore develo...@lorenzosalvadore.it
>
> Date: Wed, 16 Nov 2022 11:27:38 +0100
> Subject: [PATCH
Tested on x86_64-linux-gnu, x86_64,aarch64-darwin21.
There remain issues with shared libraries, but the link fails are fixed
by this.
OK for master?
Thanks
Iain
--- 8< ---
In the current design the main executable links explicitly to the module
registration construtors that it uses. This means
When I first made this patch I had a question as to what should be
done for registration CTORs generated by the compiler for .mod files.
I've now answered that question (the code that makes the GCC decl
has also be updated in a separately posted patch).
tested on x86_64-linux-gnu, x86_64, aar
Hi David,
Sorry for the delayed reply!
On 12/16/22 18:01, David Malcolm wrote:
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
OK for trunk?
gcc/rust/ChangeLog:
* resolve/rust-ast-resolve-item.cc (selftest::rust_flatten_list):
Remove output to stderr.
Signed-of
Hi David,
On 12/16/22 18:01, David Malcolm wrote:
Add "make" targets to make it easy to run the rust selftests under gdb
and under valgrind via:
make selftest-rust-gdb
and
make selftest-rust-valgrind
respectively, similar to analogous "make" targets in the C and C++
frontends.
Successfull
* Jeff Law:
> On 11/8/22 11:05, Florian Weimer via Gcc-patches wrote:
>> The sizes are compile-time constants. Create a vector with them,
>> so that they can be inspected at compile time.
>>
>> * gcc/dwarf2cfi.cc (init_return_column_size): Remove.
>> (init_one_dwarf_reg_size): Adjust.
>
On 1/1/23 08:55, Roger Sayle wrote:
In 2011, the rtl.texi documentation was updated to reflect that the
modes of the RTX unary operations FFS, POPCOUNT and PARITY must
match those of their operands. Unfortunately, some of the transformations
in simplify-rtx.cc predate this tightening of RTL s
On Mon, Jan 02, 2023 at 08:45:15AM -0700, Jeff Law via Gcc-patches wrote:
> On 1/1/23 08:55, Roger Sayle wrote:
> > In 2011, the rtl.texi documentation was updated to reflect that the
> > modes of the RTX unary operations FFS, POPCOUNT and PARITY must
> > match those of their operands. Unfortunate
On 1/2/23 08:59, Jakub Jelinek wrote:
On Mon, Jan 02, 2023 at 08:45:15AM -0700, Jeff Law via Gcc-patches wrote:
On 1/1/23 08:55, Roger Sayle wrote:
In 2011, the rtl.texi documentation was updated to reflect that the
modes of the RTX unary operations FFS, POPCOUNT and PARITY must
match those
On Mon, Jan 02, 2023 at 09:20:33AM -0700, Jeff Law wrote:
> > > In fact Raphael and I were about to submit a patch which takes advantage
> > > of
> > > that capability to improve the code slightly for risc-v.
> >
> > Just use a pattern with zero_extend or sign_extend around it or subreg of
> > it
Hi Jeff,
> On 2 Jan 2023, at 15:45, Jeff Law wrote:
> On 1/1/23 08:55, Roger Sayle wrote:
>> In 2011, the rtl.texi documentation was updated to reflect that the
>> modes of the RTX unary operations FFS, POPCOUNT and PARITY must
>> match those of their operands. Unfortunately, some of the trans
On 1/2/23 10:22, Jakub Jelinek wrote:
On Mon, Jan 02, 2023 at 09:20:33AM -0700, Jeff Law wrote:
In fact Raphael and I were about to submit a patch which takes advantage of
that capability to improve the code slightly for risc-v.
Just use a pattern with zero_extend or sign_extend around it o
On 1/2/23 10:30, ro...@nextmovesoftware.com wrote:
Hi Jeff,
On 2 Jan 2023, at 15:45, Jeff Law wrote:
On 1/1/23 08:55, Roger Sayle wrote:
In 2011, the rtl.texi documentation was updated to reflect that the
modes of the RTX unary operations FFS, POPCOUNT and PARITY must
match those of their
From: Ju-Zhe Zhong
Notice that we should used vsetivli zero,4 instead of vsetvli zero,4
for IMM AVL (0 ~ 31) according to RVV ISA.
This patch fix vsetivli instruction asm bug.
gcc/ChangeLog:
* config/riscv/vector.md:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vle-co
Hi,
Andrew Pinski writes:
> On Thu, Dec 29, 2022 at 11:45 PM Segher Boessenkool
> wrote:
>>
>> Hi!
>>
>> On Fri, Dec 30, 2022 at 10:22:31AM +0800, Jiufu Guo wrote:
>> > Considering the limitations of CSE, I try to find other places
>> > to handle this issue, and notice DSE can optimize below
From: Ju-Zhe Zhong
Currently we support this optimization:
bb 0:
vsetvli a5,zero,e32,mf2
bb 1:
vsetvli a5,zero,e64,m1 --> vsetvli zero,zero,e64,m1
According RVV ISA, we can do this optimization only if both RATIO and AVL are
equal.
However, current VSETVL PASS missed the check of AVL. This p
From: Ju-Zhe Zhong
Since we only change insn which is not in group. The flag currently is not
correct.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (change_insn): Adjust in_group in
validate_change.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
1 file changed, 1 insertion(+), 1 dele
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (loop_basic_block_p): Adjust function.
(backward_propagate_worthwhile_p): Fix non-worthwhile.
---
gcc/config/riscv/riscv-vsetvl.cc | 91 +---
1 file changed, 71 insertions(+), 20 deleti
From: Ju-Zhe Zhong
This patch is NFC patch. I move these code as a function since we will
reuse it in the following patch (Refine phase 3 of VSETVL PASS)
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (change_vsetvl_insn): New function.
(pass_vsetvl::compute_global_backward_infos
From: Ju-Zhe Zhong
Suppose there are 2 demand infos:
Demand 1: demand TAIL.
Demand 2: not demand TAIL.
If a block is demand 1, we should adjust this block is available both for
demand 1 && 2.
However, if a block is demand 2, we should only adjust this block is available
for demand 2 only.
gc
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