Re: Adding a new thread model to GCC

On 10/31/22 15:22, i.nixman--- via Gcc-patches wrote: On 2022-10-31 09:18, Eric Botcazou wrote: Hi Eric! thank you very much for the job! I will try to build our (MinGW-Builds project) builds using this patch and will report back. @Jonathan what the next steps to be taken to accept this pat

[r13-4764 Regression] FAIL: gfortran.dg/pr107397.f90 -O (test for excess errors) on Linux/x86_64

On Linux/x86_64, 09710f9934969dcb07131e1ed78b72e648123a3a is the first bad commit commit 09710f9934969dcb07131e1ed78b72e648123a3a Author: Steve Kargl Date: Sat Dec 17 19:15:43 2022 -0800 Add a check for invalid use of BOZ with a derived type. caused FAIL: gfortran.dg/pr107397.f90 -O

[PATCH v2 01/11] riscv: attr: Synchronize comments with code

From: Christoph Müllner The comment above the enumeration of existing attributes got out of order and a few entries were forgotten. This patch synchronizes the comments according to the list. This commit does not include any functional change. gcc/ChangeLog: * config/riscv/riscv.md: Syn

[PATCH v2 00/11] RISC-V: Add XThead* extension support

From: Christoph Müllner This series introduces support for the T-Head specific RISC-V ISA extensions which are available e.g. on the T-Head XuanTie C906. The ISA spec can be found here: https://github.com/T-head-Semi/thead-extension-spec The series begins with two preparation patches, that do

[PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code

From: Christoph Müllner This patch restructures the loop over the GP registers which saves/restores then as part of the prologue/epilogue. No functional change is intended by this patch, but it offers the possibility to use load-pair/store-pair instructions. gcc/ChangeLog: * config/risc

[PATCH v2 04/11] riscv: riscv-cores.def: Add T-Head XuanTie C906

From: Christoph Müllner This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". The C906 is shipped for quite some time (it is the core of the Allwinner D1). Note, that the tuning struct for the C906 is already part of GCC (it is also name "thead-c906"). gcc/ChangeLog:

[PATCH v2 06/11] riscv: thead: Add support for the XTheadBs ISA extension

From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The new INSN pattern is defined in a new file to separate this vendor extension from the standard extensions. The cost model adjustment reuses the xbs:bext cost. gcc/ChangeLog: * config/riscv/riscv.cc (riscv

[PATCH v2 07/11] riscv: thead: Add support for th XTheadBb ISA extension

From: Christoph Müllner This patch adds support for the XTheadBb ISA extension. Thus, there is a functional overlap of the new instructions with existing Bitmanip instruction, which allows a good amount of code sharing. However, the vendor extensions are cleanly separated from the standard extens

[PATCH v2 03/11] riscv: Add basic XThead* vendor extension support

From: Christoph Müllner This patch add basic support for the following XThead* ISA extensions: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadInt * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The extensions are just recognized by the c

[PATCH v2 05/11] riscv: thead: Add support for the XTheadBa ISA extension

From: Christoph Müllner This patch adds support for the XTheadBa ISA extension. The new INSN pattern is defined in a new file to separate this vendor extension from the standard extensions. gcc/ChangeLog: * config/riscv/riscv.md: Include thead.md * config/riscv/thead.md: New fil

[PATCH v2 08/11] riscv: thead: Add support for XTheadCondMov ISA extensions

From: Christoph Müllner This patch adds support for XTheadCondMov ISA extension. The extension brings a one-sided conditional move (no else-assignment). Given that GCC has a great if-conversion pass, we don't need to do much, besides properly expanding movcc accordingly and adjust the cost model.

[PATCH v2 09/11] riscv: thead: Add support for XTheadMac ISA extension

From: Christoph Müllner The XTheadMac ISA extension provides multiply-accumulate/subtract instructions: * mula/mulaw/mulah * muls/mulsw/mulsh To benefit from middle-end passes, we expand the following named patterns in riscv.md (as they are not T-Head-specific): * maddhisi4 * msubhisi4 gcc/Chan

[PATCH v2 10/11] riscv: thead: Add support for XTheadFmv ISA extension

From: Christoph Müllner The XTheadFmv ISA extension provides instructions to move data between 32-bit GP registers and 64-bit FP registers. gcc/ChangeLog: * config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS) New constraint "th_f_fmv". (TARGET_XTHEADFMV ?

[PATCH v2 11/11] riscv: thead: Add support for XTheadMemPair ISA extension

From: "moiz.hussain" The XTheadMemPair ISA extension provides load/store pair instructions: * th.ldd * th.sdd * th.lwd * th.lwud * th.swd This patch adds the following unnamed patterns to the peephole.md stage, which take care of reordering loads/stores appropriately: * load/store pair patterns

Re: [PATCH v2 01/11] riscv: attr: Synchronize comments with code

LGTM, you can commit this separately if you want :) On Mon, Dec 19, 2022 at 9:09 AM Christoph Muellner wrote: > > From: Christoph Müllner > > The comment above the enumeration of existing attributes got out of > order and a few entries were forgotten. > This patch synchronizes the comments accor

Re: [PATCH] RISC-V: Add testcases for VSETVL PASS

Hi Jeff: > Ah, I should have looked at those regexps closer. Understood about the > checking for hoisting the vsetvl. Though it makes me wonder if we'd be > better off dumping information out of the vsetvl pass. I've discussed adding an extra verify pass and a kind of rating mechnish to vsetvl

[RFC/RFT 0/3] Add compiler support for Control Flow Integrity

This series of patches is mainly used to support the control flow integrity protection of the linux kernel [1], which is similar to -fsanitize=kcfi in clang 16.0 [2,3]. I hope that this feature will also support user-mode CFI in the future (at least for developers who can recompile the runtime), s