Ping: [PATCH] d: Update __FreeBSD_version values [PR107469]

Hello, Ping https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605685.html I would like to remind that Gerald Pfeifer already volunteered to commit this patch when it is approved. However the patch has not been approved yet. Thanks, Lorenzo Salvadore --- Original Message --- On

Re: [PATCH] rtl: add predicates for addition, subtraction & multiplication

On Sat, 2022-11-26 at 21:16 -0500, Charlie Sale via Gcc-patches wrote: > This is my first contribution to GCC :) one of the beginner projects > suggested on the website was to add and use RTL type predicates. I > added predicates for addition, subtraction and multiplication. I also > went through a

[RFA] src-release.sh: Fix gdb source tarball build failure due to libsframe

Hello, This script was recently changed as follow: | commit e619dddb3a45780ae66d762756882a3b896b617d | Date: Tue Nov 15 15:07:13 2022 -0800 | Subject: src-release.sh: Add libsframe | | Add libsframe to the list of top level directories that will be included | in a releas

Re: [PATCH]rs6000: Load high and low part of 64bit constant independently

Hi Segher! Thanks for your helpful comments! Segher Boessenkool writes: > Hi! > > On Fri, Nov 25, 2022 at 09:21:21PM +0800, Jiufu Guo wrote: >> "Kewen.Lin" writes: >> > on 2022/9/15 16:30, Jiufu Guo wrote: >> >> For a complicate 64bit constant, blow is one instruction-sequence to >> >> build

Re: [PATCH v2 16/19] modula2 front end: bootstrap and documentation tools

David Malcolm writes: >> Once modula-2 is in master I'd like to revisit rst in devel/modula-2 >> along with analyzer patches and m2 generics.  If successful then >> submit >> patches in early stage 1. > > Am I right in thinking the analyzer stuff would be an updated version > of the work you post

[PATCH v2] RISC-V: Add support for AIA ISA extensions (Ssaia and Smaia)

From: Christoph Müllner This patch adds support for the two AIA ISA extensions Ssaia and Smaia. They are not relelvant for the compiler, but the assembler might want to validate the CSRs. Therefore, all this patch does is recognize the extension name, emit a feature macro (incl. a test). Changes

Re: [PATCH] RISC-V: Add support for AIA ISA extensions (Ssaia and Smaia)

On Fri, Nov 18, 2022 at 10:08 AM Christoph Müllner wrote: > > > > On Fri, Nov 18, 2022 at 6:09 AM Palmer Dabbelt wrote: >> >> On Thu, 17 Nov 2022 18:12:23 PST (-0800), christoph.muell...@vrull.eu wrote: >> > From: Christoph Müllner >> > >> > This patch adds support for the two AIA ISA extensions

Re: [Patch] OpenMP/Fortran: Permit end-clause on directive

Updated patch – taking the comments below into account – and the remark by Harald, second by Jakub. Namely: I have now split the pre-existing nowait-2.f90 into nowait-2.f90 (with only valid usage) and nowait-4.f90 (with the dg-error tests). In the previous version of the patch, nowait-4.f90 was a

Re: [PATCH 1/2] rs6000: Emit vector fp comparison directly in rs6000_emit_vector_compare

Hi! Whoops I missed following up to this. On Mon, Nov 21, 2022 at 10:01:14AM +0800, Kewen.Lin wrote: > on 2022/11/18 23:10, Segher Boessenkool wrote: > > ge is nasty for float, it means something different with and without > > -ffast-math (with fast-math ge means not lt, le means not gt; both can

[PATCH] Fortran: ICE with elemental and dummy argument with VALUE attribute [PR107819]

Dear Fortranners, in dependency checking of arguments of elemental prodecures we should treat dummy arguments with the value attribute as implicitly having intent(in). This is simple and obvious. The PR by Gerhard provides a series of testcases that are either valid (like the one in the attached

Re: [PATCH]rs6000: Load high and low part of 64bit constant independently

Hi Segher, on 2022/11/25 23:46, Segher Boessenkool wrote: > Hi! > > On Fri, Nov 25, 2022 at 09:21:21PM +0800, Jiufu Guo wrote: >> "Kewen.Lin" writes: >>> on 2022/9/15 16:30, Jiufu Guo wrote: For a complicate 64bit constant, blow is one instruction-sequence to build: lis 9,0x800

[PATCH] RISC-V: Support the ins "rol" with immediate operand

From: wangfeng There is no Immediate operand of ins "rol" accroding to the B-ext, so the immediate operand should be loaded into register at first. But we can convert it to the ins "rori" or "roriw", and then one immediate load ins can be reduced. Please refer to the following use cases: unsigne

Re: [PATCH]rs6000: Load high and low part of 64bit constant independently

Hi Kewen/Segher, Thanks a lot for your review! I updated the patch accordingly as below for message/code/testcase: For a complicate 64bit constant, blow is one instruction-sequence to build: lis 9,0x800a ori 9,9,0xabcd sldi 9,9,32 oris 9,9,0xc167 ori 9,9

Re: [pushed][PATCH v4] LoongArch: Optimize immediate load.

Pushed r13-4315. 在 2022/11/23 上午12:44, Xi Ruoyao 写道: On Tue, 2022-11-22 at 22:03 +0800, Xi Ruoyao via Gcc-patches wrote: While I still can't fully understand the immediate load issue and how this patch fix it, I've tested this patch (alongside the prefetch instruction patch) with bootstrap-ubsa

Re: [PATCH] vect: Fold LEN_{LOAD, STORE} if it's for the whole vector [PR107412]

Hi Richard, on 2022/11/24 17:24, Richard Sandiford wrote: > "Kewen.Lin" writes: >> Hi, >> >> As the test case in PR107412 shows, we can fold IFN .LEN_{LOAD, >> STORE} into normal vector load/store if the given length is known >> to be equal to the length of the whole vector. It would help to >>

Re: [PATCH 0/2] Support HWASAN with Intel LAM

On Fri, Nov 11, 2022 at 9:26 AM liuhongt wrote: > > 2 years ago, ARM folks support HWASAN[1] in GCC[2], and introduced several > target hooks(Many thanks to their work) so other backends can do similar > things if they have similar feature. > Intel LAM(linear Address Masking)[3 Charpter 14] su

Re: [PATCH V2] rs6000: Support to build constants by li/lis+oris/xoris

Hi Segher! Thanks a lot for your comments! Segher Boessenkool writes: > Hi guys, > > On Fri, Nov 25, 2022 at 04:11:49PM +0800, Kewen.Lin wrote: >> on 2022/10/26 19:40, Jiufu Guo wrote: >> for "li/lis + oris/xoris", I interpreted it into four combinations: >> >>li + oris, lis + oris, li + x

[PATCH 0/1] RISC-V: fix stack access before allocation.

In current riscv stack frame allocation, 2 steps are used. The first step allocates memories at least for callee saved GPRs and FPRs, and the second step allocates the rest if stack size is greater than signed 12-bit range. But it's observed in some cases, like gcc.target/riscv/stack_frame.c in

[PATCH 1/1] RISC-V: fix stack access before allocation.

In current riscv stack frame allocation, 2 steps are used. The first step allocates memories at least for callee saved GPRs and FPRs, and the second step allocates the rest if stack size is greater than signed 12-bit range. But it's observed in some cases, like gcc.target/riscv/stack_frame.c in

[PATCH 0/1] RISC-V: fix stack access before allocation.

In current riscv stack frame allocation, 2 steps are used. The first step allocates memories at least for callee saved GPRs and FPRs, and the second step allocates the rest if stack size is greater than signed 12-bit range. But it's observed in some cases, like gcc.target/riscv/stack_frame.c in

[PATCH 1/1] RISC-V: fix stack access before allocation.

In current riscv stack frame allocation, 2 steps are used. The first step allocates memories at least for callee saved GPRs and FPRs, and the second step allocates the rest if stack size is greater than signed 12-bit range. But it's observed in some cases, like gcc.target/riscv/stack_frame.c in

Ping [PATCH] Change the behavior of predicate check failure on cbranchcc4 operand0 in prepare_cmp_insn

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2022-November/607083.html Thanks Gui Haochen 在 2022/11/23 10:54, HAO CHEN GUI 写道: > Hi, > I want to enable "have_cbranchcc4" on rs6000. But not all combinations of > comparison codes and sub CC modes are benefited to generate cbr

[PATCH][_GLIBCXX_INLINE_VERSION] Adapt dg error messages

libstdc++: [_GLIBCXX_INLINE_VERSION] Adapt dg error messages libstdc++-v3/ChangeLog     * testsuite/20_util/bind/ref_neg.cc: Adapt dg-prune-output message.     * testsuite/20_util/function/cons/70692.cc: Adapt dg-error message. Ok to commit ? François diff --git a/libstdc++-v3/testsuit

[PATCH][_GLIBCXX_INLINE_VERSION] Adapt to_chars/from_chars symbols

This patch is fixing those tests: 20_util/to_chars/float128_c++23.cc std/format/formatter/requirements.cc std/format/functions/format.cc std/format/functions/format_to_n.cc std/format/functions/size.cc std/format/functions/vformat_to.cc std/format/string.cc Note that symbols used in for __ibm12

Re: [PATCH] Change the behavior of predicate check failure on cbranchcc4 operand0 in prepare_cmp_insn

Add more experts in CC. on 2022/11/23 10:54, HAO CHEN GUI wrote: > Hi, > I want to enable "have_cbranchcc4" on rs6000. But not all combinations of > comparison codes and sub CC modes are benefited to generate cbranchcc4 insns > on rs6000. There is an predicate for operand0 of cbranchcc4 to bypas

Re: [PATCH 0/2] Support HWASAN with Intel LAM

On Mon, Nov 28, 2022 at 4:35 AM Hongtao Liu wrote: > > On Fri, Nov 11, 2022 at 9:26 AM liuhongt wrote: > > > > 2 years ago, ARM folks support HWASAN[1] in GCC[2], and introduced several > > target hooks(Many thanks to their work) so other backends can do similar > > things if they have similar

[Patch] gcn: Fix __builtin_gcn_first_call_this_thread_p

It turned out that cprop cleverly propagated the unspec_volatile to the preceding (pseudo)register, permitting to remove the 'set (s0) (pseudoregister)' at -O2. Unfortunately, it does matter whether the assignment is done to 's2' (previously: pseudoregister) or to s1. – Just having a hard registe

Re: [PATCH V2] rs6000: Support to build constants by li/lis+oris/xoris

Jiufu Guo via Gcc-patches writes: > Hi Segher! > > Thanks a lot for your comments! > > Segher Boessenkool writes: > >> Hi guys, >> >> On Fri, Nov 25, 2022 at 04:11:49PM +0800, Kewen.Lin wrote: >>> on 2022/10/26 19:40, Jiufu Guo wrote: >>> for "li/lis + oris/xoris", I interpreted it into four com

[PATCH] tree-optimization/107867 - failed abnormal cleanup in forwprop

The following makes sure to perform abnormal cleanup when forwprop propagates into a call. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/107867 * tree-ssa-forwprop.cc (pass_forwprop::execute): Handle abnormal cleanup after substitution.