Re: [PATCH] lower-subreg, expr: Mitigate inefficiencies derived from "(clobber (reg X))" followed by "(set (subreg (reg X)) (...))"

Takayuki 'January June' Suwa via Gcc-patches writes: > Emitting "(clobber (reg X))" before "(set (subreg (reg X)) (...))" keeps > data flow consistent, but it also increases register allocation pressure > and thus often creates many unwanted register-to-register moves that > cannot be optimized aw

RE: [PATCH 2/2]middle-end: Support recognition of three-way max/min.

> -Original Message- > From: Richard Biener > Sent: Tuesday, August 2, 2022 10:11 AM > To: Tamar Christina > Cc: Richard Biener ; ja...@redhat.com; nd > ; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH 2/2]middle-end: Support recognition of three-way > max/min. > > On Tue, Aug 2, 2022 at

[PATCH, rs6000] TARGET_MADDLD should include TARGET_POWERPC64

Hi, This patch changes the definition of TARGET_MADDLD and includes TARGET_POWERPC64, since maddld is a 64 bit instruction. maddld-1.c now checks "has_arch_ppc64". It depends on a patch which fixes empty TU problem. https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598744.html Bootstrappe

RE: [PATCH 2/2]middle-end: Support recognition of three-way max/min.

On Wed, 3 Aug 2022, Tamar Christina wrote: > > > -Original Message- > > From: Richard Biener > > Sent: Tuesday, August 2, 2022 10:11 AM > > To: Tamar Christina > > Cc: Richard Biener ; ja...@redhat.com; nd > > ; gcc-patches@gcc.gnu.org > > Subject: Re: [PATCH 2/2]middle-end: Support rec

RE: [PATCH] x86: Enable __bf16 type for TARGET_SSE2 and above

Hi, Old patch has some mistake in `*movbf_internal` , now disable BFmode constant double move in `*movbf_internal`. Thanks, Lingling > -Original Message- > From: Kong, Lingling > Sent: Tuesday, July 26, 2022 9:31 AM > To: Liu, Hongtao ; gcc-patches@gcc.gnu.org > Cc: Kong, Lingling > S

Re: [PATCH] IPA: reduce what we dump in normal mode

On 8/2/22 18:27, Jan Hubicka wrote: > If you disable dumping, you can also disable the collection of stats > which is guarded by if (dump_file) as well. Otherwise the patch is OK. Sure, good point! I'm going to push the following. Thanks, MartinFrom 7585e5ecb47761516b8f397002819f2c95b8c32e Mon

Re: [PATCH v2] cselib: add function to check if SET is redundant [PR106187]

On 03/08/2022 00:36, Jeff Law wrote: On 8/2/2022 10:06 AM, Richard Earnshaw wrote: On 01/08/2022 11:38, Richard Earnshaw via Gcc-patches wrote: On 30/07/2022 20:57, Jeff Law via Gcc-patches wrote: On 7/29/2022 7:52 AM, Richard Earnshaw via Gcc-patches wrote: A SET operation that wri

Re: [PATCH, rs6000] TARGET_MADDLD should include TARGET_POWERPC64

Hi Haochen, on 2022/8/3 16:24, HAO CHEN GUI wrote: > Hi, > This patch changes the definition of TARGET_MADDLD and includes > TARGET_POWERPC64, since maddld is a 64 bit instruction. > > maddld-1.c now checks "has_arch_ppc64". It depends on a patch which fixes > empty TU problem. > https://gcc.

[PATCH] backwards threader costing TLC and a fix

The previous change to the backwards threader costing contained a mistake that can make us reject a path based on size when the full thread path is not know yet and the full path would be considered hot but the partial path not yet. Instead of adding another simple fix for this particular issue I

[PATCH] Backwards threader greedy search TLC

I've tried to understand how the greedy search works seeing the bitmap dances and the split into resolve_phi. I've summarized the intent of the algorithm as // For further greedy searching we want to remove interesting // names defined in BB but add ones on the PHI edges for the

[PATCH] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU

We produce inefficient code for some synthesized SImode conditional set operations (i.e. ones that are not directly implemented in hardware) on RV64. For example a piece of C code like this: int sleu (unsigned int x, unsigned int y) { return x <= y; } gets compiled (at `-O2') to this: sleu:

Re: [PATCH] Properly honor param_max_fsm_thread_path_insns in backwards threader

On Tue, 2 Aug 2022, Jan Hubicka wrote: > > On Tue, 2 Aug 2022, Aldy Hernandez wrote: > > > > > On Tue, Aug 2, 2022 at 1:45 PM Richard Biener wrote: > > > > > > > > On Tue, 2 Aug 2022, Aldy Hernandez wrote: > > > > > > > > > Unfortunately, this was before my time, so I don't know. > > > > > > > >

[PATCH] PR106342 - IBM zSystems: Provide vsel for all vector modes

Bootstrapped and regtested on s390x-redhat-linux. Ok for master? dg.exp=pr104612.c fails with an ICE on s390x, because copysignv2sf3 produces an insn that vsel is supposed to recognize, but can't, because it's not defined for V2SF. Fix by defining it for all vector modes supported by copysign3

Re: [PATCH] lower-subreg, expr: Mitigate inefficiencies derived from "(clobber (reg X))" followed by "(set (subreg (reg X)) (...))"

Thanks for your response. On 2022/08/03 16:52, Richard Sandiford wrote: > Takayuki 'January June' Suwa via Gcc-patches writes: >> Emitting "(clobber (reg X))" before "(set (subreg (reg X)) (...))" keeps >> data flow consistent, but it also increases register allocation pressure >> and thus often

Re: [PATCH] RFC: Extend SLP permutation optimisations

On Tue, 2 Aug 2022, Richard Sandiford wrote: > Currently SLP tries to force permute operations "down" the graph > from loads in the hope of reducing the total number of permutes > needed or (in the best case) removing the need for the permutes > entirely. This patch tries to extend it as follows:

Re: [PATCH] configure: respect --with-build-time-tools [PR43301]

On Tue, Aug 2, 2022 at 11:33 PM Alexandre Oliva wrote: > > On Aug 2, 2022, Eric Gallager wrote: > > > On Tue, Aug 2, 2022 at 1:24 AM Alexandre Oliva wrote: > > >> -elif test -x as$build_exeext; then > >> +elif test -x as$build_exeext \ > >> + && { test "x$build_exeext" != "x" \ > >> +

[PATCH] middle-end: Allow backend to expand/split double word compare to 0/-1.

This patch to the middle-end's RTL expansion reorders the code in emit_store_flag_1 so that the backend has more control over how best to expand/split double word equality/inequality comparisons against zero or minus one. With the current implementation, the middle-end always decides to lower thi

[committed] libstdc++: Avoid try-catch and O(N) size in std::list::merge for old ABI

Tested x86_64-linux, pushed to gcc-10 branch. -- >8 -- The current std::list::merge code calls size() before starting to merge any elements, so that the _M_size members can be updated after the merge finishes. The work is done in a try-block so that the sizes can still be updated in an exception

Re: [Patch] OpenMP, libgomp, gimple: omp_get_max_teams, omp_set_num_teams, and omp_{gs}et_teams_thread_limit on offload devices

Hi Jakub, This patch was reduced a bit and most of your comments were considered in the last submission of the environment variable syntax extension patch (https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599175.html). This patch also builds on that envvar patch version. The nteams-var rela

Re: [PATCH] PR106342 - IBM zSystems: Provide vsel for all vector modes

On 8/3/22 12:20, Ilya Leoshkevich wrote: > Bootstrapped and regtested on s390x-redhat-linux. Ok for master? > > > > dg.exp=pr104612.c fails with an ICE on s390x, because copysignv2sf3 > produces an insn that vsel is supposed to recognize, but can't, > because it's not defined for V2SF. Fix by

Re: [09/23] Add a cut-down version of std::span (array_slice)

Hi Richard, On Fri, Nov 13 2020, Richard Sandiford via Gcc-patches wrote: > A later patch wants to be able to pass around subarray views of an > existing array. The standard class to do that is std::span, but it's > a C++20 thing. This patch just adds a cut-down version of it. thanks a lot for

RE: [PATCH 1/2]middle-end: Simplify subtract where both arguments are being bitwise inverted.

> -Original Message- > From: Richard Biener > Sent: Tuesday, June 21, 2022 8:43 AM > To: Tamar Christina > Cc: Richard Sandiford ; Richard Biener via Gcc- > patches ; Richard Guenther > ; nd > Subject: Re: [PATCH 1/2]middle-end: Simplify subtract where both > arguments are being bitwise

Re: [09/23] Add a cut-down version of std::span (array_slice)

Martin Jambor writes: > Hi Richard, > > On Fri, Nov 13 2020, Richard Sandiford via Gcc-patches wrote: >> A later patch wants to be able to pass around subarray views of an >> existing array. The standard class to do that is std::span, but it's >> a C++20 thing. This patch just adds a cut-down ve

[COMMITED] testsuite: btf: fix regexps in btf-int-1.c

The regexps in hte test btf-int-1.c were not working properly with the commenting style of at least one target: powerpc64le-linux-gnu. This patch changes the test to use better regexps. Tested in bpf-unkonwn-none, x86_64-linux-gnu and powerpc64le-linux-gnu. Pushed to master as obvious. gcc/tes

Re: [PATCH, rs6000] TARGET_MADDLD should include TARGET_POWERPC64

Hi! On Wed, Aug 03, 2022 at 04:24:15PM +0800, HAO CHEN GUI wrote: > This patch changes the definition of TARGET_MADDLD and includes > TARGET_POWERPC64, since maddld is a 64 bit instruction. Hrm. But the maddld insn is useful for SImode as well, in 32-bit mode, it is just its name that is a bit

Re: [PATCH] lower-subreg, expr: Mitigate inefficiencies derived from "(clobber (reg X))" followed by "(set (subreg (reg X)) (...))"

On 8/3/2022 1:52 AM, Richard Sandiford via Gcc-patches wrote: Takayuki 'January June' Suwa via Gcc-patches writes: Emitting "(clobber (reg X))" before "(set (subreg (reg X)) (...))" keeps data flow consistent, but it also increases register allocation pressure and thus often creates many unw

Re: [PATCH] stack-protector: Check stack canary for noreturn function

On Tue, Aug 2, 2022 at 4:34 PM Jeff Law wrote: > > > > On 8/2/2022 11:43 AM, H.J. Lu wrote: > > On Sat, Jul 30, 2022 at 1:30 PM Jeff Law via Gcc-patches > > wrote: > >> > >> > >> On 7/14/2022 3:55 PM, H.J. Lu via Gcc-patches wrote: > >>> Check stack canary for noreturn function to catch stack cor

Ping: [PATCH, V2] Do not enable -mblock-ops-vector-pair.

Ping patch. | Date: Mon, 25 Jul 2022 16:15:05 -0400 | Subject: [PATCH, V2] Do not enable -mblock-ops-vector-pair. | Message-ID: -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Ping: [PATCH 0/5] IEEE 128-bit built-in overload support.

Ping patches. Patch #1 of 5. | Date: Thu, 28 Jul 2022 00:47:13 -0400 | Subject: [PATCH 1/5] IEEE 128-bit built-in overload support. | Message-ID: Patch #2 of 5. | Date: Thu, 28 Jul 2022 00:48:51 -0400 | Subject: [PATCH 2/5] Support IEEE 128-bit overload round_to_odd built-in functions. | Messag

HELP!!How to add a testing case to check a compilation time warning for "cc1"

Hi, My private cc1 issued the following warning: [opc@qinzhao-ol8u3-x86 gcc]$ sh t cc1: warning: ‘-fstrict-flex-arrays’ is not supported with a ISO C before C99, ignored I’d like to add a testing case for this warning into gcc.dg directory, however, I cannot find a proper testing directive to

Re: HELP!!How to add a testing case to check a compilation time warning for "cc1"

Never mind, just found how to do this: /* { dg-warning "'-fstrict-flex-arrays' is not supported with a ISO C before C99, ignored" "" { target *-*-* } 0 } */ And worked. thanks. Qing > On Aug 3, 2022, at 2:52 PM, Qing Zhao via Gcc-patches > wrote: > > Hi, > > My private cc1 issued the foll

[PATCH] match.pd: Add bitwise and pattern [PR106243]

This patch adds a new optimization to match.pd. The pattern, -x & 1, now gets simplified to x & 1, reducing the number of instructions produced. This patch also adds tests for the optimization rule. Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? PR tree-optimization/106243

[COMMITTED] tree-optimization/106514 - Do not walk equivalence set in path_oracle::killing_def.

The path oracles killing_def () routine was removing an ssa-name from each equivalence in the set.  This was busy work that did not need to be done. when checking for an equivalence between A and B, the path oracle requires that A be in B's set and B be in A's set.  By setting the equivalence

Re: [PATCH, V2] Do not enable -mblock-ops-vector-pair.

Hi Mike, On Mon, Jul 25, 2022 at 04:15:05PM -0400, Michael Meissner wrote: > Testing has shown that using the load vector pair and store vector pair > instructions for block moves has some performance issues on power10. > This patch eliminates the code setting -mblock-ops-vector-pair. If you > w

Re: [PATCH 2/2]middle-end: Support recognition of three-way max/min.

On Wed, Aug 3, 2022 at 1:26 AM Richard Biener via Gcc-patches wrote: > > On Wed, 3 Aug 2022, Tamar Christina wrote: > > > > > > -Original Message- > > > From: Richard Biener > > > Sent: Tuesday, August 2, 2022 10:11 AM > > > To: Tamar Christina > > > Cc: Richard Biener ; ja...@redhat.com

Re: [PATCH] match.pd: Add bitwise and pattern [PR106243]

On Thu, 4 Aug 2022 at 00:41, Sam Feifer via Gcc-patches wrote: > > This patch adds a new optimization to match.pd. The pattern, -x & 1, > now gets simplified to x & 1, reducing the number of instructions > produced. Hi Sam, No comments on patch, but wondering if we can similarly add another patter

Re: [PATCH] match.pd: Add bitwise and pattern [PR106243]

On 8/3/2022 2:44 PM, Prathamesh Kulkarni via Gcc-patches wrote: On Thu, 4 Aug 2022 at 00:41, Sam Feifer via Gcc-patches wrote: This patch adds a new optimization to match.pd. The pattern, -x & 1, now gets simplified to x & 1, reducing the number of instructions produced. Hi Sam, No comments

RE: [PING][PATCH] Add instruction level discriminator support.

One more ping for this patch https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596065.html CC Jason since this changes discriminators emitted in dwarf. Thanks, Eugene -Original Message- From: Eugene Rozenfeld Sent: Monday, June 27, 2022 12:45 PM To: gcc-patches@gcc.gnu.org; Andi Kle

Re: [PATCH, rs6000] TARGET_MADDLD should include TARGET_POWERPC64

Hi Segher, On 4/8/2022 上午 12:54, Segher Boessenkool wrote: > Hrm. But the maddld insn is useful for SImode as well, in 32-bit mode, > it is just its name that is a bit confusing then. Sorry for confusing > things :-( > > Add a test for SImode maddld as well? Thanks for your comments. Just w

[r13-1950 Regression] FAIL: gfortran.dg/make_unit.f90 -O1 (test for excess errors) on Linux/x86_64

On Linux/x86_64, 9bb19e143cfe8863e2e79d4176b5d7e997b08c5f is the first bad commit commit 9bb19e143cfe8863e2e79d4176b5d7e997b08c5f Author: Tamar Christina Date: Wed Aug 3 16:00:39 2022 +0100 middle-end: Support recognition of three-way max/min. caused FAIL: gcc.dg/analyzer/pr96653.c (inte

[RFC: PATCH] Extend vectorizer to handle nonlinear induction for neg, mul/lshift/rshift with a constant.

For neg, the patch create a vec_init as [ a, -a, a, -a, ... ] and no vec_step is needed to update vectorized iv since vf is always multiple of 2(negative * negative is positive). For shift, the patch create a vec_init as [ a, a >> c, a >> 2*c, ..] as vec_step as [ c * nunits, c * nunits, c * nuni

Re: [PATCH] x86: Enable __bf16 type for TARGET_SSE2 and above

On Wed, Aug 3, 2022 at 4:41 PM Kong, Lingling via Gcc-patches wrote: > > Hi, > > Old patch has some mistake in `*movbf_internal` , now disable BFmode constant > double move in `*movbf_internal`. LGTM. > > Thanks, > Lingling > > > -Original Message- > > From: Kong, Lingling > > Sent: Tues

RE: [PATCH 1/2]middle-end: Simplify subtract where both arguments are being bitwise inverted.

On Wed, 3 Aug 2022, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Tuesday, June 21, 2022 8:43 AM > > To: Tamar Christina > > Cc: Richard Sandiford ; Richard Biener via Gcc- > > patches ; Richard Guenther > > ; nd > > Subject: Re: [PATCH 1/2]middle-end: