Hello Iain,
> On 20 Aug 2020, at 14:54, Iain Buclaw wrote:
>
>> We have a batch of vxworks changes queued that we will be submitting soon,
>> and we might get to rationalize this with other places along the way.
>>
>
> Running the build through one more time, and I've noticed that the make
> r
OG10 = devel/omp/gcc-10 – a GCC 10 branch with some additional
OpenMP/OpenACC/offloading patches
Commits:
* 16052969a54db5df3d37fdcc81acba6ed1ec8c6a
moved OG10 ChangeLog items to ChangeLog.omp
* 612fee635bbb1198bc550c9c328330cae3259ed5
Merged origin/releases/gcc-10 into branch
* f99ec65aea0d
xiezhiheng writes:
>> -Original Message-
>> From: Richard Sandiford [mailto:richard.sandif...@arm.com]
>> Sent: Thursday, August 20, 2020 4:55 PM
>> To: xiezhiheng
>> Cc: Richard Biener ; gcc-patches@gcc.gnu.org
>> Subject: Re: [PATCH PR94442] [AArch64] Redundant ldp/stp instructions
>> e
Hi Palmer,
The 64-bit RISC-V Linux port has a minimum of 39-bit virtual addresses, so it
should be 1<<36 for 64-bit targets. In the implementation of address sanitizer,
we need a shadow memory that is 1/8th of the memory size, which is
where the 36 comes from. I don't think the choice of this va
Hi Martin,
> Hi,
>
> On Thu, Aug 20 2020, Richard Sandiford wrote:
> >>
> >>
> >> Really appreciate for your detailed explanation. BTW, My previous
> >> patch for PGO build on exchange2 takes this similar method by setting
> >> each cloned node to 1/10th of the frequency several month agao :)
>
Alex Coplan writes:
> Hi Richard,
>
>> -Original Message-
>> From: Richard Sandiford
>> Sent: 18 August 2020 09:35
>> To: Alex Coplan
>> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw ;
>> Marcus Shawcroft ; Kyrylo Tkachov
>>
>> Subject: Re: [PATCH] aarch64: Don't generate invalid zero/s
Hongtao Liu via Gcc-patches writes:
> ping ^ 4, it's a very simple fix for ICE.
OK, thanks. (Reviewing on the basis that I agree it's a simple rtx
correctness fix.)
Richard
>
> On Mon, Aug 10, 2020 at 6:00 PM Hongtao Liu wrote:
>>
>> Ping^3
>>
>> On Tue, Aug 4, 2020 at 4:21 PM Hongtao Liu wr
Pip Cet writes:
>> Pip Cet via Gcc-patches writes:
>> > I'm working on the AVR cc0 -> CCmode conversion (bug#92729). One
>> > problem is that the cmpelim pass is currently very strict in requiring
>> > insns of the form
>> >
>> > (parallel [(set (reg:SI) (op:SI ... ...))
>> >(clobber
Hi all!
Proposed patch to PR95352 - ICE on select rank with assumed-size
selector and lbound intrinsic.
Patch tested only on x86_64-pc-linux-gnu.
Add check for NULL pointer before trying to access structure member,
patch by Steve Kargl.
Thank you very much.
Best regards,
José Rui
2020-8
These tests do not actually require TBB, because they only inspect the
feature test macros present in the headers. However, if TBB is installed
then its headers will be included, and the version will be checked. If
the version is too old, compilation fails due to a #error directive.
This change di
On 8/21/20 9:55 AM, Tobias Burnus wrote:
* c0db5b424d33577e633895c9c430bc1626336fb5
Backport of 'Fortran: Fix OpenMP's 'if(simd:' etc. conditions'
Missed that OG10 has changed the warning to an error;
this could be also something for the trunk, matching C/C++
which does print an error ...
To
On Wed, 2020-08-19 at 09:24 +0200, Andrea Corallo wrote:
> Hi all,
>
> just a small patch updating some comments that apparently went out of
> sync a while ago adding gcc_jit_context_new_rvalue_from_long.
> Okay for trunk?
Yes
Thanks for fixing these
Dave
On Dec 20, 2019, Jonathan Wakely wrote:
> On 10/12/19 15:58 +0100, Corentin Gay wrote:
>> This patch was tested on x86_64-linux and is part of our nightly testing
>> on all platforms, including VxWorks.
> Was it tested on AIX?
> I think dg-require-gthreads will prevent the tests running for the
This patch improves the code generated on PA-RISC for DImode
(double word) left shifts by small constants (1-31). This target
has a very cool shd instruction that can be recognized by combine
for simple shifts, but relying on combine is fragile for more
complicated functions. This patch tweaks p
> > > gcc/
> > > PR target/88808
> > > * config/i386/i386.c (ix86_preferred_reload_class): Allow
> > > QImode data go into mask registers.
> > > * config/i386/i386.md: (*movhi_internal): Adjust constraints
> > > for mask registers.
> > > (*movqi_inter
From: Joe Ramsay
Hi,
Previously, the machine description patterns for vst1q accepted a generic memory
operand for the destination, which could lead to an unrecognised builtin when
expanding vst1q* intrinsics. This change fixes the pattern to only accept MVE
memory operands.
Tested on arm-none-e
Seemingly, the patch which caused this made it now to GCC 10;
at least it fails now with offloading on the OG10 branch, after
merging the trunk into that branch.
Hence, I committed this to GCC 10 to avoid this ICE. It occurs
here for libgomp.c/../libgomp.c-c++-common/reduction-16.c when
compiling
On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
>
> > > > gcc/
> > > > PR target/88808
> > > > * config/i386/i386.c (ix86_preferred_reload_class): Allow
> > > > QImode data go into mask registers.
> > > > * config/i386/i386.md: (*movhi_internal): Adjust constrain
On Fri, Aug 21, 2020 at 5:44 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > ping ^ 4, it's a very simple fix for ICE.
>
> OK, thanks. (Reviewing on the basis that I agree it's a simple rtx
> correctness fix.)
>
Thanks for the review.
> Richard
>
> >
> > On Mon, Aug 10,
On Fri, Aug 21, 2020 at 8:41 AM Hongtao Liu wrote:
>
> On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
> >
> > > > > gcc/
> > > > > PR target/88808
> > > > > * config/i386/i386.c (ix86_preferred_reload_class): Allow
> > > > > QImode data go into mask registers.
> > > >
On Fri, Aug 21, 2020 at 5:41 PM Hongtao Liu wrote:
>
> On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
> >
> > > > > gcc/
> > > > > PR target/88808
> > > > > * config/i386/i386.c (ix86_preferred_reload_class): Allow
> > > > > QImode data go into mask registers.
> > > >
OG10 = devel/omp/gcc-10
a GCC 10 branch with some additional OpenMP/OpenACC/offloading patches
I have cherry-picked the following GCC 11 patches,
related to OpenMP 5 features (newest commit first):
commit 8ec8095634cab5053da4c49935eeba13f2aee2fa
gcc/fortran/module.c: Fix indentation
(che
On Fri, Aug 21, 2020 at 11:50 PM Uros Bizjak wrote:
>
> On Fri, Aug 21, 2020 at 5:41 PM Hongtao Liu wrote:
> >
> > On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
> > >
> > > > > > gcc/
> > > > > > PR target/88808
> > > > > > * config/i386/i386.c (ix86_preferred_reload_class):
On Fri, Aug 21, 2020 at 9:29 AM Hongtao Liu wrote:
>
> On Fri, Aug 21, 2020 at 11:50 PM Uros Bizjak wrote:
> >
> > On Fri, Aug 21, 2020 at 5:41 PM Hongtao Liu wrote:
> > >
> > > On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
> > > >
> > > > > > > gcc/
> > > > > > > PR target/88808
>
On Fri, Aug 21, 2020 at 9:35 AM H.J. Lu wrote:
>
> On Fri, Aug 21, 2020 at 9:29 AM Hongtao Liu wrote:
> >
> > On Fri, Aug 21, 2020 at 11:50 PM Uros Bizjak wrote:
> > >
> > > On Fri, Aug 21, 2020 at 5:41 PM Hongtao Liu wrote:
> > > >
> > > > On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
>
On Sat, Aug 22, 2020 at 12:36 AM H.J. Lu wrote:
>
> On Fri, Aug 21, 2020 at 9:29 AM Hongtao Liu wrote:
> >
> > On Fri, Aug 21, 2020 at 11:50 PM Uros Bizjak wrote:
> > >
> > > On Fri, Aug 21, 2020 at 5:41 PM Hongtao Liu wrote:
> > > >
> > > > On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
>
This simple patch to match.pd optimizes away bit permutation
operations, specifically bswap and rotate, in calls to popcount and
parity. Although this patch has been developed and tested on LP64,
it relies on there being no truncations or extensions to "marry up"
the appropriate PARITY, PARITYL a
PR tree-optimization/21137 is now an old enhancement request pointing out
that an optimization I added back in 2006, to optimize "((x>>31)&64) != 0"
as "x < 0", doesn't fire in the presence of unanticipated type conversions.
The fix is to call STRIP_NOPS at the appropriate point.
I'd considered m
On Fri, Aug 21, 2020 at 9:46 AM Hongtao Liu wrote:
>
> On Sat, Aug 22, 2020 at 12:36 AM H.J. Lu wrote:
> >
> > On Fri, Aug 21, 2020 at 9:29 AM Hongtao Liu wrote:
> > >
> > > On Fri, Aug 21, 2020 at 11:50 PM Uros Bizjak wrote:
> > > >
> > > > On Fri, Aug 21, 2020 at 5:41 PM Hongtao Liu wrote:
>
On Fri, Aug 21, 2020 at 10:02 AM H.J. Lu wrote:
>
> On Fri, Aug 21, 2020 at 9:46 AM Hongtao Liu wrote:
> >
> > On Sat, Aug 22, 2020 at 12:36 AM H.J. Lu wrote:
> > >
> > > On Fri, Aug 21, 2020 at 9:29 AM Hongtao Liu wrote:
> > > >
> > > > On Fri, Aug 21, 2020 at 11:50 PM Uros Bizjak wrote:
> >
Hi Jose,
Proposed patch to PR94110 - Passing an assumed-size to an assumed-shape
argument should be rejected.
OK for master.
Thanks a lot for the patch!
Best regards
Thomas
On Sat, Aug 22, 2020 at 1:08 AM H.J. Lu wrote:
>
> On Fri, Aug 21, 2020 at 10:02 AM H.J. Lu wrote:
> >
> > On Fri, Aug 21, 2020 at 9:46 AM Hongtao Liu wrote:
> > >
> > > On Sat, Aug 22, 2020 at 12:36 AM H.J. Lu wrote:
> > > >
> > > > On Fri, Aug 21, 2020 at 9:29 AM Hongtao Liu wrote:
> > > > >
Hi Jose,
Proposed patch to PR95352 - ICE on select rank with assumed-size
selector and lbound intrinsic.
Patch tested only on x86_64-pc-linux-gnu.
Add check for NULL pointer before trying to access structure member,
patch by Steve Kargl.
this is OK, but you'll have to adjust your ChangeLog
On Fri, Aug 21, 2020 at 6:29 PM Hongtao Liu wrote:
>
> On Fri, Aug 21, 2020 at 11:50 PM Uros Bizjak wrote:
> >
> > On Fri, Aug 21, 2020 at 5:41 PM Hongtao Liu wrote:
> > >
> > > On Fri, Aug 21, 2020 at 9:15 PM Uros Bizjak wrote:
> > > >
> > > > > > > gcc/
> > > > > > > PR target/88808
>
This is my proposed fix to PR middle-end/87256 where synth_mult takes an
unreasonable amount of CPU time determining an optimal sequence of
instructions to perform multiplications by (large) integer constants on
hppa.
One workaround, proposed in bugzilla, is to increase the hash table used
to cach
Hi Roger,
On 2020-08-21 8:53 a.m., Roger Sayle wrote:
> I was wondering whether Dave or Jeff (or someone else with access
> to real hardware) might "spin" this patch for me?
This may be totally unrelated to this patch but I hit this error in stage2
testing your change:
build/genattrtab ../../gcc/
On 8/19/20 6:09 PM, Joseph Myers wrote:
On Wed, 19 Aug 2020, Martin Sebor via Gcc-patches wrote:
I think you need a while loop there, not just an if, to account for the
case of multiple consecutive cdk_attrs. At least the GNU attribute syntax
direct-declarator:
[...]
( gnu-attribu
On 8/20/20 4:22 PM, Marek Polacek wrote:
This patch implements C++20 P1009, allowing code like
new double[]{1,2,3}; // array bound will be deduced
Since this proposal makes the initialization rules more consistent, it is
applied to all previous versions of C++ (thus, effectively, all the way
On Thu, Aug 20, 2020 at 07:00:13PM -0300, Giuliano Belinassi wrote:
> This patch series add a new flag "-fparallel-jobs=" to control if the
> compiler should try to compile the current file in parallel.
[...]
> Bootstrapped and Regtested on Linux x86_64.
>
> Giuliano Belinassi (6):
> Modify gcc
On Mon, Aug 17, 2020 at 7:42 PM Dennis Zhang wrote:
>
>
> Hi all,
>
> This patch enables MVE vsub instructions for auto-vectorization.
> It adds RTL templates for MVE vsub instructions using 'minus' instead of
> unspec expression to make the instructions recognizable for vectorization.
> MVE targe
On Wed, Aug 19, 2020 at 10:32 AM Christophe Lyon via Gcc-patches
wrote:
>
> armv8-m.base (cortex-m23) has the movt instruction, so we need to
> disable the define_split to generate a constant in this case,
> otherwise we get incorrect insn constraints as described in PR94538.
>
> We also need to f
On Fri, Aug 21, 2020 at 2:28 PM Joe Ramsay wrote:
>
> From: Joe Ramsay
>
> Hi,
>
> Previously, the machine description patterns for vst1q accepted a generic
> memory
> operand for the destination, which could lead to an unrecognised builtin when
> expanding vst1q* intrinsics. This change fixes t
On Tue, Aug 18, 2020 at 5:03 PM Kewen.Lin wrote:
>
> Hi Bin,
>
> > I see, it's similar to the auto-increment case where cost should be
> > recorded only once. So this is okay given 1) fine predicting
> > rtl-unroll is likely impossible here; 2) the patch has very limited
> > impact.
> >
> Really
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