Re: [PATCH] [AVX512]For vector compare to mask register, UNSPEC is needed instead of comparison operator [PR96243]

On Tue, Aug 4, 2020 at 6:28 PM Kirill Yukhin wrote: > > On 04 авг 13:26, Kirill Yukhin wrote: > > Could you please clarify, how your patch relared to [1]? > > I see from the bug that it describes perf issue w.r.t. scalar > > operations. > Sorry for Typo, it's pr96243. https://gcc.gnu.org/bugzilla/

[PATCH] Power10: Add BRH, BRW, BRD support.

Power10: Add BRH, BRW, BRD support. The power10 processor adds 3 new instructions (BRH, BRW, BRD) that byte swaps half-words, words, and double-words within a GPR register. This patch adds support for these instructions. I have applied the suggestions from the previous times I have submitted thi

Re: [RISC-V] Add support for AddressSanitizer on RISC-V GCC

Hi Joshua, Jim: > > +/* Implement TARGET_ASAN_SHADOW_OFFSET. */ > > + > > +static unsigned HOST_WIDE_INT > > +riscv_asan_shadow_offset (void) > > +{ > > + return HOST_WIDE_INT_UC (0x1000); > > +} > > Is there a reason why you used 0x1000? > > Looking at other targets, it appears the conv

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