[ fixed $subject ]
On 7/3/20 7:20 PM, Roger Sayle wrote:
>
> The following patch adds support for three-input addition instructions to the
> nvptx backend.
> The PTX ISA's "vadd.u32.u32.u32.add d, a, b, c" instruction effectively
> implements 32-bit d = a+b+c,
> and the "vsub.u32.u32.u32 d,a,b
Hi Paul and Dominique,
The patch looks fine to me. If Dominique has nothing to report then it is
OK for trunk.
committed. Thanks!
Regards
Thomas
On Fri, 3 Jul 2020, Marek Polacek via Gcc-patches wrote:
> Pushed.
Nice. And thanks for doing this along the way. That's beneficial
for users/testers of GCC 11 as it evolves, and also helps not forget
things during the release process.
Gerald
Early ping.
> Gesendet: Montag, 29. Juni 2020 um 22:58 Uhr
> Von: "Harald Anlauf"
> An: "fortran" , "gcc-patches"
> Betreff: [PATCH] PR fortran/95980 - ICE in get_unique_type_string, at
> fortran/class.c:485
>
> Dear all,
>
> here's a couple of NULL pointer dereferences on invalid code.
>
> Reg
When cleaning out the multitude of patterns with unknown
coverage, this one went the way of the bathwater. It's use is
barely common enough to mark when diffing libgcc, and has a
minimal impact on performance-testsuites. Anyway, reinstated
with a couple of test-cases. It's suboptimal of gcc-core
The code in cris_select_cc_mode for selecting CC_NZmode was
partly inconsistent with the comment and partly seemed
ambiguous. I couldn't find a reason why I qualified selection
of CC_NZmode on the setting operation once a matching user was
spotted, so I just removed that. The cris.c update was du
Yet another misnumbering of operands: the asserted non-overlap
would be the only benign operands overlap. "Suddenly" exposed
by g++.dg/cpp0x/pr81325.C when testing unrelated changes
affecting register allocation.
To wit, operands 2 and 1 are the only ones that are safe for
overlap, it's only that
(The previous patch was also committed, FWIW, I just forgot to
mention it.)
Combine likes to change a zero-extension / and + shift as seen
in the test-case source to a logical shift followed by an and of
the shifted mask, like:
lsrq 1,r0
and.d 0x7f,r0
This was observed in the hot loop of corema
Currently this is using the macro prefix map without allowing the
---fmacro-prefix-map argument, which is arguably pretty weird... but I
don't know what would be a better way.
I think this remapping should happen with `file-prefix-map` but shouldn't
with `debug-prefix-map` (though if it happens fo
Sorry I think I accidentally had rich text mode on and also forgot the
`[PATCH]` in the title in the previous email... Try again...
Currently this is using the macro prefix map without allowing the
-fmacro-prefix-map argument, which is arguably pretty weird... but I
don't know what would be a bett
TL;DR: fixing a misdetection of what is a "simple move".
Looking into performace degradation after de-cc0 for CRIS, I
noticed combine behaving badly; it changed a move and a
right-shift into two right-shifts, where the "combined" move was
not eliminated in later passes, and where the deficiency ca
> I think this remapping should happen with `file-prefix-map` but
> shouldn't with `debug-prefix-map` (though if it happens for both it's
> also not too bad) and I believe this patch is the minimum change to
> achieve that. I think it makes sense to make this follow
> `macro-prefix-map` although I'
On Wed, 2020-07-01 at 18:29 +0100, Jonathan Wakely wrote:
> On 30/06/20 17:43 +0100, Jonathan Wakely wrote:
> > gcc/testsuite/ChangeLog:
> >
> > * g++.dg/analyzer/pr94028.C: Make operator new non-throwing so
> > that the compiler doesn't implicitly mark it as returning
> > non-null.
>
Hi:
This patch is about to support Intel Advanced Matrix Extensions (AMX)
which will be enabled in GLC.
AMX is a new 64-bit programming paradigm consisting of two
compo nents: a set of 2-dimensional registers (tiles) representing
sub-arrays from a larger 2-dimensional memory image,
and an acceler
Most comments, including the second sentence in the head comment
of combine_validate_cost, the main decision-maker of the combine
pass, refer to the function as returning true if the new
insns(s) *cheaper* than the old insns, when in fact the function
returned true also if the cost was the same. R
For extracting high part element from DImode register like:
{%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}
split it before reload with "and mask" to avoid generating shift right
32 bit then shift left 32 bit.
srdi 3,3,32
sldi 9,3,32
mtvsrd 1,9
xscvspdpn 1,1
=>
rldicr 3,3,0,31
mtvsrd 1,3
x
Hi Harald,
Early ping.
OK. Thanks for the patch!
Regards
Thomas
Hi Harald,
OK for master / backports?
OK. Thanks for the patch!
Regards
Thomas
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